JPS61265646A - Memory addressing system - Google Patents

Abstract

PURPOSE:To simplify an address generating circuit, and to reduce the quantity of hardware by providing a RAM which has areas corresponding to plural areas of a memory, respectively, and stores an address of the corresponding area of the memory in each area. CONSTITUTION:The titled system is provided with a RAM 102 which has areas corresponding to plural areas of a memory 101, respectively, and stores an address of the corresponding area of the memory 101 in each area. By an address which has been read out of this RAM 102, the memory 101 is read out, and also, whenever it is read out, the address which has been stored in the RAM 102 is stepped by a stepping circuit 103, by which from the memory 101 which has stored data in plural addresses in plural areas, respectively, a head address in each area is set optionally and the data is read out cyclically. In this way, the constitution of an address generating circuit is simplified, and the quantity of hardware is reduced.

Description

[Detailed Description of the Invention] [Summary] A RAM is provided, which has areas corresponding to a plurality of areas of the memory, and each area stores the address of the corresponding area of the memory. By reading the memory and incrementing the address stored in the RAM with each read, the start address in each area is arbitrarily set from the memory in which data is stored at multiple addresses in each of the multiple areas. To enable cyclic data reading.

[Industrial application field]

The present invention relates to a memory addressing method for accessing memory, and more particularly to a read address generation method for cyclically reading a memory space consisting of a plurality of regions while sequentially stepping within each region. be.

When providing voice guidance via an extension telephone in a hotel or the like, a service format is often used in which a plurality of types of messages are registered in advance, and one of these is arbitrarily selected and sent to the telephone line.

Conventionally, for this purpose, a method of selecting a message recorded on tape, playing it, and transmitting it was generally used, but as private branch exchanges (PBXs) became digital, this method was used. Therefore, such voice messages are also digitized and registered in memory as PCM signals, which are then read out and played back in a time-sharing manner, thereby providing voice services as described above. became.

FIG. 4 conceptually explains a method for time-divisionally reading out a plurality of types of digitized voice messages registered on a readout memory (ROM).

In the same figure, (cL) indicates the contents of EOM, and 1-1
1-fi, +, . . . 1-2 are 2 areas of the ROM 1, and for example, 8-bit data is recorded in each area corresponding to 2' addresses. (b) is RO
M output is shown, TS1, TS2 . ......, T.S.
2” ld 2 O time slots. Each R
There is an address circuit (not shown) corresponding to the OM area, and each address circuit sequentially advances every frame to sequentially designate the address of the area to the corresponding ROM, and when a certain point "initial value + 2J" is reached, By returning to the initial values, it is possible to send messages in each area to the PBX in a time-sharing manner.With PFIX, these are separated for each time slot, demodulated, reproduced audio, and sent to each area via the telephone circuit. In Fig. 4(b), A, E,
.......

X is R specified by the contents of different address circuits.
OM data is shown.

It is desired that the read address generation method for the memory in such a case be implemented with as little hardware as possible.

[Conventional technology]

FIG. 5 shows a conventional memory addressing system. N-1y11-2p..., 11-
2? L is 2? L i-bit counters, 12-1.12
-z+..., 12-2'' are 2' j-bit registers, and these constitute 2f'' address circuits from N111 to Nα2' by having the same subscript. . 13 is a selection circuit which sequentially selects 2f'' address circuits according to the output of the rubit counter 14 and connects them to the read memory (ROM) 15.

FIG. 6 shows an operational diagram of the memory addressing method of FIG. 5. Below, the operation of the memory addressing method shown in FIG. 5 will be briefly explained using FIG.
-1 outputs the fixed part A of the address, and the i-bit counter 12-1 outputs the increment parts α, +j,
aH+2. By outputting...
Address A+α8. A ten α, +1. A+α, +2.・・・
7 rem m, m+1. m+2. Outputs sequentially in response to... Similarly, the N112 address circuit has a fixed part B defined by the j-bit register 12-1, and (
An increment portion determined by the bit color ratio 11-2.

α! +L 6*+2p... Address B+α2. B tena @ +1, E+al +2. −
are sequentially output, and N(12' address circuit consists of a fixed part X and an incremental part αr, α-+1.αr+2...
Outputs ・J times.

The selection circuit 13 selects each address circuit Nu1. N112.
....

Sequentially select the output of [2f'' for each time slot,
It is given to the ROM 15 as an address. The fixed parts of the address A, E, ......, is specified in a fixed manner, and the increment portion specifies 2' addresses in each area and reads out, for example, 8-bit data stored at each address and outputs it.

In this case, the data in each area usually needs to be read out sequentially from the beginning, so when a control unit (not shown) instructs to read a message, the initial value of the incremental part of the address is specified together with the fixed part. The message area and its address initial value are specified by reading the data into each register and counter in accordance with the initial value setting timing and timing signal.

[Problem that the invention seeks to solve]

The conventional memory addressing system shown in FIG. 5 consists of a register and a counter corresponding to each area in order to specify each area of the ROM and obtain an address that increments sequentially within each area. requires an address circuit,
The amount of nodeware increases. In particular, if the message stored in each area is long, the capacity of the counter to increment and specify the address increases, which increases the amount of node hardware and creates a heavy burden both in terms of space and economy. There was a problem.

The purpose of the system of the present invention is to provide a memory addressing system that can solve the problems of the prior art and reduce the amount of hardware.

[Means for solving problems]

FIG. 1 shows the basic configuration of the system of the present invention.

A memory 101 is composed of a plurality of areas, and each area stores data corresponding to a plurality of addresses.

102 is a RAM, which is stored in the area of the memory 101.
It has a plurality of areas corresponding to it, and each area has a memory 101.
The address of the corresponding area is stored.

Reference numeral 105 is an increment circuit that increments the address in RAA (102) every time it is read.

[For production]

In the memory addressing scheme of the present invention, RAM10
2 and reads the address stored in memory 101.
Since the address is given as an address and the address is incremented each time it is read, the start address in each area of the memory 101 can be arbitrarily set and each area can be read out cyclically.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the memory addressing system of the present invention, in which 21 is a rubit counter, 22 and 23 are selection circuits, and 24 is a read/write memory (RAM). 25 is a holding circuit that holds the output of the RAM 24 for each time slot period. Reference numeral 26 denotes a read memory (ROM), the contents of which are read out using the output of the holding circuit 25 as an address. 27 is an i-bit counter, and 28 is an OR circuit. The selection circuit 22 selects the output of the 1-bit counter 21 and the information specifying the initialization target from the control section (not shown), and selects
The selection circuit 23 selects either the combination of the output of the bit counter 27 and the output of the holding circuit 25, or the initial value information from the control section, and inputs it to the RAM 24.

FIG. 3 shows an operational diagram of the memory addressing scheme shown in FIG.

The operation of the memory addressing system shown in FIG. 2 will be explained below using the operation diagram shown in FIG.

The n-bit counter 21 counts up in accordance with the clock, and the n-bit counter 21 counts up each time slot TS1 . T
S'l,..., corresponding to TS2'','
0",'1",...

・Generates "2 outside - 1". Each selection circuit 22 and 23 switches the first half of each time slot to the counter side and the second half to the control section side according to the selection circuit switching signal. As a result, the selection circuit 22 is time slot TS1.
TE12. ......, corresponding to TS2", IO
″、′1″.

......, RAAf24 with 2'-1 as address
give to

The RAM 24 has addresses O to 2t''-1 (s+
/) Data is stored in bit width, and selection circuit 2
It is read out according to the address given from 2.

Now, as shown in FIG. 3, in a frame, time slot TS1. TS2. ------, TS2
”, A+al, B+at, ・=, X+
Let it be a-. The data read from the RM 24 is held in the holding circuit 25 for each time slot period according to the holding qt. The output of the holding circuit 25 is given to the ROM 26 as an address, and the ROM 26 thereby stores the fixed part A.

E, . . . , X respectively in the areas 26-1.
26-It...

26-2j is specified, and the step part '1*Ls
*e...r('2' specifies an address within each area, and reads and outputs the 8-bit data stored at that address.

On the other hand, the increment portion of the output of the RAM 24 is simultaneously set in the bit counter 27 by the holding clock, but since the increment clock is subsequently applied, its contents are incremented by one. For example, in time slot TS1 in FIG. 3, the contents of the i-bit counter 27 are from α, to α, +
Changes to 1. The selection circuit 23 outputs this in the first half of the selection period, but an update timing signal is input from a timing section (not shown) via the OR circuit 2B.
RAJy as a write control signal (write strobe signal)
Since it is given to f24, the data in RAM24 is A+6.
1 will be rewritten as A+81+1. This data is read out in time slot TS1 in the next frame +1.

Since this kind of data update is performed for each frame for each time slot, data is updated from RAM 24 to ROM 2.
6 is given an address that increments sequentially for each area.

Different messages are pre-registered in each area of the ROM 26, and the PBX arbitrarily selects these messages and gives them to a telephone with an arbitrary number, so it is necessary to read them at an arbitrary time slot. The specification of and the initial value within the area are performed as follows.

Now, when the control unit specifies an arbitrary area in the ROM 26, for example, z6-2, and attempts to read it in any time slot, for example, TS2, 11'' is passed through the selection circuit 22 as initialization target specification information. is given, the address corresponding to time slot TS2 in the RAM 24 is given.At the same time, when an initial value consisting of a fixed part and an incremental part is given via the selection circuit 23, an initialization instruction signal is given via the OR circuit 28. When the selection circuit switching signal is used as a write control signal, the content corresponding to the specified address in the RAM 24 is rewritten with the initial value and initialization is performed. This is done in the shaded area where the side is selected and designated.

In this way, any area of the ROM 26 can be read out at any time slit. In this case, in order to read out the messages in each area from the beginning, the increment portion given as the initial value is The first address value may be set to 0, for example.

〔Effect of the invention〕

As explained above, according to the memory addressing method of the present invention, a RAM is provided which has areas corresponding to a plurality of areas of the memory and each area stores the address of the corresponding area of the memory, and reads from this RAM. Since the memory is read based on the issued address, the configuration of the address generation circuit for cyclically reading the memo space consisting of multiple areas while stepping in each area is simplified, and the amount of hardware is reduced. is reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the system of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a diagram showing an operation diagram of the embodiment shown in FIG. 2. , Fig. 4 is a diagram conceptually showing a method for reading out digitized voice messages in a ROM in a time-sharing manner, Fig. 5 is a diagram showing a conventional memory addressing method, and Fig. 6 is a diagram showing the memory of Fig. 5. - It is a diagram showing an operation diagram of the addressing method. 21...n-bit counter, 22.23...selection circuit, 24...write/read memory (L4M), 25...
...Holding circuit, 26...Reading memory (ROM) 1.27...1
Bit counter, 28...OR circuit.

Claims (1)

[Claims] For a memory (101) space consisting of a plurality of areas and storing data corresponding to a plurality of addresses in each area, the start address of each area is arbitrarily set and each area is cycled. In the read address generation method for reading data, a RAM having a plurality of areas each corresponding to an area of the memory (101) and storing an address of a corresponding area of the memory (101) in each area.
(102); and an increment circuit (103) that increments the address in the RAM (102) each time it is read.