JP3389386B2 - Video signal processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device, and more particularly to, for example, a frame switch circuit which reads a plurality of camera input video signals from a memory and outputs them in a time division manner, and outputs the output video signals continuously or intermittently. The present invention relates to a video signal processing device including a time-lapse VTR capable of time-lapse recording.

[0002]

2. Description of the Related Art A conventional video signal processing apparatus of this type is constructed by integrating or combining a frame switch circuit for switching a plurality of video signals and outputting in a time division manner and a time lapse VTR, and writing and reading are asynchronous at the same time. Synchronize by recording multiple input video signals in the memory that can be implemented in, writing the video signals in synchronization with the input video signals, and reading from the memory according to the synchronization signal from the independent synchronization signal generator. I was doing

[0003]

However, the above-mentioned video signal processing device has a drawback that a signal during reading is overtaken by writing and reading, resulting in a so-called cut-out image. For this reason, the video signal cannot be output in a time division manner when the time lapse mode in which the recording interval is short is set.

Further, in order to switch a plurality of asynchronous video signals on a field-by-field basis in synchronization with each other, a memory of two or more fields is required and high-speed switching is generally performed every three fields. In order to switch at high speed, a large amount of memory and peripheral circuits are required, and there is a drawback that the cost becomes high. Therefore, a main object of the present invention is to provide a video signal processing device capable of improving the visibility of an image in the time-lapse mode as much as possible and increasing the switching speed with a simple circuit configuration.

[0005]

SUMMARY OF THE INVENTION According to the present invention, there are provided frame switch means for storing a plurality of input video signals in a memory for each field and outputting them in a time division manner, and intermittently by thinning out the input video signals in the time direction. In a video signal processing device including a time-lapse means for storing in a memory, the time-lapse means includes a write control means for outputting a control signal for restricting writing to the memory from an input video signal or a reference sync signal from a sync signal generator. The video signal processing device is characterized in that a control signal from the writing control means is inputted to the frame switch means to control the memory.

[0006]

When the time-lapse mode is set, the second input video signal selected by the second selecting means is input to the adder, and the composite sync signal from the sync signal generator and the input video signal are added. This second video signal is given to the time-lapse VTR after the camera number is added. Then, the vertical synchronizing signal (VD) is taken out from the second video signal in the video circuit, and the writing control means outputs the writing control signal (WMW) from the synchronizing signal (VD) and the ROM pattern for each mode from the syscon. Recording control signal (REC GATE) that determines the time-lapse recording cycle
To generate.

The write control signal (WMW) and the recording control signal (REC GATE) are supplied to the frame switch means, and the input video signal is written in the memory according to the write control signal (WMW). That is, the recording control signal (R
The writing to the memory is controlled before the recording timing by EC GATE). On the other hand, when the continuous recording mode is set, the first selection means selects the first input video signal (main signal) from the plurality of input video signals, and the second selection means reads the second video signal from the memory.
Vertical sync signal (V) of the main signal to the input video signal (slave signal)
D) is added. The first video signal (main signal) and the second video signal (slave signal) are alternately switched by the switching means and input to the time-lapse VTR.

Then, in the servo circuit of the time-lapse VTR, the vertical synchronizing signal (VD) is taken out and the write control signal (WMW) is generated from this synchronizing signal (VD). The write control signal (WMW) is given to the frame switch means, and writing and reading of the input video signal are controlled according to the control signal.

[0009]

According to the present invention, the frame switch means controls the writing to the memory on the basis of the write control signal from the time-lapse means, so that the overtaking of writing and reading can be prevented. Also, a video signal (main signal) to be recorded is determined from among a plurality of input video signals, and the main signal and a video signal other than the main signal (slave signal) are alternately switched for each field and output. Since this is done, high-speed switching becomes possible.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the detailed description of the embodiments below with reference to the drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a video signal processing apparatus 10 of this embodiment includes a frame switch circuit 12 for time-compressing and multiplexing, for example, a luminance signal and a chrominance signal in one line of an input video signal, for example. Time-lapse V that can be recorded intermittently, such as recording once in 3 fields
And TR14. As shown in FIG. 1, the frame switch circuit 12 and the time-lapse VTR 14 are interfaced so that signals can be exchanged with each other.

The plurality of video signals input from the input terminal 16, that is, the video signals from the cameras 1 to 4 are the first selector 18 and the second selector 2 in this embodiment.
Given to 0. The first selector 18 and the second selector 20 selectively output one of the plurality of video signals by the microcomputer 22 (memory controller 28). The input video signal selected by the first selector 18 is A / D
The digital signal is converted by the converter 24 and the vertical sync signal (VD) is given to the sync separation circuit 26. The vertical synchronization signal (VD) controls the writing to the field memory 32.
8 and ODD / EVEN discrimination circuit 30.
The memory controller 28 generates a write address for writing the digitally converted input video signal into the field memory 32, and the video signal selected by the first selector 18 according to the write address is stored in the field memory 32.
Recorded in. The ODD / EVEN discriminating circuit 30 discriminates between an odd (ODD) field and an even (EVEN) field.

On the other hand, the input video signal selected by the second selector 20 is supplied to the sync separation circuit 34 and is also input to the changeover switch 36 to change the changeover switch 36.
And the second video signal selected by the first selector 18
The video signal selected by the selector 20 is switched. The video signal input to the sync separation circuit 34 is sync-separated and a vertical sync signal (VD) is taken out. The sync signal (VD) is read out from the memory controller 28 and the field memory 32 via the changeover switch 38. Is provided to the memory controller 40 for controlling the.

A vertical synchronizing signal (V
D) is input to the adder 42, in which the first selector 18 converted into analog by the D / A converter 46
The vertical synchronizing signal (VD) is added to the output video signal from the. When the time-lapse VTR 14 selects the time-lapse mode, the changeover switch 38 is connected to the H terminal side, the composite sync signal from the sync signal generator 44 is changed to the vertical sync signal (VD), and the memory controllers 28 and 40. It is given to the adder 42.

The video signal selected by the changeover switch 36 is added with the camera number (ID) by the encoder 48 and is given to the video circuit 50 of the time-lapse VTR 14. The video circuit 50 extracts the vertical synchronizing signal (VD) from the video signal, and the synchronizing signal (VD)
The servo circuit 52 generates a write control signal (WMW) and a recording control signal (REC GATE) that determines a recording cycle in the time-lapse mode according to the control signal for each mode from the system controller 54.

That is, referring to FIG. 2, the mono-multi circuit 58 delays the vertical synchronizing signal (VD) so that the recording control signal (RECGATE) is switched before the vertical synchronizing signal (VD). Generate a signal (MM). The signal (MM) is, for example, the D flip-flop 6
0a, 60b and 60c are input to a ternary ring counter, so that each D flip-flop outputs signals Q ₁ , Q ₂ and Q as shown in FIG.
₃ is output. AND gates 62a and 6
2b, and the OR gate 64 generates the write control signal (WMW) shown in FIG.

A recording control signal (RECGATE) that determines the recording period in the time-lapse mode is given to the video circuit 50 and the frame switch circuit 12 via the changeover switch 66a. The recording control signal (REC GATE) is a signal obtained by toggling the write control signal (WMW). When the continuous recording mode is set, the changeover switches 66a and 66b are connected to the L terminal side, and the write control signal (WMW) divides the output signal (MM) from the mono-multi circuit 58. Generated by.

As described above, the write control signal (WMW) and the recording control signal (R) generated in the servo circuit 52.
EC GATE) is given to the microcomputer 22 of the frame switch circuit 12, whereby the microcomputer 22 determines the mode of the time-lapse VTR 14 and outputs a control signal corresponding to each mode. That is, with reference to FIG. 4, the microcomputer 22 determines in step S1 when the power is turned on, a time counter and SW OUT which are not shown.
Reset the counter. This time counter is
Is a counter that counts how many times the routine for viewing SW OUT in steps S5 to S21 shown in FIG. 6 is used. The SW OUT counter is a time-lapse VTR.
It is counted how many times SW OUT, that is, the recording control signal (REC GATE) output from 14 is input to the frame switch circuit 12.

Subsequently, in step S3, it is determined whether the mode setting information by the key input is the playback (PB) mode or the recording (REC) mode. If it is the recording mode, SW OUT is set in step S5. To be detected. In the playback mode, key input information, that is, camera selection and PB / REC re-input information and the like are fetched again in step S23, and data corresponding to this key input information is output in step S25.

When the recording mode is set by the key input, the time counter is incremented in step S7 of FIG. 5 and the SW OUT (REC GA) is applied to the frame switch circuit 12 in step S9.
TE) is input. When the recording control signal (REC GATE) is at a high level, for example, the microcomputer 22 judges that "there is an input", and step S11
The SW OUT counter is incremented with. Then, in step S13, it is determined whether the count value of the time counter is 10 times (100 msec),
If "YES", the count value is reset in step S15.

Subsequently, in step S17, it is determined whether the SW OUT counter is "1" or more, and the count value (NS
When W) is "1" or more, the microcomputer 22 determines that the time-lapse mode is set, and the time-lapse bit (flag) is set to "H" in step S21. When the count value is "0", the flag bit of the time lapse is set to "L" in step S19.

In this way, SW OUT (REC GAT
The recording pattern is determined by counting the interval E). Then, in step S23, the key input is taken in again and the bit (flag) is set, and thereafter, in step S25, data (bit) such as mode information and camera selection number is output to the memory controller 28. The processing in steps S1 to S25 above is 10 msec.
It is carried out at intervals of.

The serial data such as the mode information or the camera selection number output from the microcomputer 22 is input to the memory controller 28 and used as each mode signal for switching the mode in the gate array. That is, FIG.
With reference to, the serial data from the microcomputer 22 is converted to parallel by the serial / parallel converter 68 and recorded in the register unit 70 composed of a plurality of registers.

For example, when the data specified by the time-lapse mode is given from the microcomputer 22 to the memory controller 28, the write control signal (WMW) is selected by the first selector 18 in the D flip-flop 72a. The vertical synchronizing signal (VD) of the video signal is used as a latch signal,
Latch retained. The output signal (WMW) from the D flip-flop 72a is the output signal of the EX OR gate 76 that receives the signal (O / E) output from the ODD / EVEN discrimination circuit 30 and the signal (O / E) for writing. Together with OR gate 74. Therefore,
As shown in FIG. 7, the OR gate 74 outputs an enable signal (WE) for permitting writing to the memory 32. The write signal (O / E) is divided at the rising edge of the enable signal (WE). This enable signal (WE) is input to, for example, a 2-bit binary counter 82, and the first selector 18 is switched according to the output signal from this counter 82.

On the other hand, when the continuous recording mode is designated, the changeover switches 80a-80d shown in FIG. 6 are changed over to the L terminal side, and the D flip-flop 72a outputs the write control signal (WMW) to the vertical synchronizing signal (VD). ) To latch and hold to generate an enable signal (WE). Further, the write control signal (WMW) is given to the changeover switch 36, and the video signal read from the field memory 32 and the output signal of the first selector 18 passing through the memory 32 are switched.

In operation, for example, 1 in 3 fields
When the time-lapse recording mode for recording once is set, the composite synchronizing signal output from the synchronizing signal generator 44 is given to the adder 42 via the changeover switch 38, and the adder 4
In 2, the input video signal selected by the first selector 18 and the composite sync signal are added. Then, this video signal is given to the encoder 48 via the changeover switch 36, and after the camera number (ID) is added, it is inputted to the time-lapse VTR 14.

The video signal input to the time-lapse VTR 14 is supplied to the vertical synchronizing signal (V
D) is taken out. The vertical synchronizing signal (VD) and the control signal set by the system controller 54 for each mode are given to the servo circuit 52, where the write control signal (W
MW) and a recording control signal (REC GATE) are generated (see FIG. 7). These two control signals are given to the microcomputer 22 and the memory controller 28 of the frame switch circuit 12, and the memory controller 28 generates a switching signal for switching the first selector 18. This switching signal is, as shown in FIG. 7, a recording control signal (RE
C GATE) changes at the rising edge of the vertical synchronizing signal of the video signal selected by the first selector 18 during the low level period.

Then, as described above with reference to FIG. 6, the enable signal (W
According to E), the output video signal from the first selector 18 is written in the field memory 32. That is, in this embodiment, the ODD / EVEN discriminating circuit 30 discriminates the ODD / EVEN of the video signal so that the video signal of the ODD field and the video signal of the EVEN field alternate and the write control signal. It is written to the memory 32 while (WMW) is in the low level period.

Therefore, as shown in FIG.
2 has a camera A corresponding to the second ODD field.
Signal, camera B signal of the second EVEN field, 2
The camera C signal of the th ODD field is written in order. Moreover, the writing to the memory is executed before the recording timing by the recording control signal (REC GATE). Therefore, overwriting of writing and reading in the field memory 32 can be prevented.

Then, the video signal is read from the field memory 32 in accordance with the vertical sync signal (VD) from the video circuit 50 (sync signal generator 44). The read video signal is added to the composite sync signal and the camera number (ID), and then input to the video circuit 50. There, a recording control signal (RE
According to C GATE), as shown in FIG.
A video signal is recorded on a magnetic tape (not shown) once in the field.

When the continuous recording mode is set, the desired one input video signal is selected from the plurality of input video signals by the second selector 20. This one input video signal is a signal (main signal) to be recorded most preferentially among a plurality of input video signals, and is selected by the operation key. From the first video signal (main signal) selected by the second selector 20 (first selection means), a vertical synchronizing signal (VD) is taken out by the sync separation circuit 34, and the vertical synchronizing signal (VD) and the first selector are selected. The adder 42 adds the second input video signal (slave signal) other than the main signal selected by 18 (second selection means). This video signal is input to the encoder 48 via the changeover switch 36, and the camera number (ID) is added thereto. This video signal is input to the video circuit 50 of the time-lapse VTR 14, the vertical synchronizing signal (VD) is taken out, and the servo circuit 5 is based on this vertical synchronizing signal (VD).
2 generates a write control signal (WMW). This write control signal (WMW) is supplied to the microcomputer 22 and the memory controller 28 of the frame switch circuit 12, and the writing to the field memory 32 is controlled based on this control signal.

That is, as shown in FIG. 8, when the write control signal (WMW) is at the low level, the rising edge of the vertical synchronizing signal of the second video signal selected by the first selector 18 indicates the write memory gate (WMG). When the write control signal (WMW) becomes high level, the second video signal is read from the field memory 32.

The second selector 2 is added to the read second video signal.
A main signal selected by 0, that is, a vertical synchronizing signal (VD) of the first video signal is added, and the second video signal (slave signal) and the first video signal (main signal) selected by the second selector 20.
And are alternately switched by the changeover switch 36.
Therefore, the main signal selected by the second selector 20 is
Switching is performed for each field, and switching is performed so that the sub-signals selected by the first selector 18 are sequentially inserted into one field in between. Therefore, 4 as in this embodiment
When two video signals are input, the main signal is recorded once in two fields, and the remaining three signals (slave signals) are each recorded once in six fields. Switching is possible at three times the speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a servo circuit of the embodiment in FIG.

FIG. 3 is a timing diagram showing an operation in the servo circuit shown in FIG.

FIG. 4 is a flowchart showing the operation of the microcomputer of FIG. 1 embodiment.

5 is a flowchart showing the operation of the microcomputer of FIG. 1 embodiment.

FIG. 6 is a block diagram showing an example of a memory controller of FIG. 1 embodiment.

FIG. 7 is a timing chart showing an operation when the time-lapse mode is set in the embodiment of FIG.

FIG. 8 is a timing chart showing an operation when a continuous recording mode is set in the embodiment of FIG.

[Explanation of symbols]

10 ... Video signal processing device 12 ... Frame switch circuit 14 ... Time-lapse VTR 18 ... 1st selector 20 ... Second selector 22 ... Microcomputer 28 ... Memory controller 32 ... Field memory 36 ... Changeover switch 44 ... Synchronous signal generator 50 ... Video circuit 52 ... Servo circuit 54 ... Syscon

Claims (4)

(57) [Claims] 1. A frame switch means for storing a plurality of input video signals in a memory for each field and outputting them in a time division manner, and a time lapse means for thinning out the input video signals in the time direction and intermittently storing them in the memory. In the video signal processing device, the time lapse means includes write control means for outputting a control signal for restricting writing to the memory from the input video signal or a reference sync signal from a sync signal generator, A video signal processing device, characterized in that the control signal from the embedded control means is input to the frame switch means to control the memory. 2. The frame switch means includes a first selecting means for selecting a desired first input video signal from the input video signals, and a second selecting means for selecting a second video signal other than the first input video signal. 2. The video signal processing device according to claim 1, further comprising a selection unit and a switching unit that alternately switches the first video signal and the second video signal read from the memory for each field. 3. The frame switch means includes a mode discriminating means for counting a recording control signal for determining a recording cycle in the time-lapse recording mode.
The described video signal processing device. 4. The frame switch means includes means for discriminating ODD / EVEN of the input video signal, and ODD
4. The video signal processing device according to claim 1, wherein the input video signal is written in the memory based on the / EVEN discrimination result and the control signal.