KR920003367B1 - Memory device for video printer - Google Patents

Abstract

The memory circuit for editing two screens by using a memory to arrange the scenes by a user comprises first and second screen selection switches (SW1,SW2), a number of mode selection switches (SW3-SWn), a microcomputer (11) for receiving horizontal and vertical sync. signals to generate horizontal and vertical address control signals (S1,S2) and reading a second horizontal address from an internal memory to output it, a comparator (9) for comparing the second address with a first horizontal address from a memory controller (8) to generate a coincidence signal (S1), and a memory enable controller (17) for logic-operating the coincidence signal and first and second image memory control signals to generate an image memory (3) enable signal (S4).

Description

Memory device of video printer

1 is a conventional block diagram.

2 is a block diagram of the present invention.

3 is an exemplary view of image editing according to the present invention.

4 is a flow chart of the present invention.

* Explanation of symbols for main parts of the drawings

1: Decoder 2: Analog / Digital Converter

3: image memory 4: memory selection switch

5 line memory 6 control means

7: recording unit 8: memory control unit

9 comparison unit 10 print control unit

11: micom 12: digital analog converter

13: monitor G1: Oagate

G2: End gate SW1, SW2: Screen selector switch

SW3... SWN: Mode selector switch

The present invention relates to a screen data memory circuit for screen editing in a video printer.

In general, a video printer apparatus has been proposed in response to the necessity of printing an image recording content to be reproduced on a monitor through a recording apparatus such as a still camera or a recording of an image by instantaneous capture of an image signal.

In the conventional case, when the video signal is input as shown in FIG. In addition, when the memory command signal is applied to the memory command input terminal 11, the memory control unit 8 generates a sampling pulse to the analog / digital converter 2 in accordance with the vertical and horizontal synchronization signals. The analog digital converter 2 converts analog R, G, and B signals into digital a, G, and B signals for each a bit in accordance with the sampling pulse. The digitized R, G, and B signals are recorded in the image memory 3 in accordance with the write address designated by the memory control section 8. At this time, the reason why the digital R, G, and B signals are written to the image memory 3 once is due to the difference between the speed of the video signal and the printing speed. When a print command input signal is input to the print control unit 10 after the memory function is completed, the print control unit 10 applies a read address to the image memory 3 and writes a write address to the line memory 5. Select the memory selection switch. On the other hand, in order to print R, G, and B three-color signals on recording paper, it is necessary to convert them into three colors of yellow (Y), cyan (C), and magenta (M). In order to convert data into three colors Y, M, and C, one line is sequentially memorized in the line memory 5 by a memory selection switch, and then, the memory is again controlled by the print control unit 10. The stored data is transferred to the control means 6.

The control means 6 sequentially changes the R, G, and B signals to Y, M, and C signals, and at the same time reduces the effect of density change due to the correlation between the characteristics of the recording paper and the amount of heat generated by the head. After performing resistance compensation to reduce the resistance deviation of the heating element of each of the opening heads, heating data is applied to the recording head of the recording unit 7 in the order of Y, M, C three colors, and printing is performed one line by one line. To complete. However, in the case of printing as described above, the video signal of one field or one frame is received and recorded in the image memory 3, and then printed. Therefore, the printing is performed in a continuous operation such as a pitcher's pitching operation. It was easy to implement a multi-screen printing method for recording and indexing the entire disc recording contents by a video camera, but the user would like to place his portrait in the middle and place a landscape image in the background around the portrait. In case of changing the surrounding background on one screen, image editing is difficult. Accordingly, an object of the present invention is to provide a memory circuit that allows a user to randomly arrange images by editing two screens using a memory.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of the present invention, in which the following parts are added in the same configuration as in FIG. That is, a digital / analog converter 13 for analogizing R, G, and B digital data output from the image memory 3, a monitor 12 for outputting the analogized video signal, and first and third Inputs the screen selection switches SW1 and SW2, the plurality of mode selection switches SW3 to SWN, and the horizontal and vertical synchronization signals separated from the video signal, and the first and second screens according to the first and second screen selection states. A microcomputer 11 which generates two image memory control signals S1 and S2 and reads and outputs a second horizontal address from an internal memory according to the mode selection state, and is generated from the second horizontal address and the memory controller 8. A comparison unit 9 generating a matching signal S1 of a predetermined state and a matching operation of the matching signal S1 and the first and second image memory control signals by performing a logical operation Memory in which the enable signal S5 is generated. It is configured by further adding the block controller 17.

3 is a diagram illustrating screen editing according to mode selection according to the present invention, and FIG. 4 is a flowchart of the present invention.

The present invention will be described in detail based on the above configuration.

When the video signal is input to the decoder 1, the decoder 1 performs R, G, B separation and synchronous separation. Here, the separated vertical and horizontal synchronization signals are input to the memory control unit 8 and the microcomputer 11, where the microcomputer 11 is first shown in step (a) as shown in the flowchart of FIG. 4. 2Read the corresponding port to check whether the switch (SW1, SW2) is ON. After performing step (a), if it is found in step (b) that the first switch SW1 is in a state, the image memory 30 is enabled. If it is found in step (b) that the first switch SW1 is in the off state, the process proceeds to step (c) to check whether the second switch SW2 is in the on state in order to check whether two screen edits are selected. If the second switch SW2 is not in the ON state, the operation loops to step (a). If the second switch SW2 is in the ON state, the third switch SW3 is first checked for the mode check in step (d).

In this case, if the third switch SW3 is not in the ON state, starting from step (q), the state of the remaining switches may be checked and the mode may be checked, but here, only the case where the third switch SW3 is found to be in the ON state will be described. It is assumed that the mode according to the ON state of the third switch SW3 is a mode having an output form as shown in FIG. Therefore, when the third switch SW3 is turned on in step (d), the microcomputer 11 reads the vertical synchronization signal input port in step (e) and detects whether the vertical synchronization signal is input in step (f). If it is determined that the vertical synchronization signal has been input, the process proceeds to step (g) to reset the address value (x). After performing step (g), in step (h), the microcomputer 11 reads the horizontal sync signal to determine whether the horizontal sync signal is detected in step (i). If it is determined that the horizontal synchronization signal is detected, the process proceeds to step (j) to increase the address value by 1 (n = x + 1), and then, in step (k), the address value is a value between the vertical addresses in a predetermined range (M <x < M + β). If the check result does not belong to a certain range, in step (p), it is checked whether the address value is 256, and if it is 256, the memory operation for one screen is completed.

On the other hand, if it is within the range, it proceeds to step (I) to set the second output port to generate an image memory enable signal, and (m) reads the microcomputer 11 internal memory in step (n) and the comparator 11 in step n. ) Outputs the second horizontal address and loops to step (h). The second horizontal address is generated by a certain format for image editing recorded in the microcomputer 11 internal memory.

Here, the operation of each part of the system according to the control flow of the microcomputer 11 will be described. In the comparator 9, the first horizontal address currently being processed from the memory control unit 8 is inputted, and the microcomputer 11 performs the above-described operation. As described above, assuming that the address is Y by inputting the second horizontal address, K &lt; Y &lt; The comparator performs a window detection operation. If the result of the check matches, the matching signal S1 in the low state is output. At this time, the AND gate G2 is a result of performing an AND operation on the image memory enable control signal S20 generated from the microcomputer 11 due to the selection of the match signal S1 and the third switch SW43 in the low state. A high state output signal S4 is generated, where it is assumed that the image memory 11 is active high.

As described above, by allowing two screens to be edited using a memory, there is an advantage that any image arrangement desired by a user can be performed.

Claims (1)

In a video printer having an image memory (3) and a memory control section (8), the first and second screen selection switches (SW1, SW2), a plurality of mode selection switches (SW3 ... SWN), and a video signal are separated from each other. Input the horizontal and vertical synchronization signals to generate vertical and horizontal address control signals S1 and S2 according to the first and second screen selection states, and read a second horizontal address from the internal memory according to the mode selection states. A comparator 9 for outputting a matching microcomputer 11 and a second horizontal address and a first horizontal address generated from the memory control section 8 to match and generate a matching signal S1 of a predetermined state; And a memory enable control unit 17 which logically operates the coincidence signal S1 and the first and second image memory control signals to generate an image memory enable signal S4, and writes the second screen data after the first screen data is recorded. Second screen data when recording screen data And when the other write address coincides with the address when located outside the area of the format stored in the memory of the microcomputer, disabling the arc memory (3) so as to allow arbitrary screen editing.

Images