JPS61264723A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61264723A JPS61264723A JP10673985A JP10673985A JPS61264723A JP S61264723 A JPS61264723 A JP S61264723A JP 10673985 A JP10673985 A JP 10673985A JP 10673985 A JP10673985 A JP 10673985A JP S61264723 A JPS61264723 A JP S61264723A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- film
- pattern
- negative resist
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- -1 arsenic ions Chemical class 0.000 abstract description 3
- 239000000428 dust Substances 0.000 description 14
- 238000004381 surface treatment Methods 0.000 description 3
- 239000004372 Polyvinyl alcohol Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 239000003595 mist Substances 0.000 description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］被処理基板上の全面に有機樹脂膜を塗布し、有
機樹脂膜の上に所望のレジスト膜パターンを形成し、そ
のレジスト膜パターンを保護膜にして、有機樹脂膜を透
してイオン注入する。Detailed Description of the Invention [Summary] An organic resin film is applied to the entire surface of a substrate to be processed, a desired resist film pattern is formed on the organic resin film, and the resist film pattern is used as a protective film to form an organic resin film. Ions are implanted through the resin film.
［産業上の利用分野］
本発明は半導体装置の製造方法に係り、特に、レジスト
膜パターンを用いた表面処理方法に関する。[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a surface treatment method using a resist film pattern.
ＩＣなど、半導体装置の製造方法において、ラオトプロ
セスは最も重要な技術であって、ＩＣの高集積化・高密
度化はそのフォトプロセスの進歩に負うところが大きい
。The Raoto process is the most important technology in the manufacturing method of semiconductor devices such as ICs, and the high integration and density of ICs is largely due to the progress of the photo process.
初期には、レジスト膜パターンを形成し、これをマスク
にして基板をエツチングする、所謂、通常のフォトプロ
セス工程が主体であったが、現在は、レジスト膜パター
ンをマスクにして、イオン注入して不純物領域を形成す
るイオン注入法等の表面処理にもフォトプロセスが利用
されている。In the early days, the so-called normal photoprocessing process consisted of forming a resist film pattern and using this as a mask to etch the substrate, but today, ion implantation is performed using the resist film pattern as a mask. Photoprocessing is also used for surface treatments such as ion implantation to form impurity regions.
一方、半導体装置の製造方法においては、塵埃が極端に
嫌われ、アクティブな半導体基板面が汚染されないよう
に、慎重に取り扱われている。On the other hand, in the manufacturing method of semiconductor devices, dust is extremely disliked and must be handled carefully so as not to contaminate the active semiconductor substrate surface.
従って、上記のような表面処理においても、ゴミなどが
付着しないように、十分な配慮が望ましい。Therefore, even in the surface treatment as described above, it is desirable to take sufficient care to prevent dust from adhering.
［従来の技術と発明が解決しようとする問題点］第２図
は従来のレジスト膜をマスクにして、半導体基板面に不
純物イオンを注入するイオン注入工程の断面図を示して
おり、１はｐ型シリコン基板、２はポジレジスト膜パタ
ーンで、ちょうど砒素イオンを加速電圧６０ＫｅＶ程度
で注入されている図である。このような工程は、例えば
、ｎチャネルＭＯ３ＩＣのソース、ドレイン領域の形成
に使用されている。[Prior art and problems to be solved by the invention] Fig. 2 shows a cross-sectional view of a conventional ion implantation process in which impurity ions are implanted into a semiconductor substrate surface using a resist film as a mask. The type silicon substrate 2 is a positive resist film pattern into which arsenic ions are implanted at an acceleration voltage of about 60 KeV. Such a process is used, for example, to form source and drain regions of an n-channel MO3IC.
ところで、このイオン注入を行なう注入装置は、高圧の
イオン加速器などが組み合わされた複雑な大型装置で、
塵埃が付着し易いものである。また、その注入操作中に
は、処理室内に真空オイルやシリコン片のようなゴミ（
ミスト）が存在して、注入面に付着する問題がある。By the way, the implantation equipment that performs this ion implantation is a large and complex equipment that includes a high-pressure ion accelerator.
Dust easily adheres to it. Also, during the injection operation, dust such as vacuum oil and silicone pieces (
There is a problem that some mist (mist) is present and adheres to the injection surface.
このようなゴミを基板表面に付着させたまま、注入イオ
ンを表面に衝突させ、注入させると、そのゴミが同時に
内部に叩き込まれて、基板が汚染されることになる。If the implanted ions are bombarded with the surface of the substrate and implanted while such dust is still attached to the surface of the substrate, the dust will be simultaneously driven into the inside and contaminate the substrate.
本発明はこのような問題点を除去して、ゴミが基板面に
侵入しないようにする半導体装置の製造方法を提案する
ものである。The present invention proposes a method for manufacturing a semiconductor device that eliminates these problems and prevents dust from entering the substrate surface.
［問題点を解決するための手段］
その目的は、被処理基板上にの有機樹脂膜（例えば、ネ
ガレジスト膜）を塗布し、該有機樹脂膜の上に所望のレ
ジスト膜パターンを形成し、該レジスト膜パターンをマ
スクにして該有機樹脂膜を通してイオン注入処理する工
程が含まれる半導体装置の製造方法によって達成される
。[Means for solving the problem] The purpose is to apply an organic resin film (for example, a negative resist film) on a substrate to be processed, form a desired resist film pattern on the organic resin film, and This is achieved by a method for manufacturing a semiconductor device that includes a step of performing ion implantation through the organic resin film using the resist film pattern as a mask.
［作用］
即ち、本発明はを機構脂膜を全面に塗布し、その上にレ
ジスト膜パターンを形成し、レジスト膜パターンをマス
クにして、イオン注入する。[Operation] That is, according to the present invention, a mechanical fat film is applied to the entire surface, a resist film pattern is formed thereon, and ions are implanted using the resist film pattern as a mask.
そうすると、ゴミの侵入は有機樹脂膜で防止され、イオ
ンのみ薄い有機樹脂膜を透過して、基板に注入される。Then, the organic resin film prevents dust from entering, and only ions pass through the thin organic resin film and are injected into the substrate.
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図は本発明にかかるイオン注入工程の断面図を示し
ており、１１はｐ型シリコン基板、１２はポジレジスト
膜パターン、１３は膜厚１０００人のネガレジスト膜で
ある。FIG. 1 shows a cross-sectional view of the ion implantation process according to the present invention, where 11 is a p-type silicon substrate, 12 is a positive resist film pattern, and 13 is a negative resist film with a thickness of 1000.
このように形成するには、まず、粘度５ｃｐ程度のネガ
レジスト液を全面に塗布し、１４０〜１５０℃で熱処理
した後、その上にポジレジスト液を塗布し、露光・現像
して膜厚１μｍのポジレジスト膜パターン１２を形成す
る。この時、ポジレジスト膜の現像液では、ネガレジス
ト膜１３が溶解されることはない。To form this, first, a negative resist solution with a viscosity of about 5 cp is applied to the entire surface, heat treated at 140 to 150°C, then a positive resist solution is applied thereon, exposed and developed to a film thickness of 1 μm. A positive resist film pattern 12 is formed. At this time, the negative resist film 13 is not dissolved in the developer for the positive resist film.
次いで、図のように、加速電圧６０にｅＶで、ドーズ量
ｌＸｌ０”程度の砒素イオンをシリコン基板１１に注入
する。そうすると、砒素イオンはレジスト膜パターン１
２では阻止されるが、薄いネガレジスト膜１３は透過し
て、その下のシリコン基板に注入される。一方、ゴミは
薄いネガレジスト膜１３によっても阻止され、それはイ
オンと粒子との大きさの相異によるものと考えられる。Next, as shown in the figure, arsenic ions are implanted into the silicon substrate 11 at an acceleration voltage of 60 eV and a dose of about 1X10''.
2 is blocked, but it passes through the thin negative resist film 13 and is implanted into the underlying silicon substrate. On the other hand, dust is also blocked by the thin negative resist film 13, and this is thought to be due to the difference in size between ions and particles.
イオン注入後、ネガレジスト膜１３はポジレジスト膜パ
ターン１２と同時に溶解除去する。この時、ネガレジス
ト膜はイオン衝撃による変質が少なく、ポジレジスト膜
パターン１２と同時に容易に剥離することができる。After the ion implantation, the negative resist film 13 is dissolved and removed simultaneously with the positive resist film pattern 12. At this time, the negative resist film is less likely to change in quality due to ion bombardment, and can be easily peeled off at the same time as the positive resist film pattern 12.
ところで、従来、ポジレジスト膜パターンの表面にもイ
オンが衝突するため、その表面が変質し、イオン注入後
にレジスト膜パターンを溶解除去しようとすると、レジ
スト膜の変質した表皮だけが基板面に固着して、除去さ
れ難い場合が多かった。By the way, conventionally, ions also collide with the surface of a positive resist film pattern, resulting in its surface being altered, and when attempting to dissolve and remove the resist film pattern after ion implantation, only the altered surface of the resist film adheres to the substrate surface. Therefore, it was often difficult to remove.
しかし、本発明では全面にネガレジスト膜１３が被覆さ
れ、ネガレジスト膜はイオン衝撃による変質がポジより
もは少なく、且つ、全面剥離であるから、剥離が容易に
なる利点も得られる。However, in the present invention, the entire surface is coated with the negative resist film 13, and the negative resist film is less likely to change in quality due to ion bombardment than the positive resist film, and since the entire surface is peeled off, there is also an advantage that peeling is easy.
このように、ネガレジスト膜１３を介在させることによ
って、シリコン基板へのゴミの侵入が防止され、且つ、
所望のイオンのみを注入することができる。かくして、
半導体基板の結晶品質が維持され、ＩＣの品質を良くす
ることができる。In this way, by interposing the negative resist film 13, intrusion of dust into the silicon substrate is prevented, and
Only desired ions can be implanted. Thus,
The crystal quality of the semiconductor substrate is maintained, and the quality of the IC can be improved.
上記は膜厚１０００人のネガレジスト膜を被覆した例で
説明しているが、膜厚は５００〜１０００人が適切で、
それより薄いとゴミの防止が十分でなく、又、余り厚い
とイオン注入に支障がある。例えば、膜厚４０００人で
も注入イオンを透過することができて、注入イオンを完
全に阻止する膜厚は６０００〜７０００人程度であるが
、出来るだけ薄い方が注入に差し障りがなく、ゴミを防
げるだけの１０００人程度０膜厚が適している。The above explanation is based on an example in which a negative resist film with a thickness of 1,000 layers is coated, but a film thickness of 500 to 1,000 layers is appropriate.
If it is thinner than this, dust prevention will not be sufficient, and if it is too thick, ion implantation will be hindered. For example, even a film with a thickness of 4,000 layers can transmit implanted ions, and a film thickness that completely blocks implanted ions is about 6,000 to 7,000 layers, but the thinner it is, the less it poses a problem for implantation and prevents dust. A film thickness of about 1000 is suitable.
且つ、このようなゴミの防止膜にはネガレジスト膜１３
だけでなく、他の有機樹脂膜、例えば、ＰＶＡ （ポリ
ビニルアルコール）膜などを用いることもできる。また
、ネガレジスト膜パターンを形成する場合でも、ネガレ
ジスト膜をゴミ防止膜とすることができ、全面塗布した
ネガレジスト膜を予め１４０〜１５０℃で熱処理すると
、露光と同じ効果を与えることになり、その上にネガレ
ジスト膜を塗布し、露光・現像してネガレジスト膜パタ
ーンを作成して、イオン注入の保護マスクとすることが
できる。In addition, a negative resist film 13 is used as a film to prevent such dust.
In addition, other organic resin films such as PVA (polyvinyl alcohol) films can also be used. In addition, even when forming a negative resist film pattern, the negative resist film can be used as a dust prevention film, and if the negative resist film coated on the entire surface is heat-treated at 140 to 150°C in advance, it will give the same effect as exposure. A negative resist film is applied thereon, exposed and developed to create a negative resist film pattern, which can be used as a protective mask for ion implantation.
［発明の効果］
以上の説明から明らかなように、本発明によれば半導体
基板の汚染が防止されて、ｒｃの品質向上に大きく貢献
するものである。[Effects of the Invention] As is clear from the above description, the present invention prevents contamination of semiconductor substrates and greatly contributes to improving the quality of RC.
第１図は本発明にかかるイオン注入工程の断面図、第２
図は従来のイオン注入工程の断面図である。
図において、
１．１１はシリコン基板、
２．１２はレジスト膜パターン、
１３はネガレジスト膜
を示している。FIG. 1 is a cross-sectional view of the ion implantation process according to the present invention, and FIG.
The figure is a cross-sectional view of a conventional ion implantation process. In the figure, 1.11 is a silicon substrate, 2.12 is a resist film pattern, and 13 is a negative resist film.
Claims (2)
膜の上に所望のレジスト膜パターンを形成し、該レジス
ト膜パターンをマスクにして該有機樹脂膜を通してイオ
ン注入処理する工程が含まれてなることを特徴とする半
導体装置の製造方法。(1) A step of coating an organic resin film on a substrate to be processed, forming a desired resist film pattern on the organic resin film, and performing ion implantation through the organic resin film using the resist film pattern as a mask. A method of manufacturing a semiconductor device, comprising:
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the organic resin film is a negative resist film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10673985A JPS61264723A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10673985A JPS61264723A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61264723A true JPS61264723A (en) | 1986-11-22 |
Family
ID=14441290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10673985A Pending JPS61264723A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61264723A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017092256A (en) * | 2015-11-10 | 2017-05-25 | 富士電機株式会社 | Semiconductor device manufacturing method |
-
1985
- 1985-05-17 JP JP10673985A patent/JPS61264723A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017092256A (en) * | 2015-11-10 | 2017-05-25 | 富士電機株式会社 | Semiconductor device manufacturing method |
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