JPS6126273B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives a still image signal that is multiplexed and transmitted in a part of a vertical retrace period of a television signal, and uses the still image signal to perform vertical synchronization of the television signal. This relates to a still image receiving device that stores data in a main memory driven by a clock pulse synchronized with a signal, and displays the output on a television screen, in which the phase of the vertical synchronizing signal is temporarily changed. To provide a still image receiving device in which a playback screen of a still image signal is not affected by the deviation.

The phases of vertical and horizontal synchronization signals of a television signal sent from a broadcasting station may be shifted, for example, when a broadcast program is switched between a live broadcast and a VTR, or between a central station and a local station. Although the phase shift of the horizontal synchronization signal can be compensated for by the automatic frequency control (AFC) circuit in the receiver, there is a chance that the phase shift of the vertical synchronization signal will become apparent. If the above-mentioned main memory is driven by a clock pulse synchronized with the vertical synchronization signal that caused this phase shift instead of a clock pulse synchronized with the vertical synchronization signal immediately before this phase shift occurs, the still image to be displayed will be Adverse effects such as deviation in direction or deterioration of image quality are observed.

In view of this point, the present invention provides that if the phase of the vertical synchronization signal changes as described above before the memory contents complete one round in the main memory, the main memory is The vertical synchronization signal is ignored and a clock pulse corresponding to the original vertical synchronization signal is continuously input, and after the memory contents have completed one cycle, a clock pulse synchronized with the new vertical synchronization signal is input to the main memory. By doing so, it is possible to provide a novel still image receiving device that eliminates the above-described drawbacks.

It has been considered to multiplex and transmit signals other than the original video signal, such as still images and text information, during the vertical blanking period of the television signal. , Teleskyan, etc. have been proposed. Although the technology of the present invention can be applied to any of these, an example applied to the NHKC system will be described below.

To facilitate understanding of this example, we first
An overview of the NHKC system will be explained. In this C system, character signals are multiplexed only in the 1H period of the 20th and 283rd H counting from the start of the vertical blanking period. Characters are made up of 18 dots vertically and 15 dots horizontally, and if you set 14 characters per line with 2 dots between characters and leave a space of 2 dots at the beginning and end of the line, 14 characters per line will fit horizontally. direction 240
Consisting of 18 dots in the vertical direction, 7 dots make up one screen.
If it is a row and the line spacing is 12 dots, it will be 198 dots in the vertical direction. If one vertical dot is displayed with one horizontal scanning line, one screen will be displayed in 198H. If this character signal is multiplexed by 1H in one field and sent, one line (including line spacing) of 30H can be sent in 30 fields, or 0.5 seconds.

Considering the human reading speed, in the C system,
Nine types of programs are transmitted line by line every 0.5 seconds. Therefore, when you select a certain program, the display of that program will start with a maximum waiting time of 4 seconds, and the maximum waiting time will be 0.5 seconds.
When a line is completed in seconds, another program is being sent for 4 seconds, so no new display is performed, and 4 seconds later, the next line of the same program is displayed again for 0.5 seconds or so.

FIG. 1 shows the signal waveform of the 20th horizontal period of the vertical retrace period, in which the signal C for one horizontal scan of characters to be displayed is multiplexed. Furthermore, there is a 4-bit binary program code A that indicates which of the 9 types of programs this signal is, and a 8-bit binary line that indicates the H-th signal on one screen displayed for that program. A code B is added, and a signal STX that is to be used as a reference when reading all these signals is also added. Note that HP indicates a horizontal synchronization pulse and BST indicates a color burst signal. In this C system, one bit of the character signal is 5/8f _SC ≒ 175ns (f _SC = 3.579545MHZ)
Furthermore, one bit of each of the (STX) A and B signals is approximately 700 ns, which is four times that amount.

Next, a receiver for receiving and displaying such character signals will be described. FIG. 2 is a block diagram of the receiver, in which a television signal received by an antenna 1 is subjected to image detection by a tuner 2, and a video signal is output. This video signal is processed by a waveform shaping circuit 3, a synchronization separation circuit 4, a color subcarrier regeneration circuit 5,
and the signal processing circuit 6, respectively. The synchronization signal separated by the synchronization separation circuit 4 is 20H.
and 283H are input to a circuit 7 and a horizontal line counter circuit 8. The output of this detection circuit 7 is applied to a signal sampling circuit 9 into which the output from the waveform shaping circuit 3 is input, and the signal sampling circuit derives the 20th H and 283rd H character signals from the video signal. This character signal is input to a buffer memory 10, a line code comparison circuit 11, a program code comparison circuit 12, and an (STX) signal detection circuit 13, respectively. Further, the output of the horizontal line counter circuit 8 driven by the synchronization signal is input to the line code comparison circuit 11. The program code comparison circuit 12 compares the program code selected in advance by the program selection switch 14 with the program code in the character signal. The output from this switch 14 is also input to a program display section 15, where the program being selected is displayed. The STX signal detected by the STX detection circuit 13 is input to a clock signal generation circuit 16 to which the color burst signal from the reproduction circuit 5 is applied. This generation circuit 16 generates 8/5 of the color subcarrier f _SC
A clock signal having twice the frequency and in phase with the start of the STX signal is derived. When both the program code and line code match, the rewrite gate 18 is opened by a signal from the control circuit 17 and the contents of the buffer memory 10 are transferred to the main memory 19. This main memory 19 circulates in synchronization with the line counter, and is a shift register of approximately 48K bits for 198H from the 48th H to the 240th H. The buffer memory 10 is a 240-bit shift register for 1H.

The main memory is rewritten with 240 bits per field specified by the line code, and if this operation is repeated 198 times, a character pattern of 198 lines per field will be stored. The contents of the main memory are read out in 1H240 bits from the 43rd H to the 240th H in one field, and the output is supplied to the screen 20 via the signal processing circuit 6 and written to this memory again. 1 in the field
It will cycle through memory at a rate of

Note that by applying a signal from the display mode switch 21 to the control circuit 17, the contents of the buffer memory can be changed to the first one regardless of the line code.
Transferred at 241H and oldest 1 in main memory contents
By erasing lines, it is also possible to perform a scroll display in which the displayed image is moved one line at a time from the bottom to the top of the screen. In addition, since new information is sent one after another to the input signal, it is normally updated every 0.5 seconds, and even in the case of a 7-line display, the maximum
The current display will be rewritten in 3.5 seconds, minimum 0.5 seconds. If it is desired to increase the display time, the stop button 22 may be pressed to cut off new input. This can be done by prohibiting transfer from buffer memory to main memory.

FIG. 3 shows a specific example of a conventional horizontal line counter circuit. FIG. 4 is a time chart of the waveforms of each part. Load pulse generation circuit
LG receives the vertical synchronization signal VD and the horizontal synchronization signal HA passed through the AFC circuit, and outputs the load pulse LP and gated horizontal synchronization signal.
Derive HB. Each output is a line counter LC
and each bit a, b, c, d, a',
b', c', d' exhibit signals as shown in FIG. 4 as outputs, for example. This counter is a 256-decimal counter, and in order to count the horizontal synchronizing signal HA and display the 43rd H as line number [1], the load pulse LP causes the count value to 220.
is preset to. It's becoming like that. Therefore, as shown in FIG _.
When, for example, the line counter LC enters the 81st H after the input of the vertical synchronizing signal VD ₂ , the line counter LC is newly preset with the load pulse LP ₃ , so the clock pulse to the main memory 19 described above is
The clock pulses from the 81st to the 240th H are insufficient to complete the cycle since only the 43rd to the 80th are output. When this happens, the display screen will look like Figure 6 A to Figure 6 B.
It appears to have shifted down by 160H, and equivalently moved up by 38H. Also, vertical synchronization signal VD ₃ is 81H
If it gets in the middle of the eye, the shape of the displayed characters will be distorted. In addition, in Figure 5, CP
shows the time chart of the clock pulse input to the main memory, 43H to 240H are for character information,
Further, the 241st bit is used for scrolling display, and each H240 bit is read out from the main memory.

FIG. 7 is a block diagram of the main part of the apparatus of the present invention, that is, the horizontal line counter circuit, and FIG. 8 is a time chart thereof.

In Figure 7, _F1 is opened after the 241st clock pulse of 240 bits in the main memory has finished outputting, and the character information of the next field is multiplexed.
The flip-flop is closed by the 20th pulse,
_G1 is an AND gate whose inputs are the vertical synchronizing signal VD input and the output VDG of the flip-flop _F1 , whose output VDA is used as a load as the first circuit for presetting the line counter LC similar to that shown in FIG. Input to pulse generator LG. F ₂ is 241H
A second flip-flop, which opens on the end pulse of the second clock pulse and closes on the AND gate output VDA, is used as a second circuit for presetting the counter LC and whose output GL
and the output LDA of the generator LG and the AND gate G ₂
is input to line counter LC, and its output LDB is input to line counter LC.
Preset.

In such a configuration, as shown in FIG. 8, the out-of-phase vertical synchronization signal VD ₃ is ignored at the output VDG of the first flip-flop F ₁ and therefore the load pulse is not output at VD ₃ . By doing this, the clock pulses of the main memory 19 correspond to the vertical synchronizing signals VD ₁ , VD ₂ , and VD ₄ without outputting the clock pulse corresponding to VD ₃ that enters in the middle, as shown in CPA of FIG. The clock pulses for one cycle of the main memory are output.

Note that the line counter LC is an 8-bit counter in 256 decimal notation, and each field shown in Figure 5 is
By being preset to line number [220] over the 6th H (within the vertical synchronization signal period),
Since the 43rd H is line number [1], if it corresponds to the vertical synchronization signal VD ₂ in Figure 8,
If vertical synchronization signals VD ₃ and VD ₄ arrive at a timing such that vertical synchronization signal VD ₄ is located after point T ₀ , which is 256H minutes counting from the 43rd H, as shown by the broken line in FIG. At time T ₀ above, an output corresponding to line number [1] is generated from line counter LC, and after that, this counter LC is horizontally synchronized until it is preset to line number [220] at the preset timing in VD ₄ . In response to the signal HB, outputs (shown by broken lines) corresponding to line numbers [2], [3], [4], . . . are generated one after another every 1H. Therefore, a clock pulse of 240 bits is generated during each output, making ignoring VD ₃ meaningless. To prevent this, the circuit above uses 241H, which corresponds to VD ₂ .
From the end of the minute clock pulse to VD ₄ , the output of the second flip-flop is set as GL ₃ , and finally the output of AND gate G ₂ is the AND of this flip-flop output GL and the load pulse LDA.
LDB is used as a preset pulse to line counter LC. That is, by keeping the line counter LC in the preset state of line number [220] during the low level period of this pulse LDB, outputs corresponding to line numbers [1] to [199] are output from the counter LC. This prevents unnecessary lock pulses from being output.

In the above operation explanation, vertical synchronization signal VD ₃ is VD ₂
I gave an example of the case where it is output between 43H and 241H, but if VD ₃ enters before 20H,
Although VD ₃ is output without being ignored, it does not affect the operation of the line counter circuit. Also, 241H
VD ₃ is not ignored if it enters after
After the clock pulse corresponding to VD ₂ completes one cycle through the main memory, a clock pulse corresponding to VD ₃ is output. When VD ₃ enters between 21H and 43H, if a 0.5 second write transfer from buffer memory to main memory is in progress, the character information signal for write transfer is input at the 20th H of VD ₂ and the 20th H of VD ₃ . Since it is on, VD ₃
If you ignore this, the character information signal at the 20th H of VD ₃ will also be ignored, so one line of displayed characters will be missing on the screen, but this is because the character information signal will be displayed at the 20th H immediately after switching to vertical synchronization on the transmitting side. It is best to avoid multiplexing. If the phase shifts during this period other than during write transfer, it is the same as the case between 43H and 241H.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram showing an example of a character multiplexed television signal, Fig. 2 is a block diagram of its receiver, Fig. 3 is a block diagram of a conventional horizontal line counter circuit, and Fig. 4 is a block diagram of a conventional horizontal line counter circuit. , FIG. 5 is a time chart for explaining the operation of the above circuit, and FIGS. 6A and 6B are examples of screens before and after the phase shift of the vertical synchronization signal occurs. FIG. 7 is a block diagram of essential parts of the apparatus of the present invention, and FIG. 8 is a time chart thereof. Explanation of main drawing numbers, 4...Synchronization separation circuit, 5...
Color subcarrier regeneration circuit, 6... Signal processing circuit, 7...
...detection circuit, 8 ... line counter, 9 ... signal sampling circuit, 10 ... buffer memory, 11 ... line code comparison circuit, 12 ... program code comparison circuit, 13 ... (STX) signal detection circuit, 14 ... …
Program selection switch, 15...Program display section, 16...
...Clock signal generation circuit, 17...Control circuit, 1
8... Rewriting gate, 19... Main memory, 20...
Screen, 21...display mode switch, 22...pulse generation circuit, LC...line counter, _F1 ...first flip-flop, _G1 ...and gate,
F ₂ ... second flip-flop, G ₂ ... or gate.

Claims (1)

[Claims] 1. Receive a still image signal multiplexed during the vertical retrace period of a television signal, and cyclically accumulate and store the still image signal in a main memory in synchronization with horizontal and vertical synchronization signals of the television signal. A still image receiving device that displays images on a television screen includes a line counter that is preset to a predetermined value at a timing within a vertical synchronization signal and counts horizontal synchronization signals, and each field defined by the output of this counter. A gate circuit that is opened during the period from after the still image signal display period in one field to before the still image signal display period in the next field, and a vertical synchronization signal input through this gate circuit to obtain the timing within the signal. a first circuit that generates a preset pulse; a second circuit that generates a preset output that lasts from after each display period until a vertical synchronization signal is input through the gate circuit; and a circuit that continuously presets the counter to the predetermined value during each output of the second circuit, and performs a cyclic operation of each line of the main memory by a clock pulse synchronized with the output of the counter. A still image receiving device characterized in that, by doing so, disturbance of a displayed image due to a phase shift of a vertical synchronizing signal is prevented.