JPS5824992B2 - Receiving device for multiplexed information signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives and stores a still image signal superimposed and sent separately from a normal video signal during the vertical blanking period of a television signal, and reproduces the still image. The present invention relates to a receiving device for multiplexed information signals such as a still image signal, and an object of the present invention is to provide a device capable of accurately extracting a multiplexed information signal such as a still image signal and performing other accurate control.

A system for transmitting still images such as characters and figures has been considered as a system for transmitting other information using television signals.

This system uses, for example, a still image with 200 horizontal scan lines (
200 lines) and 256 bits per line, and as shown in Figure 1, any horizontal period during the vertical blanking period of the television signal (for example, the 20th
H-th), a 256-bit image signal V of one horizontal scanning line (one line) of a still image, and code signals such as a start reference signal 5TX1 program code signal PC and a line number code signal LN are binary-valued. This image signal V is sent out in a superimposed manner in the form of a
The signal is received by a receiving circuit 1 such as a television signal tuner/video detection circuit, etc., a still image signal extraction circuit 2 extracts still image signals such as an image signal V, and the image signal V is sequentially stored in a storage circuit 3. After that, the reproduction circuit 4 reads out the image signal ■ from the storage circuit 3 in synchronization with the horizontal and vertical scanning of the cathode ray tube 5, mixes it with a normal television video signal in the mixing amplification circuit 6, amplifies it, and outputs it to the cathode ray tube. A still image, for example, characters, is projected and displayed on the screen 5 as shown in FIG.

In FIG. 2, 7 is a horizontal and vertical synchronizing signal separation circuit, 8 is a burst signal separation circuit and local color subcarrier signal fsc generation circuit, and 9 is a local color subcarrier signal fsc.
10 is an image signal V in FIG.
A start detection circuit 11 detects a start reference signal STX sent prior to the start reference signal STX, and a start detection circuit 11 uses these horizontal and vertical synchronizing signals, a reference clock signal, and a start reference signal STX to perform storage and reproducing operations of the write circuit 3 and the reproducing circuit 4. This is a control circuit that controls the

The main parts of such a still image receiving apparatus will be explained in more detail using FIG. 4.

Here, 12 is a receiving circuit including a tuner, a video detection circuit, etc., 13 is a waveform shaping circuit that shapes the output of this receiving circuit 12 into a binary code, 14 is a synchronization signal separation circuit,
15 is a horizontal oscillation circuit incorporating an AFC circuit so as to oscillate a horizontal pulse in synchronization with a horizontal synchronization signal; 16 is a vertical synchronization separation circuit.

In addition, 18 generates a sampling pulse during the 20th H period in order to extract a still image signal such as the image signal V superimposed on the 20th H of each water field based on the horizontal and vertical signals. The sampling pulse generation circuit 19 detects the start point of the nH-th (for example, the 42nd H-th will be explained using the 42-nd H-th) which is the top end when displaying a still image on a cathode ray tube. circuits, both of which generate these outputs by counting horizontal signals.

Further, reference numeral 20 indicates the number of the horizontal scanning line currently being scanned by the cathode ray tube, counting from the above-mentioned 42H-th horizontal scanning line, using a horizontal oscillation circuit 15 or a frequency dividing circuit 23 to be described later.
This is a line number counter that detects by counting the horizontal signals from the horizontal and vertical synchronizing signals, and these are the parts that generate each control signal from the horizontal and vertical synchronizing signals.

Next, 21 is a subcarrier oscillation circuit that generates an fsc local subcarrier signal based on the color burst signal, and 22 is a multiplication circuit that multiplies this subcarrier signal by 3/2 to obtain a 7 fsc standard rank signal. 23 is a frequency dividing circuit which divides the frequency of this reference clock signal to obtain basic clock signals of various frequencies. Based on the output signal of this frequency dividing circuit 23, a memory clock generating circuit 24 is used for memory reproduction drive. To extract the program code signal PC and the line number signal LN from the received signal, a reception clock generation circuit 25 generates clock signals of a predetermined width and a predetermined number at predetermined times, respectively.

These are the parts that generate signals for bit-by-bit control of each signal.

Next, a means for receiving still images using these control signals and clock signals will be explained.

Here, the part where the operator specifies the reception mode is a program designation circuit 26 that specifies which program's still image is to be received.
Then, the received still images are displayed one by one while remaining still, and after each still image is finished, the next still image is displayed (so-called page display), or the incoming still image signal is displayed. and a display mode designation circuit 27 that designates whether to perform so-called roll display in which static images are displayed in a flowing manner upward or downward by writing and displaying them at the top or bottom of the display image one after another.

First, in the gate circuit 28 for signal extraction, each of the 20Hth signals STX, PC, and LN from the output of the waveform shaping circuit 13 is generated by the 20Hth sampling pulse from the sampling pulse generation circuit 18.

(2) is extracted and supplied to the input gate circuit 29, program code signal extraction circuit 30, and line number signal extraction circuit 34.

The program code signal extraction circuit 30 extracts a 4-bit program code signal LN using the program code extraction clock signal supplied from the reception clock generation circuit 25, and converts it into 1
Retains the field period.

And this extracted program code signal LN program designation circuit 2
In step 6, the comparison circuit 31 compares the program designation code signal specified by the operator with the program designation code signal, and when the two match, a match output is generated, and a flip-flop 32 is set to generate its Q output.

The input gate circuit 29 is opened by the Q output, and the image (2) of the received still image signal is written and stored in the buffer memory 33 constituted by a dynamic shift register or the like having a capacity of 256 bits for one line.

In this case, a write clock is applied to the buffer memory 33 only during the image signal V at the 20th H, so that only the still image signal V is stored.

This buffer memory 33 is further supplied with a cyclic clock signal of 256 bits every H so that the stored contents are circulated once every H, and especially during the 200H period from the 42nd H to the 241st H. During the image display period, it is driven by the same circulating clock signal as the main memory 38, which will be described later.

At the same time, the line number signal extraction circuit 34 uses the line number signal extraction clock signal supplied from the reception clock generation circuit 25 to generate the 8-bit line number signal LN.
and hold it for one field.

Then, in the line number comparison circuit 35, the count output from the line number counter 20 and the extracted line number L
When the two match, a match output is generated, and this match output is applied to the selection gate 36.

This selection gate 36 selects the main memo IJ depending on the display mode.
This is used to switch the write state to the SS, and its output opens the transfer gate 37, and the just-received image signal V stored in the buffer memory 33 is written to a predetermined location in the main memory 38 and stored.

The main memory 38 is normally a storage circuit composed of a shift register or the like having a capacity of the total prime number of still images, that is, 256 bits x 200 lines = 51,200 bits.

The operator selects "page display" from the mode designation circuit 27 above.
When the line count output of the line number counter 20 and the received line number signal LN match, the matching output from the comparison circuit 35 is applied to the transfer gate 37 via the selection gate 36. The selection gate 36 is switched, and a new line of image signal (2) is written in the storage portion corresponding to this line number in the main memory 38.

On the other hand, when the operator specifies "roll display" from the display mode designation circuit 27, the matching output from the comparison circuit 35 described above is not used, and the occurrence occurs at the 201st H, which is specially output by the line number counter 20. The selection gate 36 is switched so that the roll gate pulse is applied to the transfer gate 37 via the selection gate 36, and the new image signal V is always transferred to the beginning or end of the main memory 38 at the 201st H. Write it to the memory part of.

This switching is performed by a designation signal sent from the display mode designation circuit 27 to the selection gate 36.

By repeating this write operation,
Since the received image signal V can be stored, the display period of 200H from the 42nd H to the 241st H
During the period, a readout clock signal is supplied to the main memory 38 at a rate of 256 bits per H to read out this image signal (2), which is then sent to the mixing circuit 39, signal processing circuit 40, and RF modulator 41 for normal television reception. By adding this to the antenna terminal of the device 42, a still image can be displayed on the cathode ray tube 43.

In this way, it is possible to receive the still image signal multiplexed with the television signal and display the still image, but in such a receiving device, as described above, in order to extract the still image signal, it is possible to display the still image. It is necessary to count horizontal pulses and generate sampling pulses and other control pulses at predetermined times in order to control the storage or readout of the data.

However, in television signals, there is a difference of 0.5H between odd and even fields due to jump scanning, so a means to compensate for this difference is required. The disadvantage is that the configuration is complicated.

Therefore, the present invention eliminates such conventional drawbacks and generates control pulses such as sampling pulses at accurate positions in both odd and even fields with an extremely simple configuration.
The object is to provide a device that can perform accurate operations.

An embodiment of the present invention will be described below with reference to FIGS. 5 and 6.

FIG. 5 shows a specific circuit of a control pulse generation circuit that can be used in place of the sampling pulse generation circuit 13, 42H detection circuit 19, etc. in FIG.

Further, FIG. 6 is a waveform diagram showing the waveforms of each part shown in FIG. 5, in which the waveforms without a dash represent the waveforms of the odd field, and those with the dash represent the waveforms of the even field.

Here, 44 is a monostable multi-by-break whose duration is wider than the pulse width of the composite synchronization signal and less than 1/2 of the horizontal period, and its trigger terminal is connected to the sixth This is triggered by adding a composite synchronization signal as shown in Figures A and A', and outputs as shown in Figures B and B' are obtained.

At the same time, the composite synchronization signals A and A' are outputted by the inverter 45 as shown in FIG.
By inverting it as shown in Figure 2C' and adding this and the outputs B and B' of the monostable multi-bi break 44 to the AND gate 46, the vertical synchronizing signal as shown in Figure 6, D' can be obtained. A composite output is obtained by passing the composite synchronization signal only during the period.

Furthermore, this composite output. D' is set in addition to the flip-flop 47 for controlling the operation of the counter 48,
The counter operation control pulses as shown in FIG. 6 E and E' are obtained from the sub-output terminal, and these are added to the operation control terminal of the counter 48.
starts counting operation.

Composite synchronization signals A and A' are applied to the input terminal of the counter 48, and a pulse E is applied.

The composite synchronization signals A and A' after the rising edge of B are counted, and when a predetermined number of counts is reached, the NAND gate 50 outputs the signal F in FIG.
The sampling pulse, the 42nd H detection pulse, and other arbitrary control pulses are extracted as shown in F'.

Thereafter, at an appropriate counting time, a reset pulse is taken out from the NAND gate 49 to reset the flip-flop 47, thereby also stopping and resetting the counting operation of the counter 48.

Thereafter, this is repeated every field, and a control pulse is generated from the NAND gate 50 after a certain count from the vertical synchronizing signal.

Therefore, according to such a configuration, as is clear from the above description, the composite output obtained from the AND gate 46 and the timing of D' can be set to exactly the same timing in the vertical synchronizing signal regardless of the odd field or even field. By using this composite output D' to control the start of counting of the counter 48, it is possible to obtain control pulses accurately in a predetermined horizontal period in both odd and even fields. Therefore, it is possible to perform an accurate extracting operation of the multiplexed information signal and an accurate locking operation of the memory.

For example, in the above example, the 20th and the 2nd
Still image signal multiplexed on 83rd H.

In order to obtain a sampling pulse for extracting the signal, it is sufficient to extract the output when the counter 48 counts 21 composite synchronization signals A and A'.

Such a pulse generation circuit can also be used for the 42nd H detection circuit 19, and can also be used as a clock for other memories.

It can also be used for control circuits, etc.

In the above embodiment, the composite synchronization signal is counted by the counter to generate the output pulse, but any other horizontal pulse such as the horizontal pulse from the horizontal oscillation circuit 15 or the horizontal flybank pulse may be used.

A similar effect can be obtained by counting pulses.

Furthermore, it goes without saying that the present invention can be widely applied not only to the still image receiving apparatus as described above but also to receiving apparatuses for receiving multiplexed information signals of any format using television signals.

As described in detail above, the multiplexed information signal receiving device of the present invention receives a television signal in which information signals are multiplexed and transmitted, separates a composite synchronization signal, and uses this composite synchronization signal to determine the duration of the multiplexed information signal. triggers a monostable multi-by-break of less than 1/2 horizontal period.L1 combines the output of this multi-by-break with the above composite synchronization signal to take out the composite output that occurs only during the vertical synchronization signal period, and uses this composite output to trigger the counter. A counting operation is started, and the counter counts the composite synchronization signal to generate the information signal sampling pulse at a fixed time in each field.

Therefore, the counting operation of the counter can be started at exactly the same time during the vertical synchronization signal period in both odd and even fields, and control pulses can be accurately obtained in a predetermined horizontal period in both odd and even fields. It is possible to accurately perform operations such as extracting the conversion information signal and controlling the storage.

[Brief explanation of the drawing]

1A and 1B are waveform diagrams of a still image signal as an example of a multiplexed information signal, FIG. 2 is a block diagram of a still image receiving device as an example of a multiplexed information signal, and FIG. 3 is a block diagram of the same device. FIG. 4 is a detailed block diagram of the device, and FIG. 5 is a circuit diagram of a main part of a still image receiving device using a multiplexed information signal receiving device according to an embodiment of the present invention. Figure, Figure 6 A, B, C, D, E, F, A', B', C',
D', E'. F' is a waveform diagram for explaining the operation of the device. 12...Reception circuit, 14...Synchronization separation circuit, 18...Sampling pulse generation circuit, 19...
... 42H detection circuit, 44 ... Monostable multi-bi break, 45 ... Inverter, 46 ...
...AND gate, 47...Flip-flop, 48...Counter, 49°50...
・NAND gate.

Claims (1)

[Claims] 1. A television signal in which information signals are multiplexed and transmitted is received, a composite synchronization signal is separated, and a single unit whose upstream connection period is less than half the horizontal period is added to the composite synchronization signal. Trigger the stable multipipe rake, combine the output of this multivisor with the above composite synchronization signal, take out the composite output that occurs only during the vertical synchronization signal period, start the counting operation of the counter with this composite output, and A receiving device for multiplexed information signals, characterized in that a counter counts the composite synchronization signal or other horizontal pulse signals and generates control pulses such as the information signal extraction pulses at fixed times in each field. 2. Receiving a multiplexed information signal according to claim 1, wherein the output of the monostable multi-by-break and a signal obtained by inverting the composite synchronization signal are logically ANDed to obtain the composite output. Device. 3. The multiplexed information signal receiving apparatus according to claim 1, wherein a flip-flop is triggered by the combined output, and a counting operation of the counter is controlled by the output of the flip-flop.