JPS5850471B2 - tv jiyeonji yuzouki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for displaying a display image such as news characters, which is superimposed on a television broadcast signal and sent separately from a normal video signal.

BACKGROUND ART Television receivers, facsimile systems, and the like are used as means for transmitting information expressed by video signals using broadcast signals, and for receiving and displaying the signals.

However, facsimile systems and the like are complicated and require large, complicated, and expensive equipment, making them unusable for general purposes.

Therefore, using the most commonly used television receiver, the broadcasting station superimposes text images such as emergency news onto the normal video signal of the television broadcast signal, and displays it on the receiving screen using subtitles, rolls, etc. Conventionally, a method has been used in which the image is superimposed.

However, in this case as well, the text image is unconditionally superimposed on all television receivers receiving the television broadcast signal of that channel, so it is displayed even when it is unnecessary on the receiving side. Also, on the broadcasting station side, it is not always possible to transmit emergency news etc. during any program, and the content that can be transmitted is limited to specific items such as emergency news, so it is difficult to provide sufficient information to the viewers and be satisfied. This method has the inconvenience of not being able to give accurate results.

Therefore, in order to eliminate such conventional inconveniences, a video signal for displaying news etc. is superimposed on the part of the television broadcast signal during the vertical blanking period other than the normal video signal and broadcast. The so-called Telescan (trade name) system was devised in which images are taken out at will on a John receiver and displayed superimposed on the screen using a roll or the like only when necessary.

First, to briefly explain the principle of this system, in this system, news characters, etc. are first decomposed into matrix-like picture elements on the transmitting side, and one vertical column of the picture elements is randomly divided into pixels during the vertical blanking period of each field. During the horizontal scanning period, the pulse signal is sent separately from the normal video signal and superimposed on it.

On the other hand, on the television receiver side, the pulse signal during the vertical blanking period of the television broadcast signal is separated and demodulated, temporarily stored in the first memory, and the stored contents are further displayed on the television screen. The data is written in a shift register having bits equivalent to the total number of picture elements (for example, 4096 bits) in accordance with the scanning direction and scanning order of the television screen, and is sequentially read out from this shift register in synchronization with the scanning of the picture tube. Display images such as news characters are displayed on the screen by being superimposed on the signal.

At this time, the display on the screen can be rolled from left to right or right to left, or stopped by appropriately selecting the writing of the signal to the shift register and the timing of shifting the shift register. .

This will be explained in more detail.

First, FIG. 1 shows the form of the display.

Here, one font is divided into 16 vertically and horizontally so that kanji can also be displayed, and one character is displayed with 16 x 16 dots.
The space between each character should be increased by two dots.

Further, the number of characters displayed for the -shipment is set to 14 characters in consideration of readability, and such a display is displayed horizontally at the bottom of the television screen 1 as shown in FIG.

2 in Figure 2 is the display division, 3 and 4 are horizontal and
This is a vertical blanking division.

On the other hand, in order to fit one line of display in the center of screen 1, one dot in the horizontal direction is approximately 130 n5ec and the clock pulse frequency is approximately 7.16 MHz), and the vertical direction is continuous in time. Dot each dot on 16 horizontal scanning lines (a range of 32 lines due to interlaced scanning).

On the transmitting side, each column of display characters divided into 16 x 16 dots is scanned vertically as shown by the broken line in Figure 1, and a signal indicating whether or not each vertical dot should be displayed is sent. (white level) or O (black level), and this pulse is sequentially repeated from the left column to the right column.

Then, this signal for one column is sent out during an arbitrary horizontal scanning period during the vertical blanking period.

The state is shown in FIG.

Here, 5 is a vertical synchronizing signal, 6 is a horizontal interval signal, and 7 is a burst signal, and the display signal 8A as described above is generated during, for example, the 20th horizontal scanning period counting from the start of the vertical blanking period.

Sends 8B, 8C, 8D, and 8E.

The five types 8A to 8E in the figure are A; News;
This is to send five types of information such as B: weather forecast, C: sports, etc.

In addition, for each vertical blanking, a reference pulse is inserted several bits immediately before the display signals 8A to 8E as a reference pulse for aligning the reception timing of each of the display signals 8A to 8E in the vertical cycle. An initial pulse 9 is sent out, and a control pulse 10 for controlling the stop of the display on the receiver side, the stop of the roll, etc. is sent out at the same time to the bit immediately before each of the display signals 8A to 8E.

In addition, these signals 8A to 8E, 9, and 10 are all sent out in an accurate positional relationship, and are synchronized with the color subcarrier signal so that the receiving side can accurately obtain the period when receiving the image.
The pulse width for each bit is approximately 580 nsec (2
/color carrier frequency).

The pulse width of each signal at the time of transmission is determined in accordance with the permissible frequency band in the transmission path and the number of bits to be transmitted, independently of the frequency of the clock pulse for display on the receiving side.

Here, it is set wide so that the pulse waveform can be reliably transmitted.

On the receiving side, each signal is sampled and extracted using a sampling clock pulse obtained by dividing a clock pulse having a frequency twice the number of color subcarriers into 1/4.

When transmitting in this way, 16 fields are required to transmit a display signal for one character, and the number of characters transmitted per second is 60/16#3.7 characters, which is faster than normal television. The roll of broadcasting is almost the same as the caption.

Therefore, on the receiving side, if the signals transmitted in the xr manner are received and sequentially displayed on the screen, characters to be rolled, etc. can be displayed on the screen.

Of course, the pulse signal representing this display character (which may also be a figure) may be created by configuring a character generator on the transmitting side using a large capacity memory or the like.

Next, a television receiver that receives such signals and displays images will be explained.

FIG. 4 shows its schematic configuration, which includes an antenna 11, a tuner 12, an intermediate frequency amplification circuit 13, a video detection circuit 14, a video amplification circuit 15, a picture tube 16, a synchronous separation circuit 17, a deflection circuit 18, The color demodulation circuit 19 is similar to that of a normal television receiver.

Furthermore, this television receiver is equipped with a display circuit 20 for performing the above-described display.

This display circuit 20 is first provided with a data separation circuit 21 for extracting from the detected video signal only the display signal due to pulses superimposed in the horizontal period included in the vertical blanking period. Pulse generation circuit 22
The signal for display is extracted by the extraction pulse from.

That is, in this sampling pulse generation circuit 22, the second pulse is reset by the horizontal synchronizing signal 6, and the second
A sampling pulse that is output after the initial pulse of the 0th horizontal scanning period is generated, thereby opening the gate of the data separation circuit 21.

Alternatively, the number of horizontal synchronization signals after vertical synchronization signal 5 may be counted, and the sampling pulse may be generated only during the 20th horizontal scanning period.

Furthermore, since the display signals extracted in this way include five types of signals 8A to 8E, the data selection circuit 2
In step 3, only the desired type of signal is selected.

This selection is made by counting the number of pits after initial pulse 9 in the data selection pulse generation circuit 24 and generating a selection pulse only during the 16-bit period (excluding the space period) of the desired display signals 8A to 8E. This is done by opening the gate of the data selection circuit 23.

Of course, which of the display signals 8A to 8E is selected is determined by switching the data selection pulse generation timing of the data selection pulse generation circuit 24.

In this way, a specific type (for example, news) of a selected type is sent during the vertical blanking period and separated from the normal video signal.
The 16-bit display signal for one field is temporarily stored in a 16-bit shift register 26, which is a first memory, by a shift pulse from a shift pulse generation circuit 25, and then controlled by an input control circuit 27. The shift pulse from the shift pulse generation circuit 30 is written into the 4096-bit shift register 29, which is a second memory, via the input switching circuit 28.

The clock signal for these circuits is provided by the color demodulation circuit 19.
The color subcarrier signal of 3.58 MHz is multiplied by the doubling circuit 38 to 7.16 MHz.

As shown in FIG. 5, this shift register 29 has 16 rows of row shift registers 31 to 35 of 256 bits per row connected in cascade, each row corresponding to each row of the display on the screen, and each bit Corresponds to each column in the display.

A shift pulse is applied to this shift register 29 from a shift pulse generating circuit 30, so that it is shifted when a display signal is written and read.

For example, if a display signal for displaying news characters as shown in Figure 1 is sent from the transmitting side as shown in Figure 3, each bit of the display signal is shown in Figure 5. They are stored in their respective corresponding parts.

Although the display signal sent at this time moves in the vertical direction, the shift direction of the shift register 29 is in the horizontal direction, so in order to store it in the corresponding bit part, the writing timing is must be selected.

That is, in the first field, AI.

A2. ......, if the display signals of the column A16 are received and stored in the 16-bit shift register 26 in that order, then the display signals of the column A16 are stored in the 16-bit shift register 26 in that order.
In order to write to , write A1, then shift only the shift register 29 by 256 bits, then write A2, shift it further by 256 bits, and then write A3, repeating this process 16 times as shown in the figure. A1-A16 are written to the leftmost bits of row shift registers 31-35.

This is done during one vertical period (excluding the scanning period of display section 2), and during the vertical blanking period at the beginning of the next field, the next file B1. B2.
......, the display signal of B16 is stored in the 16-bit shift register 26, and the display signal of A1 is stored in the same manner as above.
．． A2.・・・・・・・・・B in the next bit of A16
l j B27......Write B16.

This is repeated as many times as the number of bits for 14 characters, and all display signals are written into the shift register 29 as shown in FIG.

Here, the 14 characters correspond to 256 bits of shift register 29 per line, assuming that one character has 16 horizontal dots and the space between each character is 2 dots as shown in Figure 1.
This is because only 14 characters can be written in .

In this case, 4 bits) (256 (16+2) x 14) extra bits are generated, but 4 dots on the left of the next 15th character are written into this portion.

The timing of this writing may be set arbitrarily.

Next, in order to read out the display signal stored in the shift register 29 in this way and display it on the picture tube 16, the above-mentioned doubling circuit is used in the shift pulse generation circuit 30 for the shift pulse for readout and display. 3.58 M for 38
A 7.16 MHz shift pulse is generated using a clock signal obtained by doubling the Hz color subcarrier signal, and this is added to the shift register 29 to generate a 7.16 MHz shift pulse.
The display signal is read out by the shift pulse, and is added to the signal mixing circuit 15' via the output gate circuit 36, where it is superimposed with a normal video signal and supplied to the picture tube 16, where it is applied to the display section 2 of the screen 1. Displays characters etc. representing news.

At this time, by returning the readout output of the shift register 29 to the input of the shift register 29 via the input switching circuit 28, the stored contents can be circulated and the same display can be read out repeatedly.

Note that the generation timing of the shift pulse generated from the shift pulse generation circuit 30 during this readout display is determined based on the vertical synchronization signal and the horizontal synchronization signal so that the display image can be displayed in a predetermined display section 2 on the screen 1. It is necessary to strictly set the timing to occur after a predetermined time, but this is achieved by counting by a counting circuit using vertical and horizontal synchronization (No. 8 and shift pulses).

For example, the 16-bit shift register 26 stores 1/1 of the color subcarrier frequency during the 20th horizontal scanning period and during the period when the display signal is selected by the data selection pulse.
The selected display signal is written by the second shift pulse.

On the other hand, in the 4096-bit shift register 29, in the 200th to 215th 16 horizontal scanning periods of each field,
And 35.7 after 20μsec from the horizontal synchronization signal
716MH during a period of 5μ5ec (256 bit period)
It is driven by 256 bits per horizontal scanning period by the shift pulse of z.

The display signal is read out during the clock period up to the 255th bit, and the display signal is read out during the clock period up to the 255th bit.
The display signal from the 6-bit shift register 26 is written as described above.

At this time, a 1-bit shift pulse is applied to the 16-bit shift register 26 at the clock time of the 256th bit of each horizontal scanning period, and the display signal is read out bit by bit and supplied to the 4096-bit shift register 29. .

In principle, each shift register 26 and 29 stops within these periods.

Further, the output gate circuit 36 is opened only during the display section 2 so as to transmit only the display signal read out from the shift register 29 by a shift pulse having twice the frequency of the color subcarrier to the picture tube 16 for display. The vertical and horizontal synchronization signals are used as reset signals, and the horizontal synchronization signals,
It is opened by the gate pulse generated from the output gate pulse generation circuit 37 only during the display section 2 by counting the shift pulses.

Next, a description will be given of means for rolling such a display from left to right or from right to left on the screen.

Now, a display signal for displaying as shown in Figure 1 has been sent, and the signals for one column separated as described above are
Assume that the data is stored in the 6-bit shift register 26.

At this time, when the input switching circuit 28 is switched to circulate the stored contents of the shift register 29 and the shift pulse generation circuit 30 generates only 4096 display shift pulses during the scanning period of the display section 2, it becomes static as described above. will be displayed.

Therefore, after such display shift pulses have been generated in the display period 2, only one roll shift pulse is added to the shift register 29 from the shift pulse generation circuit 30 separately from the display shift pulses.

Then, the stored contents of the shift register 29 will be shifted one column to the left as shown in FIG. A rolled display is made.

At this time, the input switching circuit 28 is switched to the shift register 26 side after the roll shift pulse is applied and until display section 2 of the next field starts, and the input switching circuit 28 is switched to the shift register 26 side. If a new display signal is written from the shift register 16 to the bits where A1-A16 were stored, this new display signal is stored in the rightmost column of the shift register 29, and is displayed at the right end of display section 2. Ru.

Therefore, by repeating this every field and writing new display signals to the rightmost column of the shift register 29 one after another, a display that rolls from right to left like lightning news will appear on screen 1. is to be done.

It goes without saying that if the number of display shift pulses is reduced by one instead of adding one roll shift pulse, a roll from left to right can be displayed.

Furthermore, all of the above explanations have been made with reference to the case where the shift register 29 is used as a storage means for display signals. Needless to say, it can be applied to all cases.

Furthermore, in this system for transmitting display images such as character images, the display signal is transmitted at a frequency of 3.58 MHz on the transmitting side.
The color subcarrier signal is pulsed and sent as a clock signal.

Therefore, on the television receiver side, a clock signal may be created based on the color tone carrier signal synchronized with the color burst signal, and the display signal may be received and demodulated using this clock signal.

In that case, a pulse with a horizontal period is required as a reset pulse for the various counter circuits used in the reception and demodulation circuits, but the horizontal pulse generated in the television receiver generally depends on the power supply voltage, beam current, and horizontal oscillation frequency. Due to the influence of adjustments, etc., it has phase fluctuations of several hundred nanoseconds.

At the same time, the composite synchronization signal separated from the video signal is affected by the average gradation of the video, noise, etc., and also includes phase fluctuations of several hundred nanoseconds.

Therefore, when various counter circuits are controlled with horizontal pulses that have phase fluctuations for each horizontal scan, if the width of the phase fluctuations is wider than the period of the clock pulse of the counter, then Naturally, counting errors occur, resulting in disadvantages such as distorted shapes of displayed images such as reproduced characters, and vertical lines swaying from side to side.

Therefore, in the present invention, in order to eliminate these adverse effects, the initial pulse 9 sent at the beginning of the horizontal period during which display signals are sent as shown in FIG. 2 is used as a reset signal, and 3. A 7.16 MHz signal obtained by doubling the chrominance subcarrier signal of 58 ME (z) is used as a clock signal, and a counter circuit with a frequency division of 1/455 is configured, whereby synchronization is performed only once in one vertical period. In this way, until the next vertical period, a stable horizontal periodic pulse without jitter for each horizontal scan is obtained from the counter circuit.

Hereinafter, the circuit configuration of the main parts of a television receiver according to an embodiment of the present invention will be explained using FIG. 7.

Here, in order to achieve the above-mentioned purpose, a color carrier wave signal of 3.58 ME (z (needless to say, synchronized with the color burst signal) is extracted from the color demodulation circuit 19,
A 7.16 MHz clock signal is obtained by doubling it in a doubling circuit 38, and this is sent to a binary 4-bit counter 39, 40,
A counter 42 having three stages of 41 connected in cascade counts down and divides the frequency into 1/455 to obtain a horizontal pulse having a period equal to the horizontal period.

NAND gate 43 and NOR gate 44 are counters 42
This is for resetting when 455 power is counted in order to set the frequency division ratio at 1/455.

In order to operate this counter 42 accurately in synchronization with the detection of the initial pulse 9, the data separation circuit 21
The output signal of is used as the trigger signal input, and the flip-flop 4 is connected to J- which is triggered by the falling edge of the initial pulse 9.
5 is provided, and its Q output and a signal obtained by slightly delaying the Q output by a resistor 46 and a capacitor 47 are supplied to the NAND gate 4B to generate an initial pulse detection pulse only at the falling edge of the initial pulse 9. , this is negative logic N
The counter 42 is supplied via the OR gate 44 to the reset terminals of the respective binary 4-bit counters 39, 40, and 41 of the counter 42 to reset the counter 42. The counting operations are synchronized.

Note that this J- flip-flop 45 is reset for each field by a vertical synchronization signal from the synchronization separation circuit 17.

In this way, the counting operation of the counter 42 can be accurately synchronized with the initial pulse once per vertical period when receiving the initial pulse, and the next initial pulse will be received in the ranking period in the next vertical direction. Until then, a stable horizontal pulse can be obtained from the output terminal 49.

Then, 2 of the color subcarrier frequency is divided by the counter 42.
The double clock signal is precisely synchronized with the color burst signal of the received color television signal, and the signal obtained by dividing this into 1/4 s 5 becomes exactly the horizontal scanning frequency (according to the broadcasting standard). horizontal scanning frequency -2×
Since the color subcarrier frequency is set to /455), a stable horizontal pulse without jitter is obtained for at least one vertical period.

In the case of the conventional horizontal synchronization signal that resets each horizontal period, the jitter effect of the horizontal synchronization signal for each horizontal period is directly reflected in the output horizontal pulse, and as a result, the display position of characters changes from left to right for each horizontal scanning line. However, in this device, there is no jitter in each output horizontal pulse within one vertical period, so this problem is eliminated.

Note that in this device, the position of the initial pulse may shift slightly, so the display position may change slightly to the left or right for each vertical period, but the displayed characters themselves will not be deformed, so The display is easy to read.

In this way, extremely accurate horizontal pulses used for reading display signals from the shift register 29 can be obtained at the horizontal pulse output terminal 49. By using it as a reference signal, accurate and good display can be performed.

Note that the NAND gate 50 is added in case it is desired to obtain a pulse of an arbitrary period in the horizontal period, and can be used, for example, as a data selection pulse of the data selection circuit 23.

Furthermore, all of the above explanations have been made with reference to the case where the shift register 29 is used as a storage means for display signals. Needless to say, it can be applied to all cases.

As described above, according to the present invention, the viewer can freely select and display a display image such as news on the screen of a television receiver, and the display is superimposed on the television signal. By detecting the initial pulse for display that is sent before the display signal and dividing the frequency of the color subcarrier signal using this as a reference, a pulse with an accurate horizontal period is obtained and the accurate display signal is transferred from the shift register. It is possible to read out information, and to perform accurate and good display.

[Brief explanation of drawings]

Figures 1a and b are diagrams showing images displayed on the television receiver of the present invention, Figure 2 is a front view of the screen of the television receiver, and Figures 3a and b are views used in the television receiver. Figure 4 is a block diagram showing the basic configuration of the television receiver;
5 and 6 are block diagrams illustrating the operation of the shift register in the television receiver, and FIG. 7 is a block diagram of essential parts of the television receiver according to an embodiment of the present invention. 1...Screen, 8A, 8B, 8C, 8D
, 8E...Display signal, 16...
Picture tube, 20...Display circuit, 21...
Data separation circuit, 24...Shift register, 3
8...2 multiplier circuit, 39, 40, 41...
...Binary 4-bit counter, 42...Counter, 43...NAND gate, 44...
・OR gate, 45...Flip-flop on J-, 46...Resistor, 47...Capacitor, 48...NAND gate, 49...・
・Horizontal pulse output terminal.

Claims (1)

[Claims] 1. Receives a video display signal superimposed and sent during the vertical blanking period of a television signal, stores this display signal in a serially readable memory circuit, and reads the picture tube screen from this memory circuit. The display signal is read out in synchronization with the scanning of the picture tube, and a display image is projected on the screen of the picture tube, and the color subcarrier signal synchronized with the color burst signal of the television signal is doubled and a 455-minute The frequency is divided by 1 to obtain a horizontal period pulse, which is inserted immediately before the display signal in each successive vertical blanking period and is sent at a vertical period, so that the reception timing of the display signal is aligned. A television receiver characterized in that the phase of the frequency division is synchronized with reference to an initial pulse for controlling the display signal from the storage circuit.