JPS6160633B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives and stores a still image signal that is superimposed and sent separately from the video signal of a normal television broadcast image during the vertical retrace period of a television signal, and then freezes the signal. Regarding an image display device, when receiving a signal in which still image signals of multiple programs are arranged in chronological order for each program and sent together with a row code signal, reception of any of the programs. During the waiting period from when the program is specified until the still image signal of the program actually starts to be received, the still image of the non-designated program that is received each time is displayed on the screen in a special manner. ,
An object of the present invention is to provide a device capable of notifying a viewer that it is in a standby state.

The following system has been considered as one of the systems for transmitting still images such as characters and figures using television signals.

In this system, one page of still images to be transmitted is made up of 200 television horizontal scanning lines, and each line is made up of 256-bit picture elements. Therefore, the total number of picture elements for one page is
It is 51200 bits.

Furthermore, a program code Pr indicating which program the still image belongs to and a page code Pa indicating its page number are attached to a portion of each still image, such as the upper left end portion.

Then, on the transmitting side, such a still image is scanned in the horizontal direction sequentially from the upper line as shown by the dashed line in FIG.
An image signal V of 256 bits per line is obtained, and as shown in FIG.
One line is superimposed and sent at the 283rd H. At the same time, the start signal indicates the reference phase of all signals
STX, a 4-bit program code signal PC indicating which program the image signal V belongs to,
A code signal such as an 8-bit line number signal LN indicating which line from the top of the still image the image signal is on is also superimposed and transmitted as a still image signal.

On the other hand, the image signal V is superimposed one line per field in the above manner starting from the upper line of the still image, and the image signal of one page of one program, that is, 200 lines, is Continuously overlap between 200 consecutive fields. However, before the transmission of these 200 lines,
In the field, in order to facilitate control on the receiving side, only the above code signals are superimposed and the image signal V
are not superimposed. Therefore, the image signal for one page is
It will be transmitted in 201 field periods, or 3.35 seconds.

Furthermore, in order to transmit a wide variety of still images such as news and weather forecasts, it is necessary to increase the number of programs; for example, about 10 programs are transmitted. In that case, for each program, one page worth of still image signals is continuously transmitted across 201 fields as described above, but when transmitting 10 programs, such one continuous program is transmitted continuously. Unit 1
As shown in Figure E, still image signals for 10 programs (A, B, ..., R, N) are arranged in chronological order and transmitted. According to such a transmission method, still image signals for 10 programs are transmitted one time in 33.5 seconds.
Still image signals of the same program will be transmitted every 33.5 seconds.

However, when receiving a still image signal sent by such a transmission method and displaying the still image, the still image signal of one program is transmitted for 3.35 seconds every 33.5 seconds as described above. Therefore, the receiving side must wait up to 30.15 seconds after specifying the desired program to begin receiving the still image signal of the specified program.

As a method to shorten this waiting time as much as possible, a method can be considered in which the still image signal in the portion corresponding to the space between lines is not transmitted. However, the last line portion of the inter-row space for transmitting the row code signal is transmitted. According to this method, 7 fields per line can be reduced compared to the 8 fields required per line for interline space transmission,
Although 56 field periods per program can be saved, the waiting time is only reduced by about 28% in this way, which still requires a considerably long waiting time.

If this waiting time is short, there will be no problem, but if it is long as described above, the viewer will not be able to tell whether or not the reception operation is being performed correctly for a long time until the still image is displayed. arise.

Therefore, when receiving a still image signal using such a transmission method, the present invention provides a screen in a special manner every time a still image of a program other than the specified one is received, from when a program is specified until the reception of the specified program is started. It is an object of the present invention to provide a device that can easily display the standby state during the waiting time by displaying the above information on the screen.

For this reason, the present invention is characterized in that only at least one of the program symbol and the page symbol in the still image is displayed on the cathode ray tube during the standby state.

An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

In the figure, 1 is a receiving circuit that includes a tuner, VIF circuit, video detection circuit, etc. and receives a normal television signal and a still image signal superimposed thereon, and 2 is a waveform of the output of the receiving circuit 1 into a binary signal. A waveform shaping circuit for shaping, 3 a synchronization separation circuit, and 4 a horizontal/vertical pulse generation circuit for generating horizontal/vertical signals. Using these horizontal and vertical pulse signals, the sampling gate pulse generation circuit 5 outputs the 20th H and 283rd H (hereinafter referred to as the 20th H) on which the still image signal is superimposed.
A sampling gate pulse is generated at the 283rd H (the 283rd H will be omitted), and the 20th H sampling circuit 6 is controlled to extract the still image signal superimposed on the 20th H.

The extracted still image signals are added to the buffer memory 7, and the image signal V thereof is temporarily stored. The buffer memory 7 is an image signal V for one line.
It is composed of a static shift register or the like having a storage capacity of 256 bits.

The image signal V for one line stored in the buffer memory 7 is transferred to the main memory 9 at a predetermined timing via the input gate circuit 8, and stored at a predetermined storage location. This main memory 9 has a storage capacity that can store image signals for one page of still images, that is, 256 bits x 200 lines = 51200.
It has a storage capacity of bits, and is composed of, for example, a static shift register.

Thereafter, the image signal stored in the main memory 7 is transferred to the main memory 9 in synchronization with the scanning of the display cathode ray tube.
By reading out the signal from the source and applying it to the cathode ray tube 12 via the output gate circuit 10 and the video amplification circuit 11, a still image is displayed in a predetermined manner as shown in FIGS. 3A and 3B. In Fig. 3, A shows the program symbol of a still image of a non-designated program during the standby period.
The display mode when only Pr and the page symbol Pa are partially displayed at the top left edge of the screen, B receives the still image signal of the specified program and displays the entire still image of the specified program for one page. This is the display mode when

Next, the input/output control section of the image signal V and the clock control section of both memories 7 and 9 for realizing such a display mode will be explained.

First, in the input and clock control circuit 13, 14 is a main clock generation circuit, which synchronizes with the scanning of the cathode ray tube 12 and operates from the 41st H to the 41st H to project a still image as shown in FIG. 3B.
During the 200H period up to the 240th H, a main clock of 256 bits per 1H is generated and supplied to the main memory 9 via the OR gate 15. As a result, the main memory 9 is clocked by 51,200 bits per field, and the stored contents are circulated once per field. The main clock is generated by multiplying and dividing the color subcarrier, and its frequency is desirably approximately 6 MHz or higher, and must be strictly synchronized with the horizontal synchronization signal.

On the other hand, 16 is a transfer clock that generates a transfer clock for transferring and storing the image signal V from the buffer memory 7 to the main memory 9 so as to be suitable for the roll display when still images are displayed as necessary. In the generating circuit, this transfer clock also generates a clock of 256 bits per 1H, similar to the main clock. However, while the main clock is generated from the 41st H to the 240th H, the transfer clock is generated always or only at the 262nd H in this embodiment. The transfer clock is applied to buffer memory 7 and main memory 9 simultaneously via AND gate 17 and OR gate 15.

Reference numeral 18 designates a circuit for specifying whether or not to display such a roll. When displaying a roll, the AND gate 19b is made conductive to supply a clock for roll transfer at the 262nd H, and the image signal from the buffer memory 7 is transferred to the main memory 9. Forward. At this time 1
The image signal V for each line is transferred to the storage position of the bottom line of the main memory 9, and the storage position of all image signals in the main memory is shifted upward by one line at a time, so it rolls from the bottom to the top. Display a still image. Conversely, when displaying a stopped display without rolling, the AND gate 19a is made conductive, and when a line match signal is received from the line comparison circuit 20, the image signal is transferred from the buffer memory 7 to the storage location of a predetermined line in the main memory 9. and write. That is, 21 is a line number code extraction circuit that extracts and stores a line number signal attached to a still image signal, 22 is a line counter that counts horizontal pulses;
Now, the 41st H, which corresponds to the top end of the still image during scanning by the cathode ray tube 12, is set as "1", and the horizontal scanning lines are counted from now on to find out how many lines from the top of the still image have been scanned, that is, the main memory. Since the line number signal extracted from the still image signal in the line comparison circuit 20 is detected and outputted, it is detected which line storage position in 9 is currently the read or write position.
LN is compared with the line detection output from the line counter 22, and when the two match, that is, when the main memory 9 has been clocked to the storage location of the same line as the received still image signal.
Generates a coincidence output that goes to a low level over a width of 1H period, applies it to the input gate circuit 8 via the AND gate 19a, and sends the image signal for one line from the buffer memory 7 to the storage location of the line in the main memory 9. Transfer and memorize. When storing in this way, each time a still image signal of a designated program is sent in order from the upper line, the image signal is stored in sequence from the storage position of the upper line in the main memory 9, and the still image is stored. You can display the image sequentially from above while it is stopped.

The above storage operation is the same whether in the standby state or when receiving a designated program.

In this way, the image signal of a still image can be stored in the main memory 9, so that when in the standby state, only the image signal of the program code Pr and page code Pa can be read out from the main memory 9 as shown in FIG. 3A. When a designated program is received, if all the image signals are read out, a display as shown in FIG. 3B can be made.

Next, output control is performed to switch the display as shown in Fig. 3 between a standby state in which still image signals other than the specified program are still being received after the program has been specified, and when a still image signal of the specified program has been received. Let me explain about the section.

To do this, first, the program code signal PC of the 20th H still image signal extracted by the 20th H sampling circuit 6 is extracted by the program code sampling circuit 23, and then until another program code signal PC is sent. Hold. On the other hand, in the program designation circuit 24,
An arbitrary program is specified from among the ten types of programs up to ``nu'' by operating, for example, a pushbutton switch. At the time of the specified operation, no matter which program is specified, the operation detection pulse is always generated.
Flip-flop 26 via NOR gate 25
In addition to this, reset this. At the same time, a code signal of the designated program is created and added to the program comparison circuit 27, where it is compared with the program code signal of the still image signal being received.When the two match, that is, the still image signal of the designated program is generated. is received, a match signal is generated to set flip-flop 26.

28 is an output control circuit that is switched by the output of the flip-flop 26, and includes a flip-flop 29 that determines the display period in the vertical direction and a flip-flop 30 that determines the display period in the horizontal direction.
and a group of gates for their control.

First, in the standby state after program specification, the flip-flop 26 is in the reset state, so its Q terminal output becomes high level and the AND gate 3
1b and 32b and NAD gate 33b are brought into conduction. Therefore, at this time, the pulses at the beginning of the 41st and 59th H output from the line counter 22 are applied to the flip-flop 29 via the AND gates 31b and 32b and the NOR gates 34 and 35 to set and reset them. 41st-Hth
A high-level output is generated only during the period up to the 58th H, that is, during the first line of the still image. On the other hand, every H256 generated from the main clock generation circuit 14
Using a bit-by-bit main clock, the first bit detection circuit 3 detects the beginning of the first bit of each H.
6 and flip-flop 30 at the time of detection.
Then, the end of the 50th bit is detected by the 50th bit detection circuit 37, and the flip-flop 30 is reset at the time of detection. Therefore, at this time, an output that is at a high level is generated only from the 1st bit to the 50th bit, that is, from the left end of the still image to the 50th bit. This output is
It is added to the NAND gate 39 via the NAND gate 33b and the negative logic AND gate 38, and is synthesized here with the output of the flip-flop 29.
An output control pulse that is at a low level only between the 1st bit and the 50th bit of each H is generated and applied to the output gate circuit 10.

The output gate circuit 10 controls the output of the image signal from the main memory 9 and at the same time controls the output of the normal television reception signal obtained by the reception circuit 1. Cathode ray tube 1 displays only television images
Analog switch circuits 40a and 4 switch in opposite modes to each other so that when a still image signal is received, the normal television reception image of the portion where the still image is displayed is erased.
0b.

Therefore, in the above standby state, the output control circuit 28
If the output gate circuit 10 is controlled by the control pulse from the main memory 9, the analog switch 40b is made conductive only from the 1st bit to the 50th bit from the 41st H to the 58th H, and the main memory 9 is turned on only during that period. The readout image signal can be extracted from the CRT 12, and only the program code Pr and page code Pa of the non-designated program can be displayed on the cathode ray tube 12 as shown in FIG. 3A. This makes it possible to inform viewers of certain events and the programs and pages being sent at that time in an easy-to-understand manner.

Next, when the still image signal of the designated program is received, the flip-flop 26 is set by the match signal from the program comparison circuit 27 as described above, so that its Q terminal output becomes high level.
AND gates 31a and 23a and NAND gate 33a are made conductive. Therefore, the flip-flop 29 is set at the end of the 20th H and reset at the beginning of the 262nd H.
A pulse is generated during the 261st H, that is, during almost the entire period in the vertical direction of the screen. On the other hand, the NAND gate 33a allows only the horizontal blanking pulse to pass through. Therefore, at this time, the NAND gate 39
From 21st to 261st H, a control pulse that becomes low level during all periods except the horizontal blanking period is generated, so the output gate circuit 10 outputs all the image signals for one page read from the main memory 9. As shown in FIG. 3B, all the still images for one page of the designated program can be displayed.

In this way, in this device, the display mode of still images can be changed between the standby state and when a designated program is received, so that even in the standby state, it can be displayed in an easy-to-understand manner.

Note that in the above embodiment, both the program code Pr and the page code Pa are used, but the same effect can be achieved even if one of them is omitted and only one of them is displayed. Needless to say, it can be done.

Further, the specific configuration circuit of such a device is not limited to that of the above-mentioned embodiments,
It can be widely used as long as it has similar effects.

As detailed above, in the still image signal device of the present invention, still image signals of still images of a plurality of programs in which at least one of a program code and a page code is attached to a portion of each still image are arranged in chronological order. Also, within each program, a signal is received that is superimposed during the vertical retrace period of the television signal so that it is sent continuously on a page-by-page basis, and a still image of the designated program is received from among the still image signals sent above. In the standby state until a signal is received, at least one of the program symbol and page symbol of the still image is displayed, and when the still image signal of the designated program is received, all one page of the designated program is displayed. It is characterized by displaying still images.

Therefore, even if the still image signal of the specified program is not received immediately after the still image program is specified,
By displaying at least one of the program code and page code of the non-designated program during the standby state, it is possible to clearly notify the viewer that the program is in the standby state.

[Brief explanation of the drawing]

FIGS. 1A, B, C, D, and E are schematic diagrams and waveform diagrams for explaining a still image signal transmission system, and FIG. 2 is a block diagram of a still image receiving device in an embodiment of the present invention. 3A and 3B are front views showing the display mode of the device. 1... Receiving circuit, 2... Waveform shaping circuit, 3...
Synchronous separation circuit, 4...Horizontal/vertical pulse generation circuit, 5...20H sampling pulse generation circuit, 6...
50H sampling circuit, 7... Buffer memory, 8...
Input gate circuit, 9... Main memory, 10...
Output gate circuit, 11... Video amplification circuit, 12...
...Cathode ray tube, 13...Input and clock control circuit, 14...Main clock generation circuit, 16...
Roll transfer clock generation circuit, 18... Roll display designation circuit, 20... Line comparison circuit, 21...
...Line number code extraction circuit, 22...Line counter, 23...Program code extraction circuit, 24...
Program designation circuit, 26...Flip-flop, 27
...Program comparison circuit, 28...Output control circuit, 29
...Flip-flop, 30...Flip-flop, 36...1st bit detection circuit, 37...50th bit detection circuit.

Claims (1)

[Claims] 1 Still image signals of still images of a plurality of programs in which at least one of a program code and a page code is attached only to a part of one line of each still image are arranged in chronological order, and each still image is arranged in chronological order. During a program, the signal superimposed during the vertical retrace period of the television signal is received so that it is sent continuously on a page-by-page basis, stored in memory, and read out from this memory to display a still image. At the same time, during the standby state after the still image signal program designation until the still image signal of the designated program is received, the program symbol and page symbol of the still image are displayed while displaying the reception screen of normal television broadcasting. reading at least one of the above from the memory and displaying only a portion of one line of the image receiving screen;
A still image receiving device characterized in that when a still image signal of a specified program is received, all still images of one page of the specified program are displayed. 2. The still image display device according to claim 1, wherein display positions of program symbols and page symbols are controlled by counting outputs of horizontal pulses and a main clock.