JPS6133303B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a system for transmitting images such as characters during the vertical retrace period of a television signal. Conventionally devised character transmission systems, such as telescan systems, receive this and print multiple lines (2 lines) of characters across the screen of a television receiver.
line), it will be displayed as shown in Figure 1. If each line represents a kanji character, at least 15 to 16 dots are required, so it is set to 16 vertical dots, that is, 16 lines. Also, the space between each line is one line, or 16 lines. If this space is 1
If a width other than one line is selected, it becomes necessary to change the way image signals are stored in the main memory depending on whether a figure is displayed without space or a character with multiple lines, which complicates the receiver. Therefore, it is absolutely necessary to do the above, and there are restrictions on the characters and figures that can be transmitted. Furthermore, when transmitting a small figure consisting of pixels of 16 vertical dots or more, it is necessary to use two lines, one line for characters and one line for spaces, and there is the inconvenience that no other changes can be made. Therefore, an object of the present invention is to eliminate such conventional drawbacks and provide a transmission method that can transmit free characters and figures, and also allows the configuration of the receiver side to be arbitrarily selected from a wide range. It is something to do. First, the principle of image display in the method of the present invention will be described with reference to FIG. In addition, in the following explanation, one horizontal scanning line (one line) of the television screen is used.
is expressed as 1H. In a normal television receiver, there is about 10% vertical overscan, and about 220% in the center.
The part from ~230H is displayed. Therefore, we decided to give sufficient margin here, and in the vertical direction
192H (=24H x 8 lines) is used, and on the other hand, in the horizontal direction, 256 dots are used, and as shown in Figure 2, one picture element is composed of 256 dots x 192H = 49152 dots. do. this is
This is advantageous because it can be divided into 1024 x 48 pieces, and if a 1K bit RAM or shift register is used, the main memory can be configured with just 48 pieces. The screen is divided into 8 lines of 24H each, as shown by the solid line in Figure 2, and the upper part of each line is used for sentences containing mixed kanji and kana, as shown by the broken line in Figure 2. Send and receive. This part should be set to an appropriate value between 15 and 20H, and as long as the space is 4H or more, there will be no problem in reading the text. Optional H for figures etc.
Choose any number. Next, the transmission and reception of image signals in each row are shown in Figures 3 and 4.
This will be explained with reference to the figures. First, the number of programs to be transmitted and received is set to eight, and they are arranged in chronological order and superimposed on the 20th and 283rd H (hereinafter only the 20th H will be described) during the vertical blanking period as shown in Figure 3A. shall be taken as a thing. 25 per program in the overlapping 1H period
Allocate bits, use 1 bit as a control bit, and use the remaining 24 bits as the 1 bit to be sent and received.
It is assigned to a 24-bit image signal for one column in the vertical direction of one row on the screen. That is, for example, the first line of the program A is "Character transmission..." as shown in FIG. 4A.
...'' and the nth line of another program B is ``television...'' as shown in Figure 4B (program C and subsequent parts are omitted). As shown by the chain lines in A and B, take out the image of one vertical column in each row and correspond to the black and white of each point constituting the character in order from the top to obtain an image signal with a signal waveform as shown in Figure 3B. . It should be noted that for Program A, Program B, and other programs, it is arbitrary to decide which position on the screen, that is, which row of images, one vertical column is superimposed on which 1H period, and for each program, the start, end,
Line breaks etc. can be done independently. The first feature of this method is that a 24-bit code signal is added in front of the image information (200 bits) as shown in Figure 3, and two-thirds of the code signal, or 16 bits, is used for sampling at the receiver. The point is that a pilot signal is sent as a reference for the start code, and the remaining 8 bits constitute a start code. Therefore, a total of 224 bits of information are sent and received, and the width of each bit can be freely selected within the transmission band of the television signal, and there is no color burst signal as in black and white television broadcasting. The sampling clock for reception can also be easily reproduced from the pilot signal. The second feature is that a complex control signal can be sent by using one bit of the control signal. That is, for example, when the control signal is "0", the subsequent 24-bit signal is used as an image signal, stored in the main memory, and controlled to be read out in accordance with the horizontal and vertical scanning of the television receiver. This allows characters as shown in FIG. 4 to be displayed on the screen. On the other hand, when the control signal is "1", it means that the following 24-bit signal is not an image signal but a control signal that determines the display or storage method, etc.
Bits are used for control. An example of the breakdown is shown in Table 1 below. There may be only ²²⁴ types of control, but in reality less than 100 types are sufficient.

【table】

[Table] Next, a receiving apparatus according to an embodiment of the present invention using such a system will be described with reference to FIG. In the figure, 1 is a tuner and video intermediate frequency amplification circuit, 2 is a video detection circuit, and 3 is a synchronization separation circuit, which are similar to those in a normal television receiver. On the other hand, 4 is a waveform shaping circuit which returns the pulse waveform of the distorted signal that has passed through the television transmission band to the correct pulse waveform as shown in FIG. 3B, which is the same as that on the sending side. 5 uses vertical and horizontal synchronization signals to synchronize the third signal superimposed on the 20th H (and 283rd H, the same applies hereinafter).
A circuit that generates a gate pulse to extract a signal as shown in the figure, 6 is its output, a gate circuit that gates the output of the waveform shaping circuit 4 and extracts only the 20th H signal, 7 is a waveform shaping circuit 4 8 detects the start code ("11001001") in the extracted signal, and detects the phase of the sampling clock generated by the sampling clock generator 9. This is a circuit that combines the following. The sampling clock generation circuit 9 outputs the sum of A program...H program.
This circuit generates a clock for sampling a 200-bit image signal. 10 is a line counter that counts the horizontal synchronizing signal or pulses (flyback pulses, etc.) synchronized therewith; 11 is a circuit that generates a transfer clock for transferring the image signal from the buffer memory 15 to the main memory 18; 12 is a main circuit; This circuit generates a display clock for reading out the contents of the memory 18 in accordance with the horizontal and vertical scanning of the television receiver.
Furthermore, 13 is a program designation circuit for inputting which program from A to H programs is to be designated, and 14 is a 25-bit portion of the designated program from the output of the sampling clock generation circuit 9 according to the designation of the program designation circuit 13. This circuit takes out only the sampling clock of the program, and uses the output of the clock gate 14 to clock a buffer memory 15 and a control bit detection circuit 16, and takes out a 25-bit signal of a designated program, for example, program B, from the output of the gate circuit 6. The first 1-bit control bit enters a control bit detection circuit 16 consisting of a 1-bit memory, and the remaining 24-bit signal enters a buffer memory 15.
As an example of this buffer memory 15, three cascade-connected 8-bit serial input/parallel output type shift registers can be used, and necessary ones of the parallel outputs are connected to the control code detection circuit 17. . 19 is a circuit for amplifying the image signal read out from the main memory 18, and 20 is a cathode ray tube for display. Now, suppose that program B is designated from the program designation circuit 13. At this time, the portion of the B program is extracted from the signal as shown in FIG. 3 using a 25-bit sampling clock for the portion corresponding to the B program. At this time, if the control bit is "0", the stored content of the buffer memory 15 is an image signal, so it is transferred to the main memory 18 every H1 bit during the subsequent 24 hours from the 21st H to the 44th H. do. Adding one additional bit to the main memory 18 and adding a roll shift clock results in a display in which the characters roll from right to left on the screen in a lightning sign pattern, similar to the receiver in known telescanning systems. can be done. In this case, if a main memory 18 of 16 x 256 = 4096 bits is prepared and only the 16-bit image signal excluding the space part is stored, the configuration will be almost the same as that of the conventional receiver, and the start code detection circuit 8 and a control bit detection circuit 16 are added. The above is sufficient as the minimum receiver that can be used in this system, but in this case, the number of characters is 1.
Only lines will be displayed. Next, the characteristic clock regeneration portion of the receiver of this system will be described with reference to FIG. In the following explanation, it is assumed that the number of programs is eight, the pulse width of one bit of the signal is 230 nsec (that is, the data rate is about 4.35 MHz), and the arrangement of each waveform and code signal is as shown in FIG. In FIG. 6, 21 is a delay circuit, which moves the leading edge of the gate pulse for 20H extraction from the gate pulse generation circuit 5 to the position _t10 in FIG. 7, that is, between the color burst signal and the code signal. The flip-flop 22 is set. As a result, the Q output of the flip-flop 22 becomes high level, as indicated by G in FIG. 7, a little before the code signal. On the other hand, 23 is a band amplifier circuit with a center frequency of 2.17 MHz, which passes only the fundamental wave component of the pilot signal from the received signal as shown in FIG. 7A. Therefore,
The output is as shown in FIG. 7B, and only the pilot signal part is taken out in the form of a sine wave, but if there is a 2.17 MHz component in other parts, it appears as an output, so the gate circuit 24 extracts the pilot signal part (t ₁₀ ~ t ₃₅ ) is gated by the output G of the flip-flop 22 and taken out. Gate circuit 2
If the output of 4 is made into a sufficiently large amplitude and shaped into a pulse waveform, then by differentiating this with the capacitor 26 and the resistor 27, a differential output as shown in Fig. 7C can be obtained, and the output can be converted to an inverter. By inverting at 25 and differentiating at capacitor 29 and resistor 30, a differential output with opposite polarity as shown in FIG. 7D can be obtained. Only the positive pulses of the differential outputs C and D are taken out by the diodes 28 and 31 and combined as shown in FIG. 7E. If this is amplified by the 4.35MHz tuned amplifier 33, a 4.35MHz signal as shown in FIG. 7H is obtained. On the other hand, if the combined signal E of both differential outputs is counted 15 times by the counter 32 to obtain a pulse as shown in FIG _. Becomes a low level. Therefore, from then on, the gate 24 is shut off, and the pulse shown by the broken line in FIG. Pulse F
Even if the differential output E is the 16th instead of the 15th,
Also, there is no problem with the 12th to 14th pieces. According to experiments, even when the clock pulse generation circuit 34 is a ringing generation circuit using a crystal oscillator, if the differential output E is repeated 12 times or more, the ringing waveform continues for about 1 hour after that, and after _t35 . It has been confirmed that the phase of the clock pulse I matches well with the phase of the pilot signal, and the same applies to the phase pull-in when the clock pulse generation circuit 34 is an oscillation circuit. In the illustrated example, in view of this point, pulse F is generated at the 15th pulse with a margin of 1 bit. Clock pulse generation circuit 3
The output H of 4 is pulse-shaped by a waveform shaping circuit 35 to obtain a clock pulse I. This clock pulse I is supplied to the 8-bit serial input/parallel output type shift register 8R in the start code detection circuit 8, and the 8-bit start code signal from _t37 to _t51 in the received signal is extracted and its output is In addition to the detection circuit 8G consisting of an 8-input AND gate and an inverter, it detects the start code "11001001" and obtains a detection output as shown in Figure 7J at _t50 , which allows the sampling clock generation circuit 9 to count. Regulate initiation. As described above, this circuit can easily reproduce the sampling clock and detect the start code signal. Next, the control bit detection section will be described. The buffer memory 15 is a 24-bit memory as described above, and the control bit detection circuit 1
Since 6 is a 1-bit memory, these are connected in series to make a total of 25 bits of memory, and the received signal is clocked at the 25-bit position of any of the programs A to H of the received signal. , the detection circuit 16 stores one bit indicated by diagonal lines in FIG. In the simplest one-line horizontal roll display type receiver, this part may be omitted and the received signal may be displayed as it is in a horizontal roll. Next, a configuration for displaying 8 lines on the entire screen will be described. Here, if the control bit of the signal of any program in the transmission signal is "1" and a control signal is sent to the following 24 bits, this control signal is the image of which line. Only the line code that indicates whether
It is assumed that a code signal specifying the 0th to 7th lines of "0111" is sent, and no other control signals are sent. The main memory 18 is divided into 8 parts according to the display of 8 lines as shown in FIG.
1 to 188. If we consider static RAM as the main memory 18 and use six 1K-bit chips (256 bits x 4) at once, there will be 256 picture elements for one horizontal scanning line and 256 pixels for one series of memory. If the bits correspond as they are and input/output selection is performed appropriately, addressing can be common to all row memories 181-188. For example, if only the row memory 181 is extracted and shown, the RAM of 1024K bits is shown in Figure 9.
There are 6 pieces from 181-1 to 181-6, 1K each.
BIT RAM has four input/output terminals (input and output are common), so buffer memory 1
The 24 outputs of the selector 41, the 24 inputs of the selector 41, and the 24 inputs and outputs of the RAMs 181-1 to 181-6 are connected in a one-to-one correspondence. Each RAM address is 8 bits, that is, 2 ⁸ = 256 types,
It corresponds to the number of displayed picture elements. The line counter 10 also includes a 45th H detection circuit 10A, a 1/24 frequency dividing circuit 10B, a 1/8 frequency dividing circuit 10C, a flip-flop 10D, and a 21H detection circuit 10E. First, when the line code is detected (this
_T1-0 field), the output of the control bit detection circuit 16 changes from high level to low level. If a flip-flop is used as the control bit detection circuit 16 as a memory, either positive or negative output is possible, and it is extremely easy to set the output to "0" when the control bit signal is "1". Among the contents of the buffer memory 15, the 10th to 13th row codes in Table 1 are the control code detection circuit 1.
7 in the row code memory, and its contents are held until the next row code is input. When the row code indicates "1st row", the output of the detection circuit 17 is "0000" and is added to the row selector 36, so the output of the selector decoder 37 is the CS (chip) of the row memory 181 of the 1st row. select) terminal is set to low level and the six RAM181-
The input/output terminals I/O of 1 to 181-6 are made active. When the CS terminal is at a high level, the I/O terminal is at high impedance. The row selector 36 is 4 of the 1/8 frequency divider circuit 10C.
This is a selector that switches between the bit output and the 4-bit output of the control code detection circuit 17, and the output of the control code detection circuit 17 is switched to the decoder 3 only for the 21st H by the output of the detection circuit 10E which is at a high level only at the 21st H.
7 to pass. At this time, as described above, the output of the selector decoder 37 is the CS of the row memory 181.
Only the outputs connected to the terminals become low level, and the input/output terminals I/O of each RAM of the row memory 181
The output of the buffer memory 15 is transmitted to the buffer memory 15. On the other hand, when the output of the 21st H detection circuit 10E and the Q output of the control bit detection circuit 16 are applied to the NAND gate 40, the output of only the 21st H of each field except the T _1-0 field becomes a low level, and all rows The W/R (Read/Write) terminal of the memory becomes low level and enters the write state, but since only the CS terminal of row memory 181 is set to low level, the buffer memory 1 is stored at the memory location for 24 lines.
5 outputs are written simultaneously. That is, the control code of the T _1-1 field is not written, but is written from the next T _1-2 field. When displaying characters on the screen, if we decide to add one bit of space at the end of each character, for example, in program A,
In the T _1-2 field, the leftmost 24 bits in Figure 4A are written to address 1 (left edge of the screen) of the row memory 181 in the 21st H, and the chain line portion in Figure 4A is T _1-4 .
Written in the 21st H of the field. That is, the write address counter 38 is an 8-bit binary counter that counts the vertical synchronization signal, but in the _T1-1 field, the flip-flop 10D is set by the output of the control bit detection circuit 16, and the counter 38 is cleared by the output. The flip-flop 10D is reset at the next falling edge of the vertical synchronizing signal in the _T1-2 field, and then starts counting the vertical synchronizing signal. Therefore, in the T _1-2 field, the output of the counter 38 is "00000000", so in the T ₂ field, the 24 bits in the leftmost vertical column of FIG. 4A are written in the "1" address as described above. Similarly, at the counter 38,
If you specify the address one by one for each field,
At _T1-256 of the 256th field, data is written to the right end, and writing of the 24×256-bit image signal for one row to the row memory 181 is completed. Next, if the second line code is detected in the T ₂ field, the line memory 18 from that T _2-1 field is
The image signal is written to 2 in the same way as in the above case. The same is true up to the 8th line, total (256+1) x 8
= 2049 fields (approximately 3.4 seconds) screen 256 x 196 =
Writing of 49152 bits is completed. Note that if the image signal ends in the middle of a line, or if one space bit after the last character of the line is not sent or received, writing for one screen will be completed sooner. Next, reading and displaying the contents of the main memory 18 will be described. W/ of each RAM in main memory 18
The R terminal is at a high level except for the 21st H, and is in a read state. Therefore, it is only necessary to select the output of each RAM according to horizontal scanning. The address of the RAM at the time of reading is the output of the read address counter 39 unless the selector 41 is at the 21st H, and the same address is given to each RAM of row addresses 181 to 188 for every field and every H. The horizontal display position on the screen and the width of each 1-bit picture element are determined by the oscillation start position and oscillation frequency of the display clock generating circuit 12, and can be set arbitrarily, but the oscillation frequency is preferably around 6 MHz. The display position is determined by how long the start of oscillation is delayed from the horizontal synchronization signal. In addition, the display clock generation period is also regulated by the H-th position in the vertical direction from which the display starts, and here, the gated oscillator of the display clock generation circuit 12 oscillates from the 45th H to the 236th H. , to form a display clock. The read address counter 39 is an 8-bit binary counter, and the write address counter 38
It has the same configuration as . Therefore, the horizontal address may be the same for all RAMs in each H. Next, reference numeral 42 denotes a gate for selecting the output of each of the 24 lines of the row memories 181 to 188, which is operated by the 5-bit output of the 1/24 frequency dividing circuit 10B in the line counter 10. That is, the frequency dividing circuit 10B is a counter that divides the frequency of the horizontal pulse by 24 from the 45th H, which is the upper end of the display, and its output indicates which of the 24 lines in each row is the line being scanned. Further, the 1/8 frequency divider circuit 10C divides the output of the frequency divider circuit 10B by 1/8 and outputs a signal indicating the row. In the first row, the output of the frequency dividing circuit 10C is "0" and the output of the selector decoder 37 makes the CS terminal of the row memory 181 a low level. In the second row, the output of the selector decoder 37 is sent to the row memory 18.
Set CS terminal 1 to low level. The same applies below. On the other hand, in the first line of each row (for example, the 45th H), the output of the frequency dividing circuit 10B is "00000", so the gate 42 is connected to the RAM 181-1 shown in FIG.
Select I/O line 1 of , and in the 46th H, select 181-
Select I/O line 2 of 1. Thereafter, in each row, the outputs 181-1 to 181-6 of the RAM are sequentially switched every 1H and selected as the output of the gate 42, and 259 x 192 bits are displayed on the screen between 192H of the 45th H to 236th H of each field. do. The above is the basic operation of the 8-line display. Next, we will describe the processing when switching programs between line codes. First of all, in the normal case, the vertical
192H, gate 4 to display only 256 bits horizontally
It is necessary to apply vertical and horizontal gates to the output of 2, and for this purpose flip-flop 44 is
It is set at the beginning of the 45th H, reset at the output of the frequency dividing circuit 10C, that is, the end of the 8th line, and the Q output is used as a gate pulse in the vertical direction on the screen. It also has a delayed horizontal pulse that regulates the beginning of the display clock.
By setting the FF flip-flop 45 and resetting it at the end of the 256-bit output of the read address counter 39, using its Q output as a horizontal gate pulse, and supplying both to the AND gate 43, 192H x 256 bits as shown in Fig. 2 is obtained. Only the part shown is cathode ray tube 2
0 and other parts are AND gate 4
Blocked by 3. Next, consider the case when the program is changed, when the power is turned on, or when the television screen is switched to text information display. It is assumed that this switching is performed at time _T.sub.X , and in any of the above cases, no row code comes immediately after _T.sub.X. As shown in FIG. 10, 46 is a 3-input NOR gate whose output changes from high level to low level when switching programs, switching text information reception, and turning on the power, flip-flop 47 is set, and its Q output is On the other hand, the output of the flip-flop 16 is at a high level except when the control signal is detected as described above.
The output of NAND gate 48 becomes low level,
The output of NAND gate 40 becomes high level and the 21st H
Even if the output of the 21st H detection circuit 10E becomes high level, the output of the NAND gate 40, that is, the main memory 18
The output to the W/R terminal remains at a high level and no writing is performed, so the display is not displayed from the middle of the line. When using RAM as the main memory 18 and displaying characters from left to right on the screen in the order in which they arrive, if you display from the middle, only one line will be displayed halfway, so it is better not to display until the line code is detected like this. Easy to see. It takes about 42 seconds for 256 fields to complete one line, so even if you switch in the middle, the line will be displayed from the beginning after an average of 2.1 seconds. If the main memory 18 is configured with a shift register and the characters are displayed by roll-shifting from right to left during writing, even if the characters are displayed from the middle of any nth line, the line break will be exactly as shown in Figure 12. When this happens, the last character of the nth line will be on the right edge, so in order to shorten the waiting time, it is better to display it immediately after switching. Note that the flip-flop 47 is not reset until the next (n+1) row code is detected, so the NAND gate 48 is not reset during that time.
The output of the NAND 40 is at a low level, therefore, the output of the NAND 40 remains at a high level, and even in the 21st H, the output is at a high level, and the W/R terminal to the main memory 18 is at a high level, so no writing is done. Next, clearing of the main memory 18 when switching programs, turning on the power, and switching text information will be described. 11th
In the figure, the output of NOR gate 46 triggers monostable multivibrator 49. The output width thereof is made sufficiently wider than one field and is applied to the NOR gate 40G. Therefore, NOR gate 40G
The output of is at a low level for a period sufficiently longer than one field, and the W/R terminal of the main memory 18 is kept at a low level for one field or more, regardless of the output of the NAND gate 40. During this time, if the contents of the buffer memory 15 are cleared using the output of the monostable multivibrator 49, "0" is written and cleared in the main memory 18. With the configuration as described above, a receiver capable of displaying eight lines of characters is configured. Next, if we consider a further development of this device, the first is to display the time, and this is done in accordance with the control code table in Table 1.
After detecting that the 5th bit is all “1”, the 20 bits from the 6th to 25th bits are stored, and the 4th
By converting bit by bit into a decimal number using a decoder, or by directly driving an IC (7 segments) that generates numbers, the time can be displayed in segment type characters. Next, when switching from the state of watching a television program to the state of receiving text information, one line of characters of the specified program can be immediately displayed. That is, the main memory 18 is configured with a shift register, and the first line corresponds to the A program, the second line corresponds to the B program, and the eighth line corresponds to the H program. Write each 24 bits of `` to 8 lines of memory for each field, roll shift from right to left, prepare buffer memory for 1 line separately, and write the corresponding 8 lines of the program at the same time as program specification. Move one line of the program to this buffer memory, display it at any position on the screen (anywhere from lines 1 to 8), and when the next line code signal comes, transfer it to the memory of the line one line above that line. By moving the contents of , it is possible to display without waiting time, and by storing one line from the next line in the buffer memory, it is possible to display one line at a time. Note that no roll is performed after the line code is detected. It is also possible to prepare a buffer memory with a storage capacity for one page in advance, write the image signal of another (sometimes the same) screen slowly while one screen is being displayed, and switch the reading when the writing is finished. good. It is also possible, of course, for the transmitting side to specify the color of the next character or figure using a control code. Table 2 shows a comparison between the performance of the receiver of the present invention and the performance of a conventional character information receiver. As is clear from the table, the system of the present invention has the feature that the receiver side, that is, the broadcast receiver side, can freely select from the simplest receiver to the most complex receiver. the current,
The cost of memory for receivers is expensive, but it is expected that the price will drop significantly from the current price in the future, and if memory becomes cheaper, receivers with memory for two screens will become practical. will be made.

【table】 [Brief explanation of the drawing]

FIG. 1 is a front view showing an example of a display mode in a conventional image transmission system, FIG. 2 is a front view showing an example of a display mode in a system using the image transmission method of the present invention, and FIGS. 3A and 3B are Waveform diagrams showing an example of transmission mode in the same system, Figures 4A and B
5 is a block diagram of an example of a receiver used in the system, FIG. 6 is a detailed circuit diagram of a part of the receiver, and FIG. 7A is a schematic diagram showing an example of a display mode in the same system. ,B,C,D,E,F,
G, H, I, J are waveform diagrams for explaining the operation of the receiver, Fig. 8, Fig. 9, Fig. 10, and Fig. 1.
FIG. 1 is a detailed block diagram of the main parts of the receiver, and FIG. 12 is a front view showing an example of the display mode of the receiver. 1... Tuner, VIF circuit, 2... Detection circuit,
3...Synchronization separation circuit, 4...Waveform shaping circuit, 5...
...Gate pulse generation circuit, 6...Gate circuit, 7
... Clock pulse regeneration circuit, 8 ... Start code detection circuit, 9 ... Sampling clock generation circuit, 10 ... Line counter, 11 ... Transfer clock generation circuit, 12 ... Display clock generation circuit, 13 ... Program specification Circuit, 14...Clock gate, 15...Buffer memory, 16...Control bit detection circuit, 17...Control code detection circuit, 18...Main memory, 19...Amplification circuit, 2
0...Cathode ray tube.

Claims (1)

[Scope of Claims] 1 A pattern of characters or figures represented by a collection of picture elements is divided vertically into n equal parts (n≧2), and horizontally divided into m picture elements, and divided into n, etc. Image signals of x picture elements in the vertical direction of each divided part are taken as a group, and image signals of picture element groups of k different types of programs are sent to an arbitrary horizontal scanning period during the vertical retrace period of the television signal. In addition to time-division arraying, superimposing and transmitting, a control signal is added independently for each picture element group before the superimposition position of the image signal of each picture element group, and in the case of a constant control signal, the subsequent A control code is superimposed instead of the image signal at the superimposition position, and this constant control signal is detected, and the control code following this control signal is used to determine the vertical position of each picture element group on the television screen. Then, the pattern is stored in the memory so that the pattern of the image signal transmitted from the field next to the field on which the control signal is superimposed is displayed in the vertical position based on the determination result of the control code and sequentially from the left edge of the screen. An image transmission method characterized by recording. 2. The image transmission system according to claim 1, wherein the memory is divided into n parts corresponding to the number n of image divisions, and writing and reading are performed for each divided part at once. 3 Each divided part of the memory is configured with a RAM, and the image signals of x picture elements are simultaneously sent to the RAM of the corresponding divided part.
3. The image transmission method according to claim 2, wherein the image transmission method is configured to write data to the image data.