JPS6126171B2 - - Google Patents

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Publication number
JPS6126171B2
JPS6126171B2 JP10242377A JP10242377A JPS6126171B2 JP S6126171 B2 JPS6126171 B2 JP S6126171B2 JP 10242377 A JP10242377 A JP 10242377A JP 10242377 A JP10242377 A JP 10242377A JP S6126171 B2 JPS6126171 B2 JP S6126171B2
Authority
JP
Japan
Prior art keywords
insulating substrate
strip
shaped
chip
shaped insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10242377A
Other languages
Japanese (ja)
Other versions
JPS5436566A (en
Inventor
Hisashi Nakamura
Akio Hyamizu
Kazutoshi Hatanaka
Masaaki Morimitsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10242377A priority Critical patent/JPS5436566A/en
Publication of JPS5436566A publication Critical patent/JPS5436566A/en
Publication of JPS6126171B2 publication Critical patent/JPS6126171B2/ja
Granted legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Non-Insulated Conductors (AREA)
  • Manufacturing Of Electric Cables (AREA)

Description

【発明の詳細な説明】 本発明はチツプ状導体素子の製造方法にかか
り、絶縁基板の表裏面と、相対する少くとも一対
の側面、および絶縁基板の表裏面のうちの一方の
面と、相対する少くとも一対の側面とに連続した
導電体層を有し、その他の面が絶縁体で構成され
た、ほゞ直方体状の形状を有するチツプ状の導体
素子を容易にかつ安価に製造することのできる方
法を提供しようとするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a chip-shaped conductive element, in which the front and back surfaces of an insulating substrate, at least a pair of opposing side surfaces, and one of the front and back surfaces of the insulating substrate, and To easily and inexpensively manufacture a chip-shaped conductor element having a substantially rectangular parallelepiped shape, having a continuous conductor layer on at least one pair of side surfaces and an insulator on the other surface. The aim is to provide a method that allows for

近年、コンデンサーや抵抗体、半導体などの電
気回路素子において、小型リードレスタイプのチ
ツプ状の部品が開発され、これらのチツプ部品を
プリント基板の配線回路側(銅はく面)に装着し
てはんだづけする電子回路の組立て技術が普及し
て来ている。
In recent years, small leadless chip-shaped parts have been developed for electrical circuit elements such as capacitors, resistors, and semiconductors, and these chip parts are attached to the wiring circuit side (copper surface) of a printed circuit board and soldered. Electronic circuit assembly technology is becoming widespread.

しかしながら、これらのチツプ部品をプリント
基板に装着し、はんだづけする方法においては、
チツプ部品の占有面積が小さいため、多数個のチ
ツプ部品をプリント基板に装着するほど、必要な
配線回路を構成したプリント基板が小型化される
という利点があるが、その反面、配線回路のパタ
ーン設計が困難となり、必要な配線回路が多く取
れないために、チツプ部品をプリント基板に装着
し、はんだづけした後に新たにビニール被覆した
銅線からなるジヤンパー線を用いて、接続を必要
とする配線回路間をはんだづけするか、または、
スルーホールめつきした両面配線板を使用しなけ
ればならなかつた。
However, in the method of mounting and soldering these chip components on a printed circuit board,
Since the area occupied by chip components is small, the more chip components are mounted on a printed circuit board, the more compact the printed circuit board that makes up the necessary wiring circuits becomes. Because it is difficult to connect many wiring circuits, chip parts are mounted on a printed circuit board, soldered, and then jumper wires made of vinyl-coated copper wire are used to connect wiring circuits that require connection. solder or
A double-sided wiring board with through-hole plating had to be used.

しかしながら、前者の方法は、はんだづけに多
くの手間を要するばかりでなく誤配線しやすい欠
点があり、また、後者の方法は、プリント基板の
コストが高くつくという欠点があつた。
However, the former method not only requires a lot of time and effort for soldering but also has the drawback of being prone to wiring errors, and the latter method has the drawback of increasing the cost of the printed circuit board.

本発明は、上記のような従来例の欠点を完全に
除去し、コンデンサーや抵抗体などのチツプ部品
を多数個プリント基板に装着し、はんだづけした
場合に生ずる配線回路間の接続を効率よく行なう
ためのチツプ状導体素子の製造方法を提供するも
のである。
The present invention completely eliminates the above-mentioned drawbacks of the conventional example and efficiently connects wiring circuits that occur when a large number of chip components such as capacitors and resistors are mounted on a printed circuit board and soldered. The present invention provides a method for manufacturing a chip-shaped conductor element.

本発明の特徴とするところは、短冊状に加工し
た絶縁基板の表面と、相対する側面とに無電解め
つきに対する活性素地を附与してから、この短冊
状絶縁基板を無電解めつき液に浸漬して、活性素
地が形成された絶縁基板の表面および相対する側
面に導電体金属層を形成し、しかる後この短冊状
基板を小片状に切断加工して、直方体形状を有す
るチツプ部品とすることにある。
A feature of the present invention is that an active material for electroless plating is applied to the surface and opposing side surfaces of an insulating substrate processed into a strip shape, and then the strip-shaped insulating substrate is coated with an electroless plating solution. A conductive metal layer is formed on the surface and opposing sides of the insulating substrate on which the active material is formed, and then the strip-shaped substrate is cut into small pieces to produce chip parts having a rectangular parallelepiped shape. It is to do so.

この方法によれば、きわめて容易にプリント基
板の配線回路間の電気的接続を確実に行なうこと
のできるチツプ状導体素子を簡単にかつ安価に製
造することができるものである。
According to this method, it is possible to easily and inexpensively manufacture chip-shaped conductive elements that can extremely easily and reliably establish electrical connections between wiring circuits on a printed circuit board.

以下、本発明によるチツプ状導体素子の製造方
法を実施例にもとづいて詳細にのべる。
Hereinafter, the method for manufacturing a chip-shaped conductor element according to the present invention will be described in detail based on examples.

先ず第1図AおよびBに示すような、紙基材フ
エノール積層板や紙基材エポキシ積層板、さらに
はガラス基材エポキシ積層板などの合成樹脂板
や、セラミツクからなる絶縁基板1を第2図Aお
よびBに示すように所望のチツプ状導体素子の長
手方向の幅をもたせて短冊状に切断加工する。
First, as shown in FIGS. 1A and 1B, an insulating substrate 1 made of a synthetic resin board such as a paper-based phenol laminate, a paper-based epoxy laminate, a glass-based epoxy laminate, or a ceramic is placed on a second insulating substrate 1. As shown in Figures A and B, the chip-shaped conductive elements are cut into strips having the desired width in the longitudinal direction.

そしてこの短冊状絶縁基板1′を例えば塩化第
1錫の塩酸酸性溶液と塩化パラジウムの塩酸酸性
溶液から成る活性化処理液に順次浸漬することに
より活性化処理を行ない、第3図に示すように短
冊状絶縁基板1′の表裏面および相対する側面に
無電解めつきの触媒核となるパラジウムの微粒子
核を附着させ、活性素地2を形成する。
Then, activation treatment is performed by immersing this strip-shaped insulating substrate 1' in an activation treatment solution consisting of, for example, an acidic solution of stannous chloride in hydrochloric acid and an acidic solution of palladium chloride in hydrochloric acid, as shown in FIG. Palladium fine particle nuclei, which serve as catalyst nuclei for electroless plating, are attached to the front and back surfaces and opposing side surfaces of the strip-shaped insulating substrate 1' to form an active matrix 2.

次いで、第4図AおよびBに示すようにこの短
冊状絶縁基板1′を公知の無電解ニツケルめつき
液や無電解銅めつき液に浸漬して、活性素地2が
形成された絶縁基板の表裏面および相対する側面
にニツケルや銅からなる導体金属3を析出させ
る。そして必要により、電気めつきを行なつてニ
ツケルや銅などの金属層の厚みを補強し、さらに
その上に錫やはんだなどの金属をめつきして銅、
ニツケル金属層の腐食を防止し、はんだづけ性を
良くする。次にこの短冊状絶縁基板1′を第5図
に示すように所望のチツプ状導体素子の寸法に合
わせて小片状に切断加工することにより、直方体
形状を有するチツプ状部品4とする。
Next, as shown in FIGS. 4A and 4B, this strip-shaped insulating substrate 1' is immersed in a known electroless nickel plating solution or electroless copper plating solution to remove the insulating substrate on which the active substrate 2 has been formed. A conductive metal 3 made of nickel or copper is deposited on the front and back surfaces and opposing side surfaces. Then, if necessary, electroplating is performed to strengthen the thickness of the metal layer such as nickel or copper, and then metal such as tin or solder is plated on top of the layer of copper or copper.
Prevents corrosion of the nickel metal layer and improves solderability. Next, as shown in FIG. 5, this strip-shaped insulating substrate 1' is cut into small pieces according to the dimensions of a desired chip-shaped conductor element, thereby forming a chip-shaped component 4 having a rectangular parallelepiped shape.

なお、この方法において、絶縁基板1を短冊状
に切断加工するかわりに、第6図に示すように所
望のチツプ状導体素子の長手方向の幅をのこして
一定間隔の細長い貫通した溝5a,5b,5c,
5dをあけ、上述の方法により第7図に示すよう
にこの絶縁基板1の表裏面と貫通溝壁面に導電体
金属層3を形成し、しかる後にこの基板を短冊状
に切り離し、さらにこの短冊状基板を小片状に切
断加工することにより、第5図に示すようなチツ
プ状の部品としてもよい。
Note that in this method, instead of cutting the insulating substrate 1 into strips, as shown in FIG. ,5c,
5d, a conductive metal layer 3 is formed on the front and back surfaces of this insulating substrate 1 and the wall surface of the through groove by the method described above as shown in FIG. 7, and then this substrate is cut into strips. By cutting the substrate into small pieces, a chip-shaped component as shown in FIG. 5 may be obtained.

また、この方法において、絶縁基板1の表裏面
に接着剤を塗布し、接着剤層の表面を粗面化した
後上述の方法により導電金属層を形成することに
より、導電金属層と絶縁基板間の密着性にすぐれ
たチツプ状導体素子を作ることができる。
In addition, in this method, an adhesive is applied to the front and back surfaces of the insulating substrate 1, the surface of the adhesive layer is roughened, and then a conductive metal layer is formed by the above-mentioned method. Chip-shaped conductive elements with excellent adhesion can be made.

この目的に合致する接着剤としては、例えばニ
トリルゴムをフエノール樹脂やエポキシ樹脂で架
橋させたものがよく、この接着剤層をクロム酸―
硫酸系溶液や過マンガン酸カリウム溶液でエツチ
ングして相面化する。
A suitable adhesive for this purpose is, for example, nitrile rubber crosslinked with phenolic resin or epoxy resin, and this adhesive layer is
Etch with a sulfuric acid solution or potassium permanganate solution to form a phase.

以上のような実施例により得られたチツプ状導
体は、絶縁基板の表裏面と、相対する一対の側面
とに連続した導電金属層を有する構造のものが得
られるが、このような構造を有するチツプ状導体
素子をプリント基板の接続を使用する配線絶縁間
に装着したはんだづけする場合においては、接続
を必要とする配線回路間に他の独立した配線回路
が構成されていない場合にのみ使用される。
The chip-shaped conductor obtained in the above embodiments has a structure having a continuous conductive metal layer on the front and back surfaces of an insulating substrate and a pair of opposing side surfaces; When chip-shaped conductive elements are soldered between wiring insulation using printed circuit board connections, they are used only when no other independent wiring circuit is configured between the wiring circuits that require connection. .

一方、プリント基板の接続を必要とする配線回
路間に他の独立した配線回路が構成されている場
合には、絶縁基板の表裏面のうち一方の面が絶縁
体で構成され、他の面と、相対する一対の側面と
に連続した導電金属層が形成されたチツプ状導体
素子を使用しなければならない。
On the other hand, if another independent wiring circuit is configured between the wiring circuits that require connection of the printed circuit board, one of the front and back surfaces of the insulating board is made of an insulator, and the other side , a chip-shaped conductor element must be used in which a continuous conductive metal layer is formed on a pair of opposing side surfaces.

このような構造を有するチツプ状導体素子は第
8図に示すように、上述した合成樹脂やセラミツ
クからなる絶縁基板1の表裏面のうち一方の面に
耐酸性を有し、かつ稀アルカリ溶液や溶剤で簡単
に除去することのできるレジスト6を塗布し、こ
のレジスト6を乾燥させた後に第9図に示すよう
にこの絶縁基板1を短冊状に切断加工する。この
場合絶縁基板1は、上述した第6図に示したよう
な形に加工してもよいことはいうまでもない。
As shown in FIG. 8, a chip-shaped conductor element having such a structure has acid resistance on one of the front and back surfaces of the insulating substrate 1 made of the above-mentioned synthetic resin or ceramic, and is resistant to dilute alkaline solutions or A resist 6 that can be easily removed with a solvent is applied, and after drying the resist 6, the insulating substrate 1 is cut into strips as shown in FIG. In this case, it goes without saying that the insulating substrate 1 may be processed into the shape shown in FIG. 6 mentioned above.

次にこの短冊状絶縁基板1′を上述した塩化第
1錫の塩酸酸性溶液と塩化パラジウムの塩酸酸性
溶液から成る活性化処理液に順次浸漬することに
より活性化処理を行なつた後に、レジスト6を除
去し第10図に示すように、無電解めつきに対す
る活性素地2を絶縁基板の一方の面と、相対する
側面にのみ残留させる。
Next, the strip-shaped insulating substrate 1' is activated by being sequentially immersed in the above-mentioned activation treatment solution consisting of an acidic solution of stannous chloride in hydrochloric acid and an acidic solution of palladium chloride in hydrochloric acid. As shown in FIG. 10, the active material 2 for electroless plating remains only on one surface of the insulating substrate and the opposing side surface.

そしてこの短冊状基板1′を無電解めつき液に
浸漬して、第11図に示すように導電金属層3を
活性素地2の上に形成する。この場合、レジスト
6が塗布されていた短冊状基板1′の一方の面は
活性化処理がなされていないので導電金属層は形
成されない。しかる後にこの短冊状絶縁基板1′
を第12図に示すように小片状に切断加工してチ
ツプ部品4′とする。
The strip-shaped substrate 1' is then immersed in an electroless plating solution to form a conductive metal layer 3 on the active substrate 2, as shown in FIG. In this case, one surface of the strip-shaped substrate 1' on which the resist 6 was applied has not been subjected to activation treatment, so that no conductive metal layer is formed. After that, this strip-shaped insulating substrate 1'
is cut into small pieces as shown in FIG. 12 to form chip parts 4'.

この方法において、上述のように絶縁基板の表
面に接着剤を塗布し、接着剤層をエツチングして
粗面化した上に、導電金属層を形成することによ
り密着性のすぐれたチツプ状導体素子が得られる
ことはいうまでもない。
In this method, an adhesive is applied to the surface of an insulating substrate as described above, the adhesive layer is etched to roughen the surface, and a conductive metal layer is then formed to form a chip-shaped conductive element with excellent adhesion. Needless to say, you can obtain

以上の実施例により得られたチツプ状導体素子
はプリント基板の接続を必要とする配線回路間に
他の独立した配線回路の有無に関係なく、その導
体面を上向けにして装着し、はんだづけすること
により、配線回路間の接続を簡単に、しかも確実
に行なうことができる。
The chip-shaped conductor elements obtained in the above embodiments can be mounted and soldered with the conductor side facing upward, regardless of the presence or absence of other independent wiring circuits between the wiring circuits that require connection to the printed circuit board. This makes it possible to easily and reliably connect wiring circuits.

以上説明したように本発明により得られるチツ
プ状導体素子は、コンデンサーや抵抗体などの他
のチツプ部品とともに、プリント基板に装着はん
だづけすることができるので、従来のようにチツ
プ部品を取付けた後でジヤンパー線ではんだづけ
する方法に比べて、組立ての効率が顕著に向上す
る。さらに、この方法により得られるチツプ状導
体素子は、量産性にすぐれ、安価に製造できる利
点があり、またこのチツプ状導体素子を使用する
ことにより、コンデンサーや抵抗体、半導体など
のチツプ状回路素子を有効にかつ合理的に活用す
ることができるなどの大きな効果がある。
As explained above, the chip-shaped conductor element obtained by the present invention can be mounted and soldered to a printed circuit board together with other chip parts such as capacitors and resistors, so that it can be mounted and soldered on a printed circuit board after the chip parts have been attached as in the conventional method. Compared to the method of soldering with jumper wire, assembly efficiency is significantly improved. Furthermore, the chip-shaped conductor elements obtained by this method have the advantage of being highly mass-producible and can be manufactured at low cost.In addition, by using this chip-shaped conductor element, chip-shaped circuit elements such as capacitors, resistors, and semiconductors can be manufactured. It has great effects, such as being able to use it effectively and rationally.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A、第2図A、第3図、第4図A、第5
図、第6図、第7図は本発明の方法を示す斜視
図、第1図B、第2図B、第4図Bは側面図、第
8図〜第11図は同側面図、第12図は同斜視図
である。 1…絶縁基板、1′…短冊状絶縁基板、2…活
性素地、3…導電金属層、4,4′…チツプ部
品、5a,5b,5c,5d…貫通溝、6…耐酸
性レジスト。
Figure 1A, Figure 2A, Figure 3, Figure 4A, Figure 5
6 and 7 are perspective views showing the method of the present invention, FIGS. 1B, 2B, and 4B are side views, and FIGS. 8 to 11 are side views, and FIGS. FIG. 12 is a perspective view of the same. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 1'... Strip-shaped insulating substrate, 2... Active base material, 3... Conductive metal layer, 4, 4'... Chip parts, 5a, 5b, 5c, 5d... Penetration groove, 6... Acid-resistant resist.

Claims (1)

【特許請求の範囲】 1 短冊状絶縁基板の表裏面および両側面に無電
解めつきに対する活性を附与する工程、前記短冊
状絶縁基板に無電解めつき法により導電金属層を
形成する工程、前記短冊状絶縁基板を小片状に切
断加工する工程からなり、前記短冊状絶縁基板の
表裏面および両側面に連続した導電金属層を形成
することを特徴とするチツプ状導体素子の製造方
法。 2 短冊状絶縁基板の表裏面に接着剤を塗布し、
前記接着剤をあらかじめ粗面化することを特徴と
する特許請求の範囲第1項記載のチツプ状導体素
子の製造方法。 3 短冊状絶縁基板の表裏面のうち一方の面にレ
ジストを塗布する工程、前記短冊状絶縁基板の全
面に無電解めつきに対する活性化処理する工程、
前記短冊状絶縁基板から前記レジストを除去する
工程、前記短冊状絶縁基板の前記レジストを塗布
した面と反対側の面および両側面に無電解めつき
法により連続した導電金属層を形成する工程、前
記短冊状絶縁基板を小片状に切断加工する工程を
有するチツプ状導体素子の製造方法。 4 短冊状絶縁基板の表面に接着剤を塗布し、前
記接着剤層をあらかじめ粗面化することを特徴と
する特許請求の範囲第3項記載のチツプ状導体素
子の製造方法。
[Claims] 1. A step of imparting activity for electroless plating to the front and back surfaces and both side surfaces of a strip-shaped insulating substrate, a step of forming a conductive metal layer on the strip-shaped insulating substrate by an electroless plating method, A method for manufacturing a chip-shaped conductive element, comprising the step of cutting the strip-shaped insulating substrate into small pieces, and forming continuous conductive metal layers on the front and back surfaces and both side surfaces of the strip-shaped insulating substrate. 2 Apply adhesive to the front and back sides of the strip-shaped insulating board,
2. The method of manufacturing a chip-shaped conductive element according to claim 1, wherein the surface of the adhesive is roughened in advance. 3. A step of applying a resist to one of the front and back surfaces of the strip-shaped insulating substrate, a step of activating the entire surface of the strip-shaped insulating substrate for electroless plating,
a step of removing the resist from the strip-shaped insulating substrate; a step of forming a continuous conductive metal layer on a surface opposite to the resist-coated surface of the strip-shaped insulating substrate and both side surfaces by electroless plating; A method for manufacturing a chip-shaped conductive element, comprising the step of cutting the strip-shaped insulating substrate into small pieces. 4. The method for manufacturing a chip-shaped conductive element according to claim 3, characterized in that an adhesive is applied to the surface of the strip-shaped insulating substrate, and the surface of the adhesive layer is roughened in advance.
JP10242377A 1977-08-25 1977-08-25 Method of making tipptype conductive element Granted JPS5436566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10242377A JPS5436566A (en) 1977-08-25 1977-08-25 Method of making tipptype conductive element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10242377A JPS5436566A (en) 1977-08-25 1977-08-25 Method of making tipptype conductive element

Publications (2)

Publication Number Publication Date
JPS5436566A JPS5436566A (en) 1979-03-17
JPS6126171B2 true JPS6126171B2 (en) 1986-06-19

Family

ID=14327033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10242377A Granted JPS5436566A (en) 1977-08-25 1977-08-25 Method of making tipptype conductive element

Country Status (1)

Country Link
JP (1) JPS5436566A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57158873A (en) * 1981-03-27 1982-09-30 Dainippon Printing Co Ltd Hologram product
JPS5835579A (en) * 1981-08-28 1983-03-02 Toppan Printing Co Ltd Manufacture of reflection type hologram
JPS6183572A (en) * 1984-10-01 1986-04-28 Dainippon Printing Co Ltd Magnetic transfer sheet containing hologram
JP2001144394A (en) * 1999-11-17 2001-05-25 Mitsubishi Electric Corp High-frequency circuit

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JPS5436566A (en) 1979-03-17

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