JPS61260647A - Power semiconductor device - Google Patents

Power semiconductor device

Info

Publication number
JPS61260647A
JPS61260647A JP60102904A JP10290485A JPS61260647A JP S61260647 A JPS61260647 A JP S61260647A JP 60102904 A JP60102904 A JP 60102904A JP 10290485 A JP10290485 A JP 10290485A JP S61260647 A JPS61260647 A JP S61260647A
Authority
JP
Japan
Prior art keywords
tab
semiconductor element
power semiconductor
heat
insulating member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60102904A
Other languages
Japanese (ja)
Inventor
Yoshihiro Horie
堀江　義弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60102904A priority Critical patent/JPS61260647A/en
Publication of JPS61260647A publication Critical patent/JPS61260647A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To ensure excellent mounting and bonding by a method wherein the end of an outer lead is held in an insulating member positioned between a junction tab and a heat-radiating tab. CONSTITUTION:A power semiconductor element 1 is installed on the upper surface of a junction tab 2. On the lower surface of the junction tab 2, a heat- radiating tab 3 is placed with the intermediary on an insulating member 4. The end of an outer lead 6 is pushed into between the junction tab 2 and heat- radiating tab 3, where the end of the outer lead 6 is held in the insulating member 4, thus insulated from its environments. The outer lead 6 and an electrode of the power semiconductor element 1 is connected to a fine metal wire 5. Sealing with resin is accomplished for the power semiconductor element 1, while the lower surface of the heat-radiating tab 3 is left exposed for unimpeded radiation of heat. By using this technique, workability is improved during the processes of mounting and bonding, and the number is reduced of troubles attributable to short-circuiting.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電力用半導体素子を良好にマウント及びボンデ
ィングが行えるようにした多数外部リードを有する電力
用半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power semiconductor device having a large number of external leads, which allows power semiconductor elements to be mounted and bonded well.

〔従来の技術〕[Conventional technology]

第２図の平向図に示す従来の電力用半導体装置において
、外部リードのうちのタブ用リード６ａと放熱用タブ７
との接続方法として、タブ用り−ド６ａの先端部と放熱
用タブ７とのカシメ構造、または、高融点半田による溶
融法が使用されているＯ 〔発明が解決しようとする問題点〕 最近の電力用半導体素子は高機能化と高集積化の要請に
より、外部リード本数が増大する傾向にある。このため
、外部リードのリード幅と厚みが小さく、かつリード間
隔が狭くなシ、外部リードの取扱いが悪いとリード先端
が曲シやすく、第２図に示す半導体素子１の電極から、
金属細線５を外部リード６に接続する場合、外部リード
６の所定の位置からすれるため、金属細線が垂れて、他
の外部リード又は半導体素子とショートしたシ、外部か
らの力により金属細線が切れるという欠点がある。また
、タフ用リード６ａが放熱用タブ７とカシメまたは高融
点半田によ多接続されているため、カシメの角度不具合
また峰マウント時の半田溶融により、外部リード６と放
熱用タブ７との相対位置がズしたり、平行度に狂いが生
じるという欠点がある。In the conventional power semiconductor device shown in the plan view of FIG. 2, a tab lead 6a and a heat radiation tab 7 of the external leads
As a connection method, a caulking structure between the tip of the tab door 6a and the heat dissipation tab 7, or a melting method using high melting point solder is used. [Problems to be Solved by the Invention] Recently Due to the demand for higher functionality and higher integration in power semiconductor devices, the number of external leads tends to increase. For this reason, if the lead width and thickness of the external lead are small and the lead spacing is narrow, the lead tip is likely to bend if the external lead is handled improperly, and from the electrode of the semiconductor element 1 shown in FIG.
When connecting the thin metal wire 5 to the external lead 6, the thin metal wire may sag from a predetermined position on the external lead 6, resulting in a short circuit with other external leads or the semiconductor element, or the thin metal wire may be damaged by external force. It has the disadvantage of being cut. In addition, since the tough lead 6a is connected to the heat dissipation tab 7 by caulking or high-melting point solder, the relative relationship between the external lead 6 and the heat dissipation tab 7 may be caused by a problem with the caulking angle or melting of the solder when mounting the peak. The disadvantage is that the position may shift or the parallelism may be inconsistent.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

上記問題点に対し、本発明では、下面が封止樹脂体から
無比されて外部装置への取付面と−ａｂ、搭載した電力
用半導体素子の発生熱を速かに外部に放散する従来の放
熱用タブに対し、本発明の放熱用タブには半導体素子を
搭載せず、その代わシ、放熱用タブの上に、半導体素子
を搭載した接続用タブを絶縁部材を介して重ね、接続用
タブと放熱用タブの間に、前記絶縁部材で絶縁した状態
で外部リードの先端部をは≧み保持し、この外部リード
と前記半導体素子の電極との間を金属細線で接続後、放
熱用タブの下面を無比させて樹脂封止をしている。In order to solve the above problems, the present invention has a lower surface that is separated from the sealing resin body and serves as a mounting surface for an external device. In contrast to the heat dissipation tab of the present invention, a semiconductor element is not mounted on the heat dissipation tab of the present invention. Instead, a connection tab equipped with a semiconductor element is stacked on top of the heat dissipation tab with an insulating member interposed therebetween. The tip of the external lead is held between the heat dissipation tab and the heat dissipation tab while being insulated with the insulating member, and after connecting the external lead and the electrode of the semiconductor element with a thin metal wire, the heat dissipation tab is inserted. The bottom surface is sealed with resin.

〔実施例〕〔Example〕

つき゛に本発明を実施例により説明する。 The present invention will now be explained by way of examples.

第１図１ａ）は本発明の一実施例の封止樹脂を省略した
平面図、同図（ｂｌは断面図である。これらの図におい
て、接続用タブ２の上面に半導体素子１がマウントされ
、接続用タブ２の］面には絶縁部材４を間にして放熱用
タブ３が１ねられ、かつ、接続用タブ２と放熱用タブ３
０間には、外部リード６の先端部が押し込まれ、絶縁部
材４により絶縁状態で保持されている。そして、外部リ
ード６と半導体素子１の電極の間は金属細線５でもって
接続後、図示してない樹脂により、放熱用タブ３の下面
を無比させて、電力用半導体素子１の発熱の放散を阻害
しないように樹脂封止されている。1a) is a plan view of an embodiment of the present invention with the sealing resin omitted, and the same figure (bl is a sectional view). In these figures, the semiconductor element 1 is mounted on the upper surface of the connection tab 2. , one heat dissipation tab 3 is laid on the surface of the connection tab 2 with an insulating member 4 in between, and the connection tab 2 and the heat dissipation tab 3 are
The tip of the external lead 6 is pushed into the space between the two ends, and is held in an insulated state by the insulating member 4. After connecting the external lead 6 and the electrode of the semiconductor element 1 with the thin metal wire 5, the lower surface of the heat dissipation tab 3 is made unique with resin (not shown) to dissipate the heat generated by the power semiconductor element 1. It is sealed with resin to prevent interference.

〔発明の効果〕〔Effect of the invention〕

上述のとおシ本発明は、外部リード先端部が接続用タブ
及び放熱用タブの間にはさまれている人め、外部リード
の位置ずれ及び曲りの不具合発生が防止され、マウント
及びボンディングの作業性の改善とショート不良低減を
計ることができる。In addition to the above, the present invention prevents problems such as misalignment and bending of the external lead when the tip of the external lead is sandwiched between the connection tab and the heat dissipation tab, and facilitates mounting and bonding work. It is possible to improve performance and reduce short-circuit defects.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）は本発明の一実施例の封止樹脂を省略した
平面図、同図（ｂ）は断面図、第２図は従来の電力用半
導体装置の封止樹脂を省略した平面図である。 １・・・・・・半導体素子、２・・・・・・接続用タブ
、３．７・・・・・・放熱用タブ、５・・・・・・金属
細線、６・・・・・・外部リード、６ｍ・・・・・・タ
ブ用リード。 ］ロロロロロロロロ 第７図 第Ｚ図FIG. 1(a) is a plan view of an embodiment of the present invention with the sealing resin omitted, FIG. 1(b) is a cross-sectional view, and FIG. 2 is a plan view of a conventional power semiconductor device with the sealing resin omitted. It is a diagram. 1... Semiconductor element, 2... Connection tab, 3.7... Heat dissipation tab, 5... Thin metal wire, 6...・External lead, 6m...Lead for tab. ] Rorororororororo Figure 7 Figure Z

Claims (1)

【特許請求の範囲】[Claims] 半導体素子が搭載された接続用タブと、この接続用タブ
の下面に絶縁部材を介して重ねられた放熱用タブと、前
記接続用タブと放熱用タブとの間に前記絶縁部材により
絶縁状態で先端部が挿入保持された外部リードと、前記
半導体素子の電極と外部リードの間を接続する金属細線
と、前記半導体素子を包覆する封止樹脂体とからなる電
力用半導体装置。A connection tab on which a semiconductor element is mounted, a heat dissipation tab stacked on the bottom surface of the connection tab with an insulating member interposed therebetween, and an insulated state between the connection tab and the heat dissipation tab by the insulating member. A power semiconductor device comprising an external lead whose tip is inserted and held, a thin metal wire connecting between the electrode of the semiconductor element and the external lead, and a sealing resin body covering the semiconductor element.
JP60102904A 1985-05-15 1985-05-15 Power semiconductor device Pending JPS61260647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60102904A JPS61260647A (en) 1985-05-15 1985-05-15 Power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60102904A JPS61260647A (en) 1985-05-15 1985-05-15 Power semiconductor device

Publications (1)

Publication Number Publication Date
JPS61260647A true JPS61260647A (en) 1986-11-18

Family

ID=14339843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60102904A Pending JPS61260647A (en) 1985-05-15 1985-05-15 Power semiconductor device

Country Status (1)

Country Link
JP (1) JPS61260647A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248774A (en) * 2011-05-31 2012-12-13 Denso Corp Semiconductor device and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248774A (en) * 2011-05-31 2012-12-13 Denso Corp Semiconductor device and manufacturing method therefor

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