JPH0447963Y2 - - Google Patents
Info
- Publication number
- JPH0447963Y2 JPH0447963Y2 JP1983124726U JP12472683U JPH0447963Y2 JP H0447963 Y2 JPH0447963 Y2 JP H0447963Y2 JP 1983124726 U JP1983124726 U JP 1983124726U JP 12472683 U JP12472683 U JP 12472683U JP H0447963 Y2 JPH0447963 Y2 JP H0447963Y2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- substrate
- conductive substrate
- semiconductor
- shaped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
Landscapes
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
〔考案の属する技術分野〕
本考案は半導体基体の一面を導電性基板上に導
電的に固着し、その半導体基体の上面の電極と導
線によつて接続された少なくとも二つの端子と基
板に導電的に固着された一つの端子を基板面に対
して垂直方向に引き出す半導体装置に関する。[Detailed description of the invention] [Technical field to which the invention pertains] The invention involves fixing one surface of a semiconductor substrate to a conductive substrate in a conductive manner, and connecting at least two electrodes to an electrode on the upper surface of the semiconductor substrate by a conductive wire. The present invention relates to a semiconductor device in which two terminals and one terminal conductively fixed to a substrate are pulled out in a direction perpendicular to the substrate surface.
端子を有する半導体素子、例えばトランジスタ
をパツケージに収容するために第1図に示すよう
な構造をとることが行なわれている。すなわち、
トランジスタチツプ1を放熱板を兼ねる金属基板
2にろう付けし、チツプ1の上面のベース電極を
基板2にセラミツク板3を介して固定されたベー
ス端子4の上面とアルミニウム線5のボンデイン
グによつて接続する。またエミツタ電極は同様に
基板2にセラミツク板3を介して固定されたエミ
ツタ端子6の上面とA1線5のボンデイングによ
つて接続されている。一方コレクタは基板2に接
続されているので、コレクタ端子7はチツプ1の
あいている側方において基板2にろう付けされ、
ベース端子4、エミツタ端子6と共に直角に折り
曲げられ、図示しないがチツプ1を保護する封止
用樹脂より端部が露出して、外部回路との接続に
利用される。この場合コレクタ端子7の基板2と
の接着部は、接着強度の確保のため、ある程度の
長さlを必要とし、基板2はその分だけ長くしな
ければならず、半導体装置の占有面積がそれだけ
大きくなる。
2. Description of the Related Art In order to accommodate a semiconductor element having terminals, such as a transistor, in a package, a structure as shown in FIG. 1 is used. That is,
A transistor chip 1 is brazed to a metal substrate 2 which also serves as a heat sink, and a base electrode on the top surface of the chip 1 is bonded to the top surface of a base terminal 4 fixed to the substrate 2 via a ceramic plate 3 with an aluminum wire 5. Connecting. Further, the emitter electrode is similarly connected to the upper surface of an emitter terminal 6 fixed to the substrate 2 via the ceramic plate 3 by bonding with an A1 wire 5. On the other hand, since the collector is connected to the substrate 2, the collector terminal 7 is brazed to the substrate 2 on the open side of the chip 1.
It is bent at right angles together with the base terminal 4 and the emitter terminal 6, and the end portion is exposed from the sealing resin that protects the chip 1 (not shown) and is used for connection with an external circuit. In this case, the adhesive part between the collector terminal 7 and the substrate 2 requires a certain length l in order to ensure adhesive strength, and the substrate 2 must be lengthened by that amount, which increases the area occupied by the semiconductor device. growing.
本考案はこのような半導体装置の占有面積を小
さくする構造を提供することを目的とする。
An object of the present invention is to provide a structure that reduces the area occupied by such a semiconductor device.
〔考案の要点〕
本考案はこの目的を達成するために端子を立体
構造化したもので、半導体基体の一面が放熱板を
兼ねる導電性基板上に導電的に固着され、該半導
体基体の上面の電極と導線によつて接続されかつ
導電性基板とは絶縁された少なくとも二つの第
一、第三のL字状端子と、導電性基板に導電的に
固着される第二のL字状端子とがそれぞれL字状
の一端が前記導電性基板上に載置され、L字状の
他端が該導電性基板の基板面に対して垂直方向に
引き出されるものにおいて、導電性基板の一方向
の長さと等しい第二と第三の端子の一端が該導電
性基板上で半導体基体をはさんで平行に対向して
位置し、半導体基体の上面の電極と接続され一端
が第二の端子の一端より短い第一の端子が第二の
端子の上に絶縁物を介して積み重ねられ、かつ第
一の端子と第二の端子はそれらの一端の長手方向
の異なる端において他端が引き出され、前記絶縁
物が第一の端子の引き出される他端とは反対側の
一端の先端で露出していることを特徴とする。[Key points of the invention] In order to achieve this purpose, the present invention has a three-dimensional terminal structure, in which one surface of a semiconductor substrate is conductively fixed to a conductive substrate that also serves as a heat sink, and the top surface of the semiconductor substrate is At least two first and third L-shaped terminals connected to the electrode by a conductive wire and insulated from the conductive substrate; and a second L-shaped terminal conductively fixed to the conductive substrate. in which one L-shaped end is placed on the conductive substrate and the other L-shaped end is pulled out in a direction perpendicular to the substrate surface of the conductive substrate; One ends of second and third terminals having the same length are located parallel to each other on the conductive substrate with the semiconductor substrate in between, and are connected to an electrode on the upper surface of the semiconductor substrate, one end of which is one end of the second terminal. A shorter first terminal is stacked on top of a second terminal with an insulator interposed therebetween, and the first terminal and the second terminal have their other ends pulled out at different longitudinal ends of the first terminal and the second terminal. The insulator is characterized in that the insulator is exposed at the tip of one end opposite to the other end from which the first terminal is pulled out.
第2図に示す実施例においては、第1図と共通
の部分には同一の符号が付されている。第2図に
おいて、コレクタ端子7はベース端子4とチツプ
1を挟んで対向する基板2の縁部にろう付けされ
ている。エミツタ端子6はこのコレクタ端子7の
上に絶縁セラミツク板3を介して積層されてい
る。その場合絶縁板3の一方の端を若干露出させ
ておくことで沿面距離の増大が図れる。各端子
4,6,7の端部は第1図と同様に直角に曲げら
れて立上つているが、コレクタ端子の立上り部7
1はエミツタ端子6の立上り部61と反対側に設
けられている。第2図ではこの立上り部71はコ
レクタ端子7の長手方向に見た側方に設けられる
が、第3図の側面図が示すように長手方向の端に
エミツタ端子の立上り部61と対向するように形
成してもよい。いずれの場合もエミツタ端子6と
エミツタ電極との間のA1線5による接続は、従
来と全く同じ装置、方法によつて可能である。
In the embodiment shown in FIG. 2, parts common to those in FIG. 1 are given the same reference numerals. In FIG. 2, the collector terminal 7 is brazed to the edge of the substrate 2, which faces the base terminal 4 with the chip 1 in between. The emitter terminal 6 is laminated on the collector terminal 7 with an insulating ceramic plate 3 interposed therebetween. In this case, by leaving one end of the insulating plate 3 slightly exposed, the creepage distance can be increased. The ends of each terminal 4, 6, and 7 are bent at right angles and stand up as in FIG. 1, but the rising part 7 of the collector terminal
1 is provided on the side opposite to the rising portion 61 of the emitter terminal 6. In FIG. 2, this rising portion 71 is provided on the side of the collector terminal 7 when viewed in the longitudinal direction, but as shown in the side view of FIG. It may be formed into In either case, the connection between the emitter terminal 6 and the emitter electrode via the A1 wire 5 can be made using the same equipment and method as in the prior art.
このように構成することにより、基板2の一方
の長さは半導体チツプ1の長さより若干大きいだ
けでよく、第1図の場合にくらべてl寸法の分だ
け短くできる。 With this configuration, the length of one side of the substrate 2 only needs to be slightly larger than the length of the semiconductor chip 1, and can be made shorter by the l dimension than in the case of FIG.
本考案は半導体基体の上面の電極と接続される
端子を基板に直接接続される端子の上に絶縁して
積み重ねることによつて半導体装置の半導体基体
支持基板の大きさ、すなわち半導体装置の占有面
積を小さくすることができるため、電子装置の小
形化に対して極めて大きな効果をもたらすもので
ある。本考案はサイリスタなどの他の3端子の半
導体装置、あるいはダーリントン接続トランジス
タなどの4端子半導体装置にも同様に有効に適用
できる。
This invention reduces the size of the semiconductor substrate supporting substrate of a semiconductor device, that is, the area occupied by the semiconductor device, by insulating and stacking the terminals connected to the electrodes on the top surface of the semiconductor substrate on top of the terminals directly connected to the substrate. This has an extremely large effect on the miniaturization of electronic devices. The present invention can be similarly effectively applied to other three-terminal semiconductor devices such as thyristors, or four-terminal semiconductor devices such as Darlington connected transistors.
第1図は従来のパワートランジスタの一例のパ
ツケージ前の斜視図、第2図は本考案の一実施例
のパツケージ前の斜視図、第3図は別の実施例の
基板部の側面図である。
1……半導体チツプ、2……金属基板、3……
セラミツク板、4……ベース端子、5……アルミ
ニウム線、6……エミツタ端子、7……コレクタ
端子、61,71……端子立上り部。
Fig. 1 is a perspective view of the front of the package of an example of a conventional power transistor, Fig. 2 is a perspective view of the front of the package of one embodiment of the present invention, and Fig. 3 is a side view of the substrate section of another embodiment. . 1... Semiconductor chip, 2... Metal substrate, 3...
Ceramic board, 4... Base terminal, 5... Aluminum wire, 6... Emitter terminal, 7... Collector terminal, 61, 71... Terminal rising portion.
Claims (1)
上に導電的に固着され、該半導体基体の上面の電
極と導線によつて接続されかつ導電性基板とは絶
縁された少なくとも二つの第一、第三のL字状端
子と、導電性基板に導電的に固着される第二のL
字状端子とがそれぞれL字状の一端が前記導電性
基板上に載置され、L字状の他端が該導電性基板
の基板面に対して垂直方向に引き出されるものに
おいて、導電性基板の一方向の長さと等しい第二
と第三の端子の一端が該導電性基板上で半導体基
体をはさんで平行に対向して位置し、半導体基体
の上面の電極と接続され一端が第二の端子の一端
より短い第一の端子が第二の端子の上に絶縁物を
介して積み重ねられ、かつ第一の端子と第二の端
子はそれらの一端の長手方向の異なる端において
他端が引き出され、前記絶縁物が第一の端子の引
き出される他端とは反対側の一端の先端で露出し
ていることを特徴とする半導体装置。 One surface of the semiconductor substrate is electrically conductively fixed on a conductive substrate that also serves as a heat sink, and at least two first and second three L-shaped terminals, and a second L-shaped terminal conductively fixed to the conductive substrate.
Each of the L-shaped terminals has one L-shaped end placed on the conductive substrate and the other L-shaped end pulled out in a direction perpendicular to the substrate surface of the conductive substrate, wherein the conductive substrate One ends of the second and third terminals, which are equal in length in one direction, are located parallel to each other on the conductive substrate with the semiconductor substrate in between, and are connected to the electrode on the upper surface of the semiconductor substrate. A first terminal, which is shorter than one end of the terminal of A semiconductor device that is pulled out, and the insulator is exposed at the tip of one end of the first terminal opposite to the other end that is pulled out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983124726U JPS6033441U (en) | 1983-08-11 | 1983-08-11 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983124726U JPS6033441U (en) | 1983-08-11 | 1983-08-11 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6033441U JPS6033441U (en) | 1985-03-07 |
| JPH0447963Y2 true JPH0447963Y2 (en) | 1992-11-12 |
Family
ID=30284217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983124726U Granted JPS6033441U (en) | 1983-08-11 | 1983-08-11 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6033441U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001308265A (en) * | 2000-04-21 | 2001-11-02 | Toyota Industries Corp | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57111054A (en) * | 1980-12-27 | 1982-07-10 | Toshiba Corp | Semiconductor device |
| JPS5893361A (en) * | 1981-11-30 | 1983-06-03 | Mitsubishi Electric Corp | semiconductor equipment |
-
1983
- 1983-08-11 JP JP1983124726U patent/JPS6033441U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6033441U (en) | 1985-03-07 |
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