JPH0451476Y2 - - Google Patents

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Publication number
JPH0451476Y2
JPH0451476Y2 JP1988111185U JP11118588U JPH0451476Y2 JP H0451476 Y2 JPH0451476 Y2 JP H0451476Y2 JP 1988111185 U JP1988111185 U JP 1988111185U JP 11118588 U JP11118588 U JP 11118588U JP H0451476 Y2 JPH0451476 Y2 JP H0451476Y2
Authority
JP
Japan
Prior art keywords
support plate
edge
semiconductor chip
terminal member
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1988111185U
Other languages
Japanese (ja)
Other versions
JPH0233433U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988111185U priority Critical patent/JPH0451476Y2/ja
Publication of JPH0233433U publication Critical patent/JPH0233433U/ja
Application granted granted Critical
Publication of JPH0451476Y2 publication Critical patent/JPH0451476Y2/ja
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4945—Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 産業上の利用分野 本考案は半導体装置に関し、詳細には半導体チ
ツプと外部リードとが複数本のリード細線によつ
て電気的に接続されている半導体装置に関する。[Detailed Description of the Invention] Industrial Application Field The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a semiconductor chip and an external lead are electrically connected by a plurality of thin lead wires.

従来の技術 第２図は従来の電力用半導体装置の平面図であ
る。図示のように支持板１の上面に半導体チツプ
２が半田（図示せず）を介して固着されている。
半導体チツプ２上に形成された電極（図示せず）
は支持板１の一方の端部側に配置された外部リー
ド３にリード細線４を介して電気的に接続されて
いる。Prior Art FIG. 2 is a plan view of a conventional power semiconductor device. As shown in the figure, a semiconductor chip 2 is fixed to the upper surface of a support plate 1 via solder (not shown).
Electrodes formed on semiconductor chip 2 (not shown)
is electrically connected to an external lead 3 disposed on one end side of the support plate 1 via a thin lead wire 4 .

考案が解決しようとする課題 ところで、今日、半導体装置の高密度実装化に
伴い電力用半導体装置に使用される半導体チツプ
２にも多数の電極が形成され、外部リード３及び
リード細線４の数が増加する傾向にある。したが
つて、リード細線４が互いに近接して配線された
り、リード細線４の接続距離が増大している。こ
のため、複数のリード細線４が互いに接触した
り、リード細線４が半導体チツプ２又は支持板１
に接触して、電気的短絡事故を起こすことがあつ
た。そこで、支持板１の前後及び左右の端部側に
も外部リード３を設けたリードフレームが提案さ
れている。このリードフレームによれば半導体チ
ツプ３からのリード細線４の引出し方向の自由度
が向上するためリード細線４の接触による短絡事
故の問題を解決できる。しかし、この構造のリー
ドフレームでは帯状の金属板をプレス加工して作
成する関係上支持板１を外部リード３よりも相対
的に肉厚に形成することが困難であるから、高い
放熱性の必要な電力用半導体装置には実用化を計
ることができなかつた。Problems to be Solved by the Invention Nowadays, as semiconductor devices become more densely packaged, a large number of electrodes are formed on semiconductor chips 2 used in power semiconductor devices, and the number of external leads 3 and thin lead wires 4 increases. There is a tendency to increase. Therefore, the thin lead wires 4 are wired close to each other, and the connection distance of the thin lead wires 4 is increased. Therefore, the plurality of thin lead wires 4 may come into contact with each other, or the thin lead wires 4 may touch the semiconductor chip 2 or the support plate 1.
could cause an electrical short circuit. Therefore, a lead frame has been proposed in which external leads 3 are provided also on the front and rear, left and right end sides of the support plate 1. According to this lead frame, the degree of freedom in the drawing direction of the thin lead wires 4 from the semiconductor chip 3 is improved, so that the problem of short circuits caused by contact of the thin lead wires 4 can be solved. However, in a lead frame with this structure, it is difficult to form the support plate 1 relatively thicker than the external leads 3 because it is created by pressing a band-shaped metal plate, so high heat dissipation is required. It was not possible to put this into practical use as a power semiconductor device.

そこで、本考案は放熱性の高い支持板を有し、
かつ短絡事故を発生することなく半導体チツプと
多数の外部リードとを多数のリード細線によつて
接続した半導体装置を提供することを目的とす
る。 Therefore, the present invention has a support plate with high heat dissipation,
Another object of the present invention is to provide a semiconductor device in which a semiconductor chip and a large number of external leads are connected by a large number of thin lead wires without causing a short circuit accident.

課題を解決するための手段 本考案による半導体装置は、支持板と、支持板
の主面に固着された半導体チツプと、半導体チツ
プ上に形成された電極に電気的に接続された複数
の外部リードとを有する。外部リードは支持板の
第一の縁部の側方のみにおいて又は支持板の第一
の縁部とそれに対向する第二の縁部の側方のみに
おいて支持板の前記第一及び第二の縁部に沿つて
並置されている。支持板の第一の縁部と第二の縁
部との間に形成された第三の縁部と第四の縁部の
側方には外部リードが配置されていない。支持板
の平均的な肉厚は外部リードの平均的肉厚よりも
大きい。支持板の主面には半導体チツプから離間
して端子部材が固着される。半導体チツプ上の電
極と端子部材上に形成された電極体は第一のリー
ド細線によつて電気的に接続される。端子部材上
の電極体と外部リードは第二のリード細線によつ
て電気的に接続されることにより、半導体チツプ
上の電極と、外部リードとが電気的に接続されて
いる。半導体チツプは支持板の第一の縁部側に形
成された第一の端部と、支持板の第二の縁部側に
形成された第二の端部と、支持板の第三の縁部側
形成された第三の端部と、支持板の第四の縁部側
に形成された第四の端部とを有する。端子部材上
の電極体と第一のリード細線との接続部分は半導
体チツプの第一の端部の延長線と第二の端部の延
長線との間に位置している。端子部材上の電極体
と第二のリード細線との接続部分は半導体チツプ
の第三の端部又は第三の端部の延長線と支持板の
第三の縁部との間又は半導体チツプの第四の端部
又は第四の端部の延長線と支持板の第四の縁部と
の間に位置している。Means for Solving the Problems A semiconductor device according to the present invention includes a support plate, a semiconductor chip fixed to the main surface of the support plate, and a plurality of external leads electrically connected to electrodes formed on the semiconductor chip. and has. The external lead is connected to the first and second edges of the support plate only on the sides of the first edge of the support plate or only on the sides of the first edge and the second edge opposite thereto. They are arranged side by side along the section. No external leads are arranged on the sides of the third edge and fourth edge formed between the first edge and second edge of the support plate. The average thickness of the support plate is greater than the average thickness of the external leads. A terminal member is fixed to the main surface of the support plate at a distance from the semiconductor chip. The electrode on the semiconductor chip and the electrode body formed on the terminal member are electrically connected by a first thin lead wire. The electrode body on the terminal member and the external lead are electrically connected by the second thin lead wire, so that the electrode on the semiconductor chip and the external lead are electrically connected. The semiconductor chip has a first end formed on the first edge side of the support plate, a second end formed on the second edge side of the support plate, and a third edge of the support plate. It has a third end formed on the side of the support plate, and a fourth end formed on the fourth edge side of the support plate. The connecting portion between the electrode body on the terminal member and the first thin lead wire is located between the extended line of the first end and the extended line of the second end of the semiconductor chip. The connection portion between the electrode body on the terminal member and the second thin lead wire is located between the third end of the semiconductor chip or an extension of the third end and the third edge of the support plate, or between the third end of the semiconductor chip or an extension of the third end and the third edge of the support plate. It is located between the fourth end or an extension of the fourth end and the fourth edge of the support plate.

作 用 本考案による半導体装置では支持板の第一の縁
部の側方のみにおいて又は第一の縁部とそれに対
向する第二の縁部の側方のみにおいて外部リード
が配置されている。したがつて、外部リードより
大きい肉厚の支持板を形成して、支持板の放熱性
を増加することができる。Function In the semiconductor device according to the present invention, external leads are arranged only on the sides of the first edge of the support plate, or only on the sides of the first edge and the second edge opposite thereto. Therefore, by forming the support plate with a thickness greater than that of the external leads, the heat dissipation of the support plate can be increased.

また、半導体チツプ上の電極に接続された第一
のリード細線と端子部材上に形成された電極体と
の接続部分が半導体チツプの第一の端部の延長線
と第二の端部の延長線との間に位置する。したが
つて、第一のリード細線を半導体チツプ上の電極
から支持板の第三の縁部もしくは第四の縁部に向
かつて引出して配線できる。また、外部リードに
接続された第二のリード細線と端子部材上に形成
された電極体との接続部分が半導体チツプの第三
の端部とまたはその延長線と支持板の第三の縁部
との間もしくは半導体チツプの第四の端部とまた
はその延長線と支持板の第四の縁部との間に位置
する。したがつて、第二のリード細線を端子部材
上の電極から外部リードのうち半導体チツプの第
三の端部及び第四の端部よりも外側に配置された
外部リードにも良好に配線できる。 In addition, the connecting portion between the first thin lead wire connected to the electrode on the semiconductor chip and the electrode body formed on the terminal member is an extension of the first end of the semiconductor chip and an extension of the second end of the semiconductor chip. located between the lines. Therefore, the first thin lead wire can be drawn out and wired from the electrode on the semiconductor chip toward the third edge or fourth edge of the support plate. Further, the connecting portion between the second thin lead wire connected to the external lead and the electrode body formed on the terminal member is connected to the third end of the semiconductor chip or its extension line and the third edge of the support plate. or between the fourth end of the semiconductor chip or an extension thereof and the fourth edge of the support plate. Therefore, the second thin lead wire can be well wired from the electrode on the terminal member to the external leads disposed outside the third and fourth ends of the semiconductor chip.

実施例 以下、本考案を電力用半導体装置に応用した実
施例について説明する。第１図は本考案の一実施
例に係わる電力用半導体装置の斜視図を示す。こ
の電力用半導体装置は支持板１１と、支持板１１
に隣接して配置された外部リード１２〜１６と、
支持板１１の主面１１ａに固着された半導体チツ
プ１７と、第１の端子部材１８及び第２の端子部
材１９と、リード細線２０〜３１とを有する。半
導体チツプ１７は、パワートランジスタとその制
御回路がワンチツプ化されたパワーICチツプで
ある。支持板１１と外部リード１２〜１６は、圧
延加工によつて肉厚部分と肉薄部分とがそれぞれ
長手方向に延在するように形成された一枚の帯状
銅材を周知のプレス加工によつて打ち抜いて形成
される。支持板１１は第一の縁部１１ｂと、第一
の縁部１１ｂに対向する第二の縁部１１ｃと、第
一の縁部１１ｂと第二の縁部１１ｃの間に形成さ
れた第三及び第四の縁部１１ｄ，１１ｅとを有す
る。Embodiment Hereinafter, an embodiment in which the present invention is applied to a power semiconductor device will be described. FIG. 1 shows a perspective view of a power semiconductor device according to an embodiment of the present invention. This power semiconductor device includes a support plate 11 and a support plate 11.
external leads 12 to 16 arranged adjacent to;
It has a semiconductor chip 17 fixed to the main surface 11a of the support plate 11, a first terminal member 18, a second terminal member 19, and thin lead wires 20-31. The semiconductor chip 17 is a power IC chip in which a power transistor and its control circuit are integrated into one chip. The support plate 11 and the external leads 12 to 16 are made by using a well-known press process to form a strip of copper material, which is formed by rolling so that the thick part and the thin part extend in the longitudinal direction. Formed by punching. The support plate 11 has a first edge 11b, a second edge 11c opposite the first edge 11b, and a third edge 11c formed between the first edge 11b and the second edge 11c. and fourth edges 11d and 11e.

支持板１１は外部リード１２〜１６に比べて肉
厚に形成されている。即ち支持板１１の平均的な
肉厚l1は外部リード１２〜１６の平均的肉厚l2よ
りも大きい。支持板１１の主要部（放熱板として
主に機能する部分）は肉厚に形成されており、支
持板１１の第一の縁部１１ｂ側と第二の縁部１１
ｃ側は部分的に肉薄となつている。 The support plate 11 is formed thicker than the external leads 12-16. That is, the average wall thickness l 1 of the support plate 11 is larger than the average wall thickness l 2 of the external leads 12 to 16. The main part of the support plate 11 (the part that mainly functions as a heat sink) is formed thick, and the first edge 11b side and the second edge 11 of the support plate 11 are thick.
The c side is partially thin.

各外部リード１２〜１６は支持板１１の第一の
縁部１１ｂ側から縦方向に導出されかつ支持板１
１の第一の縁部１１ｂに沿つて横方向に並行して
配置されている。支持板１１の第二の縁部１１ｃ
側及び第三及び第四の縁部１１ｄ，１１ｅ側には
外部リードが配置されていない。半導体チツプ１
７は支持板１１上に半田（図示せず）によつて直
接的に固着されている。半導体チツプ１７の上面
には複数の電極３２ａ〜３２ｈが形成されてい
る。本実施例では支持板１１の第一の縁部１１ｂ
に沿つて半導体チツプ１７の両側に第１及び第２
の端子部材１８，１９が配置されている。半導体
チツプ１７は支持板１１の第一の縁部１１ｂ側に
第一の端部１７ａ、支持板１１の第二の縁部１１
ｃ側に第二の端部１７ｂ、支持板１１の第三の縁
部１１ｄ側に第三の端部１７ｃ、支持板１１の第
四の縁部１１ｅ側に第四の端部１７ｄを有する。 Each of the external leads 12 to 16 is led out in the vertical direction from the first edge 11b side of the support plate 11, and
1 are arranged in parallel in the lateral direction along the first edge 11b of 1. Second edge 11c of support plate 11
No external leads are arranged on the side and the third and fourth edge portions 11d and 11e. semiconductor chip 1
7 is directly fixed onto the support plate 11 with solder (not shown). A plurality of electrodes 32a to 32h are formed on the upper surface of the semiconductor chip 17. In this embodiment, the first edge 11b of the support plate 11
The first and second chips are located on both sides of the semiconductor chip 17 along the
terminal members 18 and 19 are arranged. The semiconductor chip 17 has a first end 17a on the side of the first edge 11b of the support plate 11, and a second edge 11 of the support plate 11.
It has a second end 17b on the c side, a third end 17c on the third edge 11d side of the support plate 11, and a fourth end 17d on the fourth edge 11e side of the support plate 11.

第一の端子部材１８及び第二の端子部材１９は
それぞれセラミツクスから成る絶縁物チツプで、
それぞれ半導体チツプ１７の第三の端部１７ｃと
第四の端部１７ｄから若干離間して支持板１１上
に接着剤（図示せず）により直接的に固着されて
いる。第１の端子部材１８は端子部材本体１８ａ
と、端子部材本体１８ａに対し直角に折り曲げら
れた折曲げ部１８ｂとから成るＬ字形の平面形状
を有する。第一の端子部材１８の上面には電気的
に離間した２つの電極体３３及び３４が形成され
ている。電極体３３は電極体本体３３ａと、電極
体本体３３ａに対し直角に折曲げられた折曲げ部
３３ｂから成るＬ字形の平面形状に形成されてい
る。第一の端子部材１８の端子部材本体１８ａ、
電極体３３の電極体本体３３ａ、電極体３４は半
導体チツプ１７の第三の端部１７ｃ側に延在す
る。又第一の端子部材１８と電極体３３の各折曲
げ部１８ｂと３３ｂはそれぞれ半導体チツプ１７
の第二の端部１７ｂ側に延在する。第二の端子部
材１９の上面にも電気的に離間した２つの電極体
３５及び３６が配置されている。第二の端子部材
１９、電極体３５，３６は半導体チツプ１７の第
四の端部１７ｄ側に延在する。 The first terminal member 18 and the second terminal member 19 are each an insulating chip made of ceramics,
They are directly fixed onto the support plate 11 with an adhesive (not shown) at a slight distance from the third end 17c and fourth end 17d of the semiconductor chip 17, respectively. The first terminal member 18 is a terminal member main body 18a.
and a bent portion 18b bent at right angles to the terminal member main body 18a. Two electrically spaced electrode bodies 33 and 34 are formed on the upper surface of the first terminal member 18 . The electrode body 33 is formed into an L-shaped planar shape consisting of an electrode body body 33a and a bent portion 33b bent at right angles to the electrode body body 33a. Terminal member main body 18a of first terminal member 18,
The electrode body 33a of the electrode body 33 and the electrode body 34 extend toward the third end 17c of the semiconductor chip 17. Further, each bent portion 18b and 33b of the first terminal member 18 and the electrode body 33 is connected to the semiconductor chip 17, respectively.
It extends toward the second end 17b side. Two electrically spaced electrode bodies 35 and 36 are also arranged on the upper surface of the second terminal member 19. The second terminal member 19 and the electrode bodies 35 and 36 extend toward the fourth end 17d of the semiconductor chip 17.

リード細線２０〜３１は全て同一線径の金系細
線から成り、同一のワイヤボンデイング工程（ネ
イルヘツドボンデイング）において連続的に接続
される。半導体チツプ１７の第一の端部１７ａ側
に形成された電極３２ａ，３２ｂ，３２ｃはそれ
ぞれリード細線２０，２１，２２により外部リー
ド１４、支持板１１及び外部リード１５に接続さ
れている。半導体チツプ１７上の他の電極３２
ｄ，３２ｅ，３２ｆ，３２ｇ，３２ｈはそれぞれ
端子部材１８，１９上の電極体３３〜３６を介し
て各２本のリード細線２３〜３１により外部リー
ド１３〜１６に接続されている。即ち、電極３２
ｄは第一のリード細線としてのリード細線２７、
電極体３４及び第二のリード細線としてのリード
細線２４を介して外部リード１４に接続される。
電極体３２ｇ及び３２ｈはそれぞれ第一のリード
細線としてのリード細線３０，３１、電極体３
５，３６及び第二のリード細線としてのリード細
線２５，２６を介して外部リード１５，１６に接
続される。 The lead wires 20 to 31 are all made of gold-based thin wires having the same wire diameter, and are continuously connected in the same wire bonding process (nail head bonding). Electrodes 32a, 32b, and 32c formed on the first end 17a side of the semiconductor chip 17 are connected to the external lead 14, the support plate 11, and the external lead 15 by thin lead wires 20, 21, and 22, respectively. Other electrodes 32 on semiconductor chip 17
d, 32e, 32f, 32g, and 32h are connected to external leads 13 to 16 by two thin lead wires 23 to 31 via electrode bodies 33 to 36 on terminal members 18 and 19, respectively. That is, the electrode 32
d is a lead thin wire 27 as a first lead thin wire;
It is connected to the external lead 14 via the electrode body 34 and a thin lead wire 24 as a second thin lead wire.
Electrode bodies 32g and 32h are lead wires 30 and 31 as first lead wires, and electrode body 3, respectively.
5, 36 and lead wires 25, 26 as second lead wires to the external leads 15, 16.

電極体３２ｅ及び３２ｆはそれぞれリード細線
２８，２９を介して電極体３３に接続され、電極
体３３はリード細線２３を介して外部リード１３
に接続される。 The electrode bodies 32e and 32f are connected to the electrode body 33 through the lead wires 28 and 29, respectively, and the electrode body 33 is connected to the external lead 13 through the lead wire 23.
connected to.

第一のリード細線としてのリード細線２７，３
０，３１の一端はそれぞれ半導体チツプ１７上の
電極３２ｄ，３２ｇ，３２ｈに対してボールボン
デイングされており、その接続部分の形状は図示
の如く釘頭形状となつている。また、リード細線
２７，３０，３１の他端はそれぞれ端子部材１
８，１９上の電極体３４，３５，３６に対してス
テイツチボンデイングされておりその接続部分の
形状は図示の如く線径方向に押圧されて扁平化し
た形状となつている。また、第二のリード細線と
してのリード細線２４，２５，２６の一端は端子
部材１８，１９上の電極体３４，３５，３６に対
してネイルヘツドボンデイングされており、その
接続部分の形状は釘頭形状となつている。また、
リード細線２４，２５，２６の他端はそれぞれ外
部リード１４，１５，１６に対してステイツチボ
ンデイングされており、その接続部分の形状は線
径方向に押圧されて扁平化した形状となつてい
る。ここで、リード細線２７，３０，３１の電極
体３４，３５，３６との接続部は半導体チツプ１
７の第一の端部１７ａと第二の端部１７ｂとの間
に位置する。また、リード細線２４の電極体３４
との接続部は半導体チツプ１７の第三の端部１７
ｃと支持板１１の第三の縁部１１ｄとの間に位置
し、リード細線２５，２６と電極体３５，３６と
の接続部は半導体チツプ１７の第四の端部１７ｄ
と支持板１１の第四の縁部１１ｅとの間に位置す
る。 Lead thin wires 27, 3 as first lead thin wires
0 and 31 are ball-bonded to electrodes 32d, 32g, and 32h on the semiconductor chip 17, respectively, and the shape of the connecting portion is a nail head shape as shown in the figure. Further, the other ends of the lead thin wires 27, 30, 31 are connected to the terminal member 1, respectively.
The electrode bodies 34, 35, and 36 on the electrode bodies 8 and 19 are stitch-bonded, and the shape of the connecting portion is flattened by being pressed in the wire radial direction as shown in the figure. Further, one end of the lead wires 24, 25, 26 as the second lead wires is nail head bonded to the electrode bodies 34, 35, 36 on the terminal members 18, 19, and the shape of the connecting portion is a nail head bonding. It is shaped like a head. Also,
The other ends of the thin lead wires 24, 25, and 26 are stitch-bonded to the external leads 14, 15, and 16, respectively, and the shape of the connecting portion is flattened by being pressed in the wire radial direction. . Here, the connection portions of the thin lead wires 27, 30, 31 with the electrode bodies 34, 35, 36 are connected to the semiconductor chip 1.
7 between the first end 17a and the second end 17b. In addition, the electrode body 34 of the lead thin wire 24
The connection part with the third end 17 of the semiconductor chip 17 is
c and the third edge 11d of the support plate 11, and the connecting portion between the lead wires 25, 26 and the electrode bodies 35, 36 is located between the fourth edge 17d of the semiconductor chip 17.
and the fourth edge 11e of the support plate 11.

本実施例は以下の効果を有する。 This embodiment has the following effects.

(1) 外部リード１２〜１６が支持板１１の第一の
端部１１ｂ側にのみ配置されたリードフレーム
となつているため、外部リード１６より支持板
１１を肉厚に形成でき、放熱性の良好な半導体
装置を提供できる。(1) Since the external leads 12 to 16 are arranged as a lead frame only on the first end 11b side of the support plate 11, the support plate 11 can be made thicker than the external leads 16, which improves heat dissipation. A good semiconductor device can be provided.

(2) 半導体チツプ１７上の第三の端部１７ｃ及び
第四の端部１７ｄ側に形成された電極３２ｄ，
３２ｇ，３２ｈに接続されたリード細線２７，
３０，３１が外部リード１２〜１６の配列方向
に導出されている。また、リード細線２７，３
０，３１と電気的に接続状態にあるリード細線
２４，２５，２６がそれぞれ外部リード１４，
１５，１６の延在する方向に向かつて配線され
ている。したがつて、リード細線を互いに離間
して配線でき、リード細線間の接触に伴う電気
的短絡事故を防止できる。(2) electrodes 32d formed on the third end 17c and fourth end 17d sides of the semiconductor chip 17;
Thin lead wire 27 connected to 32g and 32h,
30 and 31 are led out in the direction in which the external leads 12 to 16 are arranged. In addition, lead thin wires 27, 3
The thin lead wires 24, 25, 26 electrically connected to the external leads 14, 31 respectively
The wires are wired in the direction in which the wires 15 and 16 extend. Therefore, the thin lead wires can be wired at a distance from each other, and it is possible to prevent electrical short circuits caused by contact between the thin lead wires.

(3) 端子部材１８，１９上の電極体３３〜３６を
介して接続するので、リード細線の接続距離を
短縮でき、リード細線の垂下を防止できる。(3) Since the connection is made via the electrode bodies 33 to 36 on the terminal members 18 and 19, the connection distance of the thin lead wire can be shortened and the thin lead wire can be prevented from drooping.

(4) 端子部材１９上の電極体３５とリード細線３
１とのクロスオーバー配線が可能となり、複雑
な配線に対応できる。(4) Electrode body 35 and thin lead wire 3 on terminal member 19
Cross-over wiring with 1 is possible, making it possible to handle complex wiring.

(5) Ｌ字形状の端子部材１８及び電極体３３に接
続されたリード細線２３，２８及び２９を介し
て、外部リード１３と半導体チツプ１７の外部
リード１３側と反対側に形成された電極３２
ｅ，３２ｆとを容易に接続できる。(5) The electrode 32 formed on the external lead 13 and the side of the semiconductor chip 17 opposite to the external lead 13 side is connected to the L-shaped terminal member 18 and the thin lead wires 23, 28, and 29 connected to the electrode body 33.
e, 32f can be easily connected.

(6) 端子部材１８の端子部材本体１８ａと第２の
端子部材１９が半導体チツプ１７の第一の端部
１７ａの延長線と第二の端部１７ｂの延長線と
の間に配置され、半導体装置の縦のサイズを短
縮できる。(6) The terminal member body 18a of the terminal member 18 and the second terminal member 19 are arranged between the extension line of the first end 17a and the extension line of the second end 17b of the semiconductor chip 17, and the semiconductor The vertical size of the device can be shortened.

(7) 半導体チツプ１７が支持板１１に半田で直接
固着されているため放熱性が良い。(7) Since the semiconductor chip 17 is directly fixed to the support plate 11 with solder, heat dissipation is good.

変形例 本考案の上記実施例は変更が可能である。例え
ば、端子部材１８，１９上面には必要に応じて抵
抗体等の電子素子を設けても良い。また、支持板
１１の第二の端部１１ｃ側にも外部リードを配置
してもよい。端子部材上の電極体に対する第一の
リード細線の接続部と第二のリード細線の接続部
を重ねて形成してもよい。更に、一端が半導体チ
ツプ上の電極に接続されたリード細線を端子部材
上の電極体に一度接続させてからその他端を外部
リードに接続して第一のリード細線と第二のリー
ド細線を同一のリード細線としてもよい。Modifications The above embodiments of the present invention can be modified. For example, electronic elements such as resistors may be provided on the upper surfaces of the terminal members 18 and 19 as necessary. Further, an external lead may also be arranged on the second end 11c side of the support plate 11. The connecting portion of the first thin lead wire and the connecting portion of the second thin lead wire to the electrode body on the terminal member may be formed in an overlapping manner. Furthermore, the lead thin wire whose one end is connected to the electrode on the semiconductor chip is once connected to the electrode body on the terminal member, and the other end is connected to the external lead to make the first lead thin wire and the second lead thin wire the same. It may also be used as a thin lead wire.

図示の実施例では、端子部材１８，１９上の電
極体３４〜３６と第二のリード細線２４〜２６と
の接続部分は半導体チツプ１７の第三の端部１７
ｃと支持板１１の第三の縁部１１ｄとの間及び半
導体チツプ１７の第四の端部１７ｄと支持板１１
の第四の縁部１１ｅとの間に位置している例を示
したが、端子部材１８，１９上の電極体３４〜３
６と第二のリード細線２４〜２６との接続部分は
半導体チツプ１７の第三の端部１７ｃの延長線と
支持板１１の第三の縁部１１ｄとの間又は半導体
チツプ１７の第四の端部１７ｄの延長線と支持板
１１の第四の縁部１１ｅとの間に位置してもよ
い。 In the illustrated embodiment, the connection portion between the electrode bodies 34 to 36 on the terminal members 18 and 19 and the second thin lead wires 24 to 26 is connected to the third end 17 of the semiconductor chip 17.
c and the third edge 11d of the support plate 11, and between the fourth end 17d of the semiconductor chip 17 and the support plate 11.
Although the example in which the electrode bodies 34 to 3 on the terminal members 18 and 19 are located between the fourth edge 11e of
6 and the second thin lead wires 24 to 26 are connected between the extension line of the third end 17c of the semiconductor chip 17 and the third edge 11d of the support plate 11, or between the fourth end of the semiconductor chip 17. It may be located between the extension of the end 17d and the fourth edge 11e of the support plate 11.

考案の効果 以上のように、本考案によれば外部リードと半
導体チツプとを短絡事故が発生することなく複数
本のリード細線で接続でき、かつ放熱性の良好な
半導体装置を提供できる。Effects of the Invention As described above, according to the present invention, it is possible to provide a semiconductor device in which an external lead and a semiconductor chip can be connected with a plurality of thin lead wires without causing a short-circuit accident, and which has good heat dissipation.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例に係わる電力用半導
体装置の斜視図、第２図は従来の電力用半導体装
置の平面図である。 １１……支持板、１１ａ……主面、１１ｂ……
第一の縁部、１１ｃ……第二の縁部、１１ｄ……
第三の縁部、１１ｅ……第四の縁部、１２〜１６
……外部リード、１７……半導体チツプ、１７ａ
……第一の端部、１７ｂ……第二の端部、１７ｃ
……第三の端部、１７ｄ……第四の端部、１８，
１９……端子部材、２４〜２６……第二のリード
細線、２７，３０，３１……第一のリード細線、
３２ａ〜３２ｈ……電極、３３〜３６……電極
体。 FIG. 1 is a perspective view of a power semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view of a conventional power semiconductor device. 11...Support plate, 11a...Main surface, 11b...
First edge, 11c... Second edge, 11d...
Third edge, 11e...Fourth edge, 12-16
...External lead, 17...Semiconductor chip, 17a
...First end, 17b...Second end, 17c
...Third end, 17d...Fourth end, 18,
19...Terminal member, 24-26...Second thin lead wire, 27, 30, 31...First thin lead wire,
32a to 32h... electrode, 33 to 36... electrode body.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 支持板と、該支持板の主面に固着された半導体
チツプと、該半導体チツプ上に形成された電極に
電気的に接続された複数の外部リードとを有する
半導体装置において、前記外部リードは前記支持
板の第一の縁部の側方のみにおいて又は前記支持
板の第一の縁部とそれに対向する第二の縁部の側
方のみにおいて前記支持板の前記第一及び第二の
縁部に沿つて並置され、前記支持板の前記第一の
縁部と前記第二の縁部との間に形成された第三の
縁部と第四の縁部の側方には前記外部リードが配
置されておらず、前記支持板の平均的な肉厚は前
記外部リードの平均的肉厚よりも大きく、前記支
持板の主面には前記半導体チツプから離間して端
子部材が固着され、前記半導体チツプ上の電極と
前記端子部材上に形成された電極体は第一のリー
ド細線によつて電気的に接続され、前記端子部材
上の電極体と前記外部リードは第二のリード細線
によつて電気的に接続されることにより、前記半
導体チツプ上の電極と、前記外部リードとが電気
的に接続されており、前記半導体チツプは前記支
持板の第一の縁部側に形成された第一の端部と前
記支持板の第二の縁部側に形成された第二の端部
と、前記支持板の第三の縁部側形成された第三の
端部と、前記支持板の第四の縁部側に形成された
第四の端部とを有し、前記端子部材上の電極体と
前記第一のリード細線との接続部分は前記半導体
チツプの第一の端部の延長線と第二の端部の延長
線との間に位置し、前記端子部材上の電極体と前
記第二のリード細線との接続部分は前記半導体チ
ツプの第三の端部又は第三の端部の延長線と前記
支持板の第三の縁部との間又は前記半導体チツプ
の第四の端部又は第四の端部の延長線と前記支持
板の第四の縁部との間に位置していることを特徴
とする半導体装置。 In a semiconductor device including a support plate, a semiconductor chip fixed to a main surface of the support plate, and a plurality of external leads electrically connected to electrodes formed on the semiconductor chip, the external leads are connected to the the first and second edges of the support plate only on the sides of the first edge of the support plate or only on the sides of the first edge and the second edge opposite thereto; The external leads are arranged on the sides of a third edge and a fourth edge formed between the first edge and the second edge of the support plate. The average thickness of the support plate is larger than the average thickness of the external leads, and a terminal member is fixed to the main surface of the support plate at a distance from the semiconductor chip. The electrode on the semiconductor chip and the electrode body formed on the terminal member are electrically connected by a first thin lead wire, and the electrode body on the terminal member and the external lead are connected by a second thin lead wire. The electrodes on the semiconductor chip are electrically connected to the external leads, and the semiconductor chip is connected to the electrodes formed on the first edge side of the support plate. a second end formed on the second edge side of the support plate; a third end formed on the third edge side of the support plate; a fourth end formed on a fourth edge side, and a connection portion between the electrode body on the terminal member and the first thin lead wire is an extension of the first end of the semiconductor chip. The connection portion between the electrode body on the terminal member and the second thin lead wire is located between the wire and the extension line of the second end, and the connection portion between the electrode body on the terminal member and the second thin lead wire is located at the third end of the semiconductor chip or the third end. between the extension line of the semiconductor chip and the third edge of the support plate, or between the fourth end of the semiconductor chip or the extension line of the fourth end and the fourth edge of the support plate. A semiconductor device characterized in that:
JP1988111185U 1988-08-26 1988-08-26 Expired JPH0451476Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988111185U JPH0451476Y2 (en) 1988-08-26 1988-08-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988111185U JPH0451476Y2 (en) 1988-08-26 1988-08-26

Publications (2)

Publication Number Publication Date
JPH0233433U JPH0233433U (en) 1990-03-02
JPH0451476Y2 true JPH0451476Y2 (en) 1992-12-03

Family

ID=31349014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988111185U Expired JPH0451476Y2 (en) 1988-08-26 1988-08-26

Country Status (1)

Country Link
JP (1) JPH0451476Y2 (en)

Also Published As

Publication number Publication date
JPH0233433U (en) 1990-03-02

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