JPS6030162A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6030162A
JPS6030162A JP58124334A JP12433483A JPS6030162A JP S6030162 A JPS6030162 A JP S6030162A JP 58124334 A JP58124334 A JP 58124334A JP 12433483 A JP12433483 A JP 12433483A JP S6030162 A JPS6030162 A JP S6030162A
Authority
JP
Japan
Prior art keywords
substrates
chips
semiconductor device
wall
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58124334A
Other languages
Japanese (ja)
Inventor
Tsunehiro Kobayashi
小林　経広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP58124334A priority Critical patent/JPS6030162A/en
Publication of JPS6030162A publication Critical patent/JPS6030162A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To dissipate heat from both the upper and lower surfaces of a vessel, and to miniaturize a semiconductor device for power by constituting both surfaces by metallic substrates and each fixing semiconductor element pieces to the substrates. CONSTITUTION:Two power transistor chips 2 are brazed to upper and lower metallic substrates 11, 12 by collector surfaces, and the substrates 11, 12 are connected by a vessel circumferential-wall 7 consisting of an insulator. Emitter electrodes for both chips 2 are connected to an emitter terminal conductor 4 penetrating the wall 7 by conductors 6, and conductors 6 connected to base electrodes are lead out through a penetrating conductor 8 in the wall 7, and connected to a base terminal. Heat generated in the chips is dissipated from both substrates, the same capacitance can be obtained from the two parallel connected chips in half size, and a semiconductor chip can be miniaturized.

Description

【発明の詳細な説明】 本発明はパワートランジスタ，サイリスタなどのように
作動中に半導体片内に発生する熱を放散するため半導体
片を放熱板上に固定する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, such as a power transistor or a thyristor, in which a semiconductor piece is fixed on a heat sink in order to dissipate heat generated within the semiconductor piece during operation.

〔従来技術とその問題点〕[Prior art and its problems]

このような半導体装置は、例えば第１図に示すパワート
ランジスタのように金属基板ｌの上にトランジスタチッ
プ２のコレクタ面を固着し、基板１に絶縁片３を介して
固定されたエミッタ端子へ。In such a semiconductor device, for example, as in the power transistor shown in FIG. 1, the collector surface of a transistor chip 2 is fixed onto a metal substrate 1, and an emitter terminal is fixed to the substrate 1 via an insulating piece 3.

ベース端子５と基板１の上面のエミツタ電極．ペース電
極とを導線６によって接続している。さらに半導体チッ
プ２を＆うように樹脂Ｊ３がモールドされている。この
装置の作動中チップ２に発生する熱は一部は樹脂１３を
介して放散されるが、大部分は基板ｌを介して冷却体等
へ放散される。このような構造の半導体装置では、素子
の大容量化に伴ないチップの大きさが大きくなるので装
部の外形も非常に大き°くなってしまう。Base terminal 5 and emitter electrode on the top surface of substrate 1. It is connected to the pace electrode by a conducting wire 6. Furthermore, a resin J3 is molded so as to cover the semiconductor chip 2. During operation of this device, part of the heat generated in the chip 2 is dissipated through the resin 13, but most of it is dissipated through the substrate 1 to a cooling body or the like. In a semiconductor device having such a structure, the size of the chip increases as the capacity of the device increases, so the outer shape of the housing also becomes very large.

〔発明の目的〕[Purpose of the invention]

本発明は、これに対して装置の右肩面積を大きくするこ
となく大容量化が達成できる半導体装置を提供すること
を目的とする。In contrast, it is an object of the present invention to provide a semiconductor device that can achieve a large capacity without increasing the right shoulder area of the device.

〔発明の要点〕[Key points of the invention]

本発明は半導体装置の容器が間隔を置いて対向する二つ
の金属基板と両基板を周縁で結合する側壁からなシ、両
基板にはそれぞれ半導体素子片が導電的に固着され、両
生導体素子片の自由表面にある電極は側壁を両基板に絶
縁されて貫通する端子導体に接続されていることにより
、半分の大きさの素子片により所望の容量を得るように
したものである。In the present invention, a container for a semiconductor device includes two metal substrates facing each other at a distance, and a side wall connecting the two substrates at their peripheries.A semiconductor element piece is electrically conductively fixed to each of the two substrates, and a bidirectional conductor element piece is attached to each of the two substrates. The electrodes on the free surface of the device are connected to terminal conductors that pass through the side walls of the device insulated from both substrates, thereby achieving the desired capacitance with an element piece that is half the size of the device.

〔発明の実施例〕[Embodiments of the invention]

第２図は本発明の一実施例を示し、第１図と共通部分に
は同一の符号が付されている。二つのパワートランジス
タチップ２は、それぞれ上下の金属基板１１　、１２に
そのコレクタ面によってろう付けされ、両基板１１　、
１２は絶縁物の容器周壁７によって連結されると共に図
示しない導体によって接続されている。両チップ２のエ
ミッタ電極は壁ツを貫通するエミッタ端子導体４に導線
６によってそれぞれ接続され、一方ベース電極に接続さ
れる導線６は壁７の貫通導体８を介して引き出され、ベ
ース端子９に接続されている。トランジスタチップ２に
、例えばプレーナ素子片のようなパッシベーションチッ
プを採用すれば、チップを特に樹脂で被覆する必要はな
い。この構造では半導体装置の容器の両面が金属基板で
構成され、チップに発生する熱は両基板から放熱されす
るので、同じ容量を半分の大きさの二つの並列接続チッ
プから得ることができ、番会式第１図に示す構造に比し
て小形にすることができる。FIG. 2 shows an embodiment of the present invention, and parts common to those in FIG. 1 are given the same reference numerals. The two power transistor chips 2 are brazed to upper and lower metal substrates 11 and 12 by their collector surfaces, respectively, and both substrates 11 and
12 are connected by an insulating container peripheral wall 7 and are also connected by a conductor (not shown). The emitter electrodes of both chips 2 are connected to the emitter terminal conductor 4 passing through the wall 7 by conductive wires 6, while the conductive wire 6 connected to the base electrode is led out through the through conductor 8 of the wall 7 and connected to the base terminal 9. It is connected. If a passivation chip such as a planar element piece is used as the transistor chip 2, there is no need to cover the chip with a resin. In this structure, both sides of the semiconductor device container are made of metal substrates, and the heat generated in the chip is dissipated from both substrates, so the same capacity can be obtained from two parallel-connected chips of half the size. The structure can be made smaller than the structure shown in FIG.

両基板１１　、１２は同電位であるため、導体の周壁を
用いて連結してもよく、その場合各端子はガラスシール
等により容器周壁と絶縁して引き出される。Since both substrates 11 and 12 have the same potential, they may be connected using a conductor peripheral wall, in which case each terminal is drawn out while being insulated from the container peripheral wall by a glass seal or the like.

〔発明の効果〕〔Effect of the invention〕

本発明は容器の上下両面を金属基板によって構成し、そ
れぞれに半導体素子片を固着することによシ平形半導体
素子のように両面放熱を可能にしたもので、電力用半導
体装置の小形化のために極めて有利な効果をもたらすも
のである。The present invention consists of metal substrates on both the upper and lower surfaces of the container, and by fixing semiconductor element pieces to each, it is possible to dissipate heat on both sides like a flat semiconductor element, and this is useful for downsizing power semiconductor devices. This has extremely beneficial effects.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のパワートランジスタの一例の断面図、第
２図は本発明の一実施例であるパワートランジスタの断
面図である。 ］、１　、１２・・・金属基板、２　・トランジスタチ
ップ、４・エミッタ端子、６　・導線、７・・容器周壁
、９・・・ベース端子。FIG. 1 is a sectional view of an example of a conventional power transistor, and FIG. 2 is a sectional view of a power transistor that is an embodiment of the present invention. ], 1, 12...Metal substrate, 2.Transistor chip, 4.Emitter terminal, 6.Conducting wire, 7.. Container peripheral wall, 9..Base terminal.

Claims (1)

【特許請求の範囲】[Claims] １）間隔を置いて対向する二つの金属基板と両基板を周
縁で結合する側壁からなる容器を備え、該容器の両基板
にはそれぞれ半導体素子片が導電的に固着され、該両生
導体素子片の自由表面にある電極は前記容器側壁を前記
両基板に絶縁されて貫通する端子導体に接続されたこと
を特徴とする半導体装置。1) A container consisting of two metal substrates facing each other at a distance and a side wall connecting both substrates at their peripheries, a semiconductor element piece being electrically conductively fixed to both substrates of the container, and a bidirectional conductor element piece. A semiconductor device characterized in that an electrode on a free surface of the semiconductor device is connected to a terminal conductor that penetrates the side wall of the container and is insulated from both the substrates.
JP58124334A 1983-07-08 1983-07-08 Semiconductor device Pending JPS6030162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58124334A JPS6030162A (en) 1983-07-08 1983-07-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58124334A JPS6030162A (en) 1983-07-08 1983-07-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6030162A true JPS6030162A (en) 1985-02-15

Family

ID=14882766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58124334A Pending JPS6030162A (en) 1983-07-08 1983-07-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6030162A (en)

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