JPS61256724A - プラズマ・エツチ開孔のプロフイルを制御する方法 - Google Patents

プラズマ・エツチ開孔のプロフイルを制御する方法

Info

Publication number
JPS61256724A
JPS61256724A JP61076856A JP7685686A JPS61256724A JP S61256724 A JPS61256724 A JP S61256724A JP 61076856 A JP61076856 A JP 61076856A JP 7685686 A JP7685686 A JP 7685686A JP S61256724 A JPS61256724 A JP S61256724A
Authority
JP
Japan
Prior art keywords
layer
etching
profile
etch
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61076856A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0519977B2 (enExample
Inventor
リー・チェン
ガンガーダラ・スワミ・マサド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS61256724A publication Critical patent/JPS61256724A/ja
Publication of JPH0519977B2 publication Critical patent/JPH0519977B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
JP61076856A 1985-05-06 1986-04-04 プラズマ・エツチ開孔のプロフイルを制御する方法 Granted JPS61256724A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US730976 1985-05-06
US06/730,976 US4671849A (en) 1985-05-06 1985-05-06 Method for control of etch profile

Publications (2)

Publication Number Publication Date
JPS61256724A true JPS61256724A (ja) 1986-11-14
JPH0519977B2 JPH0519977B2 (enExample) 1993-03-18

Family

ID=24937562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61076856A Granted JPS61256724A (ja) 1985-05-06 1986-04-04 プラズマ・エツチ開孔のプロフイルを制御する方法

Country Status (5)

Country Link
US (1) US4671849A (enExample)
EP (1) EP0201037B1 (enExample)
JP (1) JPS61256724A (enExample)
CA (1) CA1261785A (enExample)
DE (1) DE3679933D1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006505141A (ja) * 2002-10-31 2006-02-09 アプライド　マテリアルズ　インコーポレイテッド シリコン含有誘電物質をエッチングする方法

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US5006485A (en) * 1988-12-09 1991-04-09 U.S. Philips Corporation Method of manufacturing an intergrated circuit including steps for forming interconnections between patterns formed at different levels
US5174857A (en) * 1990-10-29 1992-12-29 Gold Star Co., Ltd. Slope etching process
US5317938A (en) * 1992-01-16 1994-06-07 Duke University Method for making microstructural surgical instruments
US5880036A (en) * 1992-06-15 1999-03-09 Micron Technology, Inc. Method for enhancing oxide to nitride selectivity through the use of independent heat control
US5651855A (en) * 1992-07-28 1997-07-29 Micron Technology, Inc. Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits
JP2787646B2 (ja) 1992-11-27 1998-08-20 三菱電機株式会社 半導体装置の製造方法
US5466626A (en) * 1993-12-16 1995-11-14 International Business Machines Corporation Micro mask comprising agglomerated material
US6870272B2 (en) * 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US5842387A (en) * 1994-11-07 1998-12-01 Marcus; Robert B. Knife blades having ultra-sharp cutting edges and methods of fabrication
US6040247A (en) * 1995-01-10 2000-03-21 Lg Semicon Co., Ltd. Method for etching contact
US6284563B1 (en) * 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US6211572B1 (en) * 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
KR0179791B1 (ko) * 1995-12-27 1999-03-20 문정환 플래쉬 메모리 소자 및 그 제조방법
KR0179792B1 (ko) * 1995-12-27 1999-04-15 문정환 고밀도 플라즈마 식각장비를 이용한 슬로프 콘택 홀 형성방법
US6033991A (en) * 1997-09-29 2000-03-07 Cypress Semiconductor Corporation Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation
US6074957A (en) 1998-02-26 2000-06-13 Micron Technology, Inc. Methods of forming openings and methods of controlling the degree of taper of openings
PL356718A1 (en) 2000-10-11 2004-06-28 Koninklijke Philips Electronics N.V. Scalable coding of multi-media objects
WO2003066277A1 (en) * 2002-02-07 2003-08-14 Browne & Co. Ltd. Non-symmetrical photo tooling and dual surface etching
AU2003231967B2 (en) 2002-03-11 2006-10-12 Beaver-Visitec International (Us), Inc. System and method for the manufacture of surgical blades
US7387742B2 (en) * 2002-03-11 2008-06-17 Becton, Dickinson And Company Silicon blades for surgical and non-surgical use
US7355687B2 (en) * 2003-02-20 2008-04-08 Hunter Engineering Company Method and apparatus for vehicle service system with imaging components
US20040222518A1 (en) * 2003-02-25 2004-11-11 Tessera, Inc. Ball grid array with bumps
US20090007436A1 (en) * 2003-03-10 2009-01-08 Daskal Vadim M Silicon blades for surgical and non-surgical use
US20050155955A1 (en) * 2003-03-10 2005-07-21 Daskal Vadim M. Method for reducing glare and creating matte finish of controlled density on a silicon surface
WO2005027728A2 (en) * 2003-09-17 2005-03-31 Becton, Dickinson And Company Method for creating trenches in silicon wafers using a router
US7291360B2 (en) * 2004-03-26 2007-11-06 Applied Materials, Inc. Chemical vapor deposition plasma process using plural ion shower grids
US20050211171A1 (en) * 2004-03-26 2005-09-29 Applied Materials, Inc. Chemical vapor deposition plasma reactor having an ion shower grid
US7695590B2 (en) * 2004-03-26 2010-04-13 Applied Materials, Inc. Chemical vapor deposition plasma reactor having plural ion shower grids
US20050211546A1 (en) * 2004-03-26 2005-09-29 Applied Materials, Inc. Reactive sputter deposition plasma process using an ion shower grid
US7244474B2 (en) * 2004-03-26 2007-07-17 Applied Materials, Inc. Chemical vapor deposition plasma process using an ion shower grid
US20050211547A1 (en) * 2004-03-26 2005-09-29 Applied Materials, Inc. Reactive sputter deposition plasma reactor and process using plural ion shower grids
US7396484B2 (en) * 2004-04-30 2008-07-08 Becton, Dickinson And Company Methods of fabricating complex blade geometries from silicon wafers and strengthening blade geometries
US7767561B2 (en) * 2004-07-20 2010-08-03 Applied Materials, Inc. Plasma immersion ion implantation reactor having an ion shower grid
US8058156B2 (en) * 2004-07-20 2011-11-15 Applied Materials, Inc. Plasma immersion ion implantation reactor having multiple ion shower grids
JP4484641B2 (ja) * 2004-09-10 2010-06-16 Ｏｋｉセミコンダクタ株式会社 強誘電体メモリの製造方法
US7999379B2 (en) * 2005-02-25 2011-08-16 Tessera, Inc. Microelectronic assemblies having compliancy
US7883631B2 (en) * 2006-03-07 2011-02-08 Tokyo Electron Limited Plasma etching method, plasma etching apparatus, control program and computer-readable storage medium
US7749886B2 (en) 2006-12-20 2010-07-06 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
US8196285B1 (en) * 2008-12-17 2012-06-12 Western Digital (Fremont), Llc Method and system for providing a pole for a perpendicular magnetic recording head using a multi-layer hard mask
US8254060B1 (en) 2009-04-17 2012-08-28 Western Digital (Fremont), Llc Straight top main pole for PMR bevel writer
US8225488B1 (en) 2009-05-22 2012-07-24 Western Digital (Fremont), Llc Method for providing a perpendicular magnetic recording (PMR) pole
US9346672B1 (en) 2009-08-04 2016-05-24 Western Digital (Fremont), Llc Methods for fabricating damascene write poles using ruthenium hard masks
US8298881B2 (en) 2010-06-28 2012-10-30 International Business Machines Corporation Nanowire FET with trapezoid gate structure
US8525338B2 (en) 2011-06-07 2013-09-03 Tessera, Inc. Chip with sintered connections to package
EP2819162B1 (en) 2013-06-24 2020-06-17 IMEC vzw Method for producing contact areas on a semiconductor substrate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57164529A (en) * 1981-04-03 1982-10-09 Oki Electric Ind Co Ltd Dry etching method
JPS58197820A (ja) * 1982-05-14 1983-11-17 Nippon Telegr & Teleph Corp <Ntt> プラズマエツチング方法
JPS60182136A (ja) * 1984-02-29 1985-09-17 Fujitsu Ltd エツチング方法
JPS61114530A (ja) * 1984-11-09 1986-06-02 Oki Electric Ind Co Ltd ドライエツチング方法及びその装置

Family Cites Families (9)

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GB1417085A (en) * 1973-05-17 1975-12-10 Standard Telephones Cables Ltd Plasma etching
DE2658448C3 (de) * 1976-12-23 1979-09-20 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum Ätzen einer auf einem Halbleiterkörper aufgebrachten Schicht aus Siliciumnitrid in einem Gasplasma
US4283249A (en) * 1979-05-02 1981-08-11 International Business Machines Corporation Reactive ion etching
US4324611A (en) * 1980-06-26 1982-04-13 Branson International Plasma Corporation Process and gas mixture for etching silicon dioxide and silicon nitride
US4409319A (en) * 1981-07-15 1983-10-11 International Business Machines Corporation Electron beam exposed positive resist mask process
US4417947A (en) * 1982-07-16 1983-11-29 Signetics Corporation Edge profile control during patterning of silicon by dry etching with CCl4 -O2 mixtures
DE3306703A1 (de) * 1983-02-25 1984-08-30 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von halbleitervorrichtungen
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57164529A (en) * 1981-04-03 1982-10-09 Oki Electric Ind Co Ltd Dry etching method
JPS58197820A (ja) * 1982-05-14 1983-11-17 Nippon Telegr & Teleph Corp <Ntt> プラズマエツチング方法
JPS60182136A (ja) * 1984-02-29 1985-09-17 Fujitsu Ltd エツチング方法
JPS61114530A (ja) * 1984-11-09 1986-06-02 Oki Electric Ind Co Ltd ドライエツチング方法及びその装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006505141A (ja) * 2002-10-31 2006-02-09 アプライド　マテリアルズ　インコーポレイテッド シリコン含有誘電物質をエッチングする方法

Also Published As

Publication number Publication date
CA1261785A (en) 1989-09-26
EP0201037B1 (en) 1991-06-26
JPH0519977B2 (enExample) 1993-03-18
US4671849A (en) 1987-06-09
EP0201037A2 (en) 1986-11-12
DE3679933D1 (de) 1991-08-01
EP0201037A3 (en) 1988-03-23

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