JPS61255434A - Data aligning device - Google Patents

Abstract

PURPOSE:To perform easily the control of the memory and to shorten the data aligning time by providing two same constituted memories at one comparing unit. CONSTITUTION:A data aligning device 10 is constituted by connecting in cascade plural comparing units 40-I-40-U. Respective comparing units 40 are composed of a memory 103 to store one side aligned data partial set inputted from an input terminal 601, a memory 104 to store the other side aligned data partial set, reading/writing circuits 105-1 and 105-2 to read and write respectively the data to memories 103 and 104, registers 106 and 107 to store respectively one byte of the data of the memories 103 and 104, a comparator 108 to compare the value of the data stored at the registers 106 and 107, a multiplexer 109 to select the channel for transferring the data of either of the registers 106 and 107 to an output terminal 102, and a control circuit 110 to receive the compared result signal from the comparator 108 and to control respective parts of said comparing units based on it.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a data sorting device that sorts a data set in ascending order of data values.

[Conventional technology]

Generally, a data sorting device merges two sorted data subsets and increases the number of data included in the sorted data subsets to 1, 2, 4, etc. It has a configuration in which a plurality of comparison units that increase in size each time are connected in cascade. Conventional data alignment devices can be roughly divided into two types depending on the configuration of the comparison unit. Hereinafter, these will be referred to as the A method and the B method.

First, the A-type data alignment device will be explained with reference to FIGS. 6 to 8.

FIG. 6 is a diagram showing an example of the device configuration of method A, in which 10 is a data alignment device, 20 is a data input terminal of device 1, 30 is a data output terminal of device 1, and 40-1 to 40-U are It is a comparison unit. Each comparison unit has a memory 603 that stores one of the sorted data subsets inputted from the input terminal 601, has the same size as the memory 603, and stores the other sorted data subset inputted from the input terminal 601. Memory 604, read/write circuit 605 for reading and writing data to and from memories 603 and 604; memory 60;
Register 606.3 stores 1 byte of data of No.3. Register 607 that stores 1 byte of data in memory 604
．． A comparator 608 compares the data values stored in registers 606 and 607, and register 60 according to the comparison result.
The multiplexer 609 establishes a path for transferring data stored in either one of the terminals 6 and 607 to the output terminal 602. In this case, the sizes of the memories 603 and 604 are 1 data in the comparison unit 40-1, 40-
2 has 2 data, 40-3 has 4 data, 40
-U has a size that can store 2U-1 pieces of data.

FIG. 7 shows a time chart of an example of merging processing of data subset pairs in the comparison unit 40-3 of FIG. 6. 7th
The figure shows the process of merging two pairs of data subsets each consisting of four data sets of 1 byte. In FIG. 7, 700 is a data pair comparison process, and 701 is a memory 6.
702 is the process of reading 1 byte from the memory 604 and storing it in the register 607. 703 is the process of reading 1 byte from the memory 604 and storing it in the register 606.
and 607, and according to the comparison result, the data in one register is selected by the multiplexer 609 and sent from the output terminal 602 to the comparison unit 4.
0-4, and at the same time, one byte of data is written from the comparison unit 40-2 to the memory 603 or 604 via the input terminal 601. 7
04 is data having a size of 1 byte. 705-
1 and 706-1 are 1 input sequentially from the input terminal 601.
The second sorted data subset pair 707-1 is the sorted output data subset after merging with respect to the data subset pair. Similarly, 705-2 and 706-2 are the second sorted input data subset pair, and 707-2 is the sorted output data subset after merging the data subset pair.

Regarding the example of FIG. 7, the state of processing in the comparison unit 40-3 is shown in FIG. 8.

In FIG. 8, "8" and rVj are each registered in the register 606.
．． It shows that the data of 607 is smaller, and "x" shows that it is not compared. 800 is memory 603,6
04, 800-1 is the delimiter between data subsets 705-1 and 705-2, 80
0-2 indicates a delimiter between data subsets 706-1 and 706-2.

The times correspond to the times and processes 701, 702, and 703 in FIG.

By the way, in the A-type data alignment device, as shown in FIG. 6, since there is only one circuit for reading/writing data to the memories 603 and 604, reading and writing can only be performed sequentially. Therefore, as shown in FIG. 7, three processes are required for reading and writing to the memory for processing one byte. Furthermore, the next data subset cannot be input until all of the data subsets in either memory 603 or 604 have been output. In the example of FIG. 7, data subsets 705-1 and 706-1 are stored in memories 603 and 606, respectively.
04, and at the time when data subset 705-1 has finished outputting, input of primary data subset 705-2 is started.

For this reason, depending on the data value, there is time available for inputting a data subset, as shown in FIG. For these two reasons, method A has the disadvantage of slow processing time.

Next, the B-type data alignment device will be explained with reference to FIGS. 9 to 11.

FIG. 9 is a diagram showing an example of the device configuration of the B method, and the data sorting device 10 has a configuration in which comparison units 40-1 to 40-U are connected in cascade, which is similar to FIG. 6. Each comparison unit includes a memory 903 which stores a sorted data subset input from an input terminal 901, a memory 904 having a size of one data, a read/write circuit of the memory 903, and a memory 905 having a size of one byte. registers 906, 907, and 910, and a comparator 908 to compare the values of the data stored in registers 906 and 907; register 90;
6 or 907 to the data output terminal 9
It consists of a multiplexer 909 that selects the route to be transferred to 02. As in the case of FIG.
So 2 data, 40-3 4 data, 40-
U has a size that can store 2'' pieces of data.

FIG. 10 is a time chart showing an example of merging processing of data subset pairs in the comparison unit 40-3 of FIG. 9. In FIG. 10, 1000 is a data pair comparison process, which is divided into two processes 1001 and 1002.

Process 1001 selects one of the following operations from ■ to ■ and the data of one of the registers 906 and 907 using the multiplexer 909 based on the comparison result, and outputs the data to the data output terminal 902.
This is a process that simultaneously performs the operation of outputting data to the PC, and the operations of (1) and (2) are as follows.

■ Input data from the data input terminal 901.

It is stored in the register 907 via the memory 904.

(2) Input data from the data input terminal 901 and store it in the register 910.

(2) In addition to the operation (2), one byte of data is read from the memory 903 and stored in the register 906.

(2) In addition to the operation (2), the data in register 906 is stored in register 907.

Processing 1002 stores the data in the register 910 in the memory 90.
At the same time, data values in registers 906 and 907 are compared by a comparator 908 to obtain a comparison result. 1003 indicates data with a size of 1 byte, 1004 indicates one sorted input data subset, 10
05 is the other sorted input data subset, 1006 is the output data subset after merging, and 1004-1 and 100
The result of merging 5-1 is 1006-1, which is 1004
The result of merging -2 and 1005-2 is 1006-2.

FIG. 11 shows in detail the processing in the comparison unit 40-3 for the example of FIG. 10. 11th
In the figure, since the data size is 1 byte, the unused memory 904 is omitted.

1100 is a delimiter between data subsets in the memory 903; 1100-1 is a delimiter between data subsets 1004-1 and 1005-1; 1100-2 is a delimiter between data subsets 1004-1 and 1004-2; -3 is data subset 1005-1 and 1004-2.1100
-4 indicates a break between data subsets 1004-2 and 1005-2, and 1101 indicates a pointer that connects data included in one data subset within memory 903.

The time corresponds to the time and processes 1001 and 1002 in FIG.

As shown in FIG. 10, in the B-type data alignment device,
Since there is no time gap between input and output of data subsets,
Although it is possible to speed up the processing time, it has the disadvantage that the control is very complicated.6 In other words, in the case of process 1001 in FIG. 10, there are many separate processes. Also, memory 9
Up to three data subsets are stored in 03, making data management complicated. In the 10th rXI example, at the time of data input at time 9, the data subset 1 is stored in the memory 903.
Data of 004-1.1004-2.1004-3 is stored.

[Purpose of the invention]

An object of the present invention is to provide a data alignment device that is easy to control and can reduce data alignment time.

[Features of the invention]

In the present invention, each comparison unit of the data sorting device is provided with two memories, and data input to the comparison unit is stored in two memories.
The data is copied and stored in two memories at the same time, and the data in these memories is used to perform a merging process.

[Embodiments of the invention]

FIG. 1 is a diagram showing an example of the configuration of a data alignment device according to the present invention. In FIG. 1, the data sorting device 10 has a configuration in which a plurality of comparison units 40-1 to 40-U are connected in cascade. 20 is a 1-byte wide data input terminal of the device 10, 3
0 is the 1-byte wide data output terminal of the same device [10, 101 is the 1-byte wide data input terminal of the comparison unit,
102 is a 1-byte wide data output terminal of the comparison unit. Each comparison unit 40-1 to 40-U is connected to a memory 103 that stores one sorted data subset input from an input terminal 601, a memory 104 that stores the other sorted data subset, and memories 103 and 104. A read/write circuit 10 that reads and writes data respectively.
5-1, 105-2, a register 106 for storing one byte of data in the memory 103; 1 of data in memory 104
Register 107 that stores bytes, registers 106 and 1
Comparator 10 that compares the values of data stored in 07
8. A multiplexer 109 that selects a route for transferring data from one of the registers 106 and 107 to the output terminal 102, and receives a comparison result signal from the comparator 108;
It consists of a control circuit 110 that controls each part of the comparison unit based on this. The size of memories 103 and 104 is
Comparison unit 40-1 has 1 data, 40-2 has 2@(D data, 40-31' has 4 data, 40-
U has a size that can store 2 C1-1 pieces of data.

FIG. 2 is a diagram showing the transition of processing states in each comparison unit in FIG. 1, and 200 to 205 are states,
206 indicates the direction of transition.

Each state 200-205 consists of a write process and a read process.

Now merge the two sorted data subsets.

Let R and S be the order in which they are input to the comparison unit 40-i (i=1.2...U), and T be the sorted data subset that is input following S. State A of 200 consists of the following processing.

(2) Write processing: One byte of R data is input from the data input terminal 101, and is copied and stored in the memories 103 and 104.

■ Read processing: Do nothing.

State sA is repeated until all data of R has been inputted, and then the state transitions to state B of 201. State B consists of the following processing.

(2) Write processing: One byte of S data is input from the data input terminal 101 and stored in either memory 103 or 104.

■ Read processing: Read one byte of R or S data from the memory 103 and store it in the register 106.

One byte of S or R data is read from the memory 104 and stored simultaneously in the register 107.
The comparator 10 compares the data values stored in 06 and 107.
8 and notifies the control circuit 110 of the comparison result.

State B is processed only for the first byte of S.

If S has remaining data, go to state C.

If there is no state, the state transitions to state E. State C of 203 consists of the following processing.

- Write processing: Input 1 byte of S data from the data input terminal 101 and store it in the memory where all R is not stored. At the same time, one of registers 106 and 107 is selected by multiplexer 109 according to instructions from control circuit 110, and the selected data is output to data output terminal 102.

■ Read processing: Same as the read processing in state B.

Repeat state @C until all data in S has been input. If the final byte of the final data of either R or S stored in the memory 103 or memory 104 is output in the next process, the state changes to E, and if not, the state changes to O. State 204 consists of the following processing.

(2) Write processing: One byte of data of T is input from the data input terminal 101, and is copied and stored in the memories 103 and 104. At the same time, one of registers 106 and 107 is selected by multiplexer 109 according to instructions from control circuit 110, and the selected data is output to data output terminal 102.

■ Read processing: Same as the read processing in state B.

The state is repeated until the last byte of the final data of either R or S stored in the memory 103 or memory 104 is output in the next process, and then the state changes to state E. State E of 205 consists of the following processing.

■ Write processing: Input 1 byte of T data from the data input terminal 101 and write it to the memory 103 or memory 104.
Of these, the memory is stored in the memory where all R or S is output, or in the memory opposite to the memory where all R or S are output in this process. At the same time, one of registers 106 and 107 is selected by multiplexer 109 according to instructions from control circuit 110, and the selected data is output to data output terminal 102.

■ Read processing: If R or S remains from the memory 102, 1 byte of R or S data.

If there is no remaining data, read 1 byte of data from T and store it in register 106. At the same time, read 1 byte of data from memory 104 and store it in register 107 in the same way as in memory 103 (this N).

No comparison is performed, and the control circuit 110 instructs to output data from the register storing the R or S data in the next process).

State E is repeated until the final byte of the remaining final data of R or S is output in the next process, that is, all data of T has been input, and then state C is entered. Here, T is equal to R of the next pair of data subsets to be merged.

The state transition process shown in FIG. 2 is performed simultaneously in each comparison unit. Note that the above processing can be easily realized by using, for example, a microprocessor in the control circuit 110 of each comparison unit.

FIG. 3 is a time chart showing a processing example according to the present invention. In this example, the comparison unit 40-1°40-2.4
0-3, 8 pieces of 1-byte data are aligned. In FIG. 3, 300 indicates 1-byte processing, and 301 indicates write processing.

302 is read processing, and 303 is 1-byte data.

304 is a sorted data subset, and 305 is the state shown in FIG. Further, the time required for the process 300 is assumed to be one hour.

Regarding the example of FIG. 3, comparison unit 40-1 of FIG.
The movement of data within 40-2 and 40-3 is shown in detail in FIG. In FIG. 4, reference numeral 400 indicates the flow of data, 401 indicates the state shown in FIG. 2, 402 indicates the comparison result, and 403 indicates the division of data subsets. As a result of the comparison, "V" indicates that the value of the data stored in the register 106 is greater than the value of the data stored in the register 107, and "Δ" indicates that the value of the data stored in the register 107 is smaller.

"11" means equal, and "x" means no comparison.

Although FIG. 3 shows an example in which the data size is 1 byte, the present invention can be easily expanded to cases where the data size is arbitrary. When the data size is L bytes, the processing start time of the comparison unit 40 i (t==1.2°3,...U) is set to (21-"-1)L+i time, and the two data are compared. can be done as follows. That is, the size L
When two bytes of data have the same value, the output up to K bytes will be any one of registers 106 and 107, and the next comparison byte will be the next byte of each data.

If the size of 2 data is determined at the K+1st byte, then K+1
Bytes to L bytes are output depending on the value of the entire data. The next data to be compared is the data following the previous data that was output to the end.

This is data that has only been output halfway, and the comparison starts from the first byte of each data.

FIG. 5 is a time chart showing an example of the alignment process in the comparison unit 40-1 for two pieces of data each having a size of 4 bytes, in which 501 is a write process, 502 is a read process, and 503 is a read process.
indicates 4-byte data, 504 indicates a sorted data subset, and 505 indicates the state shown in FIG.

Generally, N pieces of data can be arranged using "log, LN+L・2rJJ11" by using N1 comparison units.
+rlogz N"1-L time processing yti text.

〔Effect of the invention〕

As explained above, in the present invention, by providing one comparison unit with two memories of the same configuration, one memory can contain only two data subsets at most, and
Since the data in the memory can be arranged in the order of input, memory management is easy, and since there are only two state transition branches at most, control is also easy. Furthermore, by copying data to two memories and reading data from two memories at the same time, comparison processing of one byte can be performed in two processes, writing and reading from memory, and there is no interruption in processing between data, so alignment is possible. It has the advantage of being short in time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a data sorting device according to the present invention, FIG. 2 is a diagram showing transition of processing states of a comparison unit in FIG. 1, and FIG. 3 is a timing diagram showing an example of processing according to the present invention. , FIG. 4 is a diagram showing detailed operation of the processing example in FIG. 3, FIG. 5 is a timing diagram showing another processing example according to the present invention, and FIG. 6 is a first configuration example of a conventional data alignment device. Figure 7 is a timing diagram showing the processing example in Figure 6, Figure 8 is a diagram showing the detailed operation of the processing example in Figure 7, and Figure 9 is a timing diagram showing the processing example in Figure 7. Diagram showing a configuration example, No. 10
This figure is a timing diagram showing the processing example of FIG. 9, and FIG. 11 is a diagram showing the detailed operation of the processing example of FIG. 10. 10... Data alignment device, 40-1 to 40-U.
...Comparison unit, 101...Data input terminal,
102...Data output terminal, 103, 104.
...Two 11-ri, 105-1, 105-2...
Read/write circuit, 106, 107... register, 108... comparator, 109... multiplexer, 110... control circuit. ” ti- to the sail
) t ÷ view )

Claims (1)

[Claims] (1) Multiple comparison units are connected in cascade, each comparison unit sorts and merges two sets of sorted data subsets input from the previous stage in parallel, and the sorted data subsets resulting from the merging are In a data sorting device that outputs data to a subsequent stage and rearranges the data set in descending order of data value or in descending order of data values, each comparison unit includes a pair of memories for storing sorted data subsets input from the preceding stage, and each memory. a pair of registers that store data read from the registers, a comparator that compares the data values of the registers, a multiplexer that outputs the data of either one of the registers to a subsequent stage, and a Based on this, the multiplexer is controlled, and the reading and writing of the memory is controlled, and the data input from the previous stage is copied and stored in the two memories, and while the data in one memory is being merged, a data subset is A data sorting device comprising: a control circuit that discards the copied data in the other memory when it runs out.