JPS63149726A - Comparing unit skip system for data aligning device - Google Patents

Abstract

PURPOSE:To obtain a data aligning device with simple constitution and simple control by utilizing a memory already formed in a comparing unit to skip the comparing unit. CONSTITUTION:In case of skipping a comparing unit 40-i, a previously fixed area in a memory 103 is used as a buffer, the address of the memory 103 and a multiplexer 109 in the comparing unit to be skipped are fixed prior to the start of alignment and inputted data are written in the memory and then read out to output it to the succeeding stage. Consequently, an exclusive by-pass line for skipping can be omitted and the skip processing can be attained only by two processing, i.e. reading and writing from/to the memory, so that control can be easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data sorting device that sorts data sets in ascending order of data values or in descending order of data values.

More specifically, it relates to the skip method of the comparison unit.

(Prior Art) A data sorting device generally consists of a plurality of comparison units connected in cascade, and each comparison unit aligns and merges two sets of sorted data subsets input from the previous stage in parallel. The sorted data subset resulting from the merging is output to a subsequent stage, and the data set is sorted in ascending order of data values or in descending order of data values.

In this type of data sorting device, in order to expand the data length that can be sorted, if data larger than the memory in the comparison unit is input, the comparison unit is skipped, or to improve processing speed. If the number of input data is smaller than the number of data that can be stored in the device, a method is used in which comparison units with no data stored are similarly skipped. For this reason, conventionally, a bypass data line was separately provided in the comparison unit, and in the case of the skip mode, data input from the previous stage was directly bypassed to the N subsequent stages through the bypass data line.

FIG. 3 shows an example of the configuration of a conventional data alignment device.

10 is a data alignment device, 20 is a data input terminal of the device 10, 30 is a data output terminal of the device 10,
40-1 to 40-U are comparison units, 101 is a data input terminal of the comparison unit, and 102 is a data output terminal of the comparison unit.

Each comparison unit 40-1 to 40-U has an input terminal 101
A memory 103 that stores one sorted data subset inputted from the memory 103, a memory 104 that stores the other sorted data subset input from the memory 103, and a continuation/IF integrated circuit 105-1 that reads and writes data to and from the memories 103 and 104, respectively. ,1
05-2, a register 106 that stores one word of data in the memory 103, a register 107 that stores one word of data in the memory 104, and a comparator 108 that compares the values of the data stored in registers 10B and 107. register 106
and 107 for selecting a route for transferring the data to the output terminal 102. Comparator 1
Comparison results have been received since 2008.

A control circuit 110 that controls each part of the comparison unit based on this. A multiplexer 112 for selecting the skip data line 111° 111 and the de, - evening line from the memory.
Consisting of The sizes of the memories 103 and 104 are 2 words in comparison unit 40-1 and kX in comparison unit 40-2.
2 words, kX4 words for comparison unit 40-3, and kX2u-1 words for comparison unit 40-U.

The operation modes of each comparison unit 40-1 to 40-U include:
There is a normal mode in which normal alignment is performed and a skip mode in which the comparison unit is skipped. In normal mode, data is read from memory 103 to register 106, data is read from memory 104 to register 107, and registers 106 and 107 are read. Comparator 108
The process of outputting the data to the output terminal 102 and writing the data input from the input terminal 101 to the memory 103 or 104 is repeated. In skip mode, data input from input terminal 101 is transferred to data line 1.
11 → multiplexer 112 → register 106 → multiplexer 109 → send to the next comparison unit through output terminal 102.

The processing of such a data sorting device is described in detail in, for example, Japanese Patent Application No. 60-96398.

[Problem that the invention seeks to solve]

In this way, in the conventional data sorting device, a dedicated data line 111 and a multiplexer 112 are added in order to skip a comparison unit, and furthermore, the comparison unit to be skipped has a processing pattern that is completely different from the normal processing mode. I need.

For this reason, there are disadvantages in that the amount of hardware increases and the control becomes complicated.

The purpose of the present invention is to: when skipping a comparison unit,
It is an object of the present invention to provide a data alignment device that is simpler in configuration and control than the conventional one by performing the operation without providing a dedicated line for bypass.

[Means and effects for solving the problem] The present invention provides a data sorting device consisting of a plurality of comparison units connected in cascade, in which memory already existing in the comparison unit is used as a buffer, and when the unit is skipped. ,
By writing the input data into the memory, reading it out as is, and outputting it to the next stage, a dedicated bypass line for skipping can be omitted.

[Example〕 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the difference from FIG. 3 is that the data line 111 for bypass and the multiplexer 112 are omitted. 1, the memory 103
The comparison unit to be skipped is stored in memory 1 before alignment starts.
Address 03 and multiplexer 109 are fixed.

FIG. 2 is a state transition diagram illustrating the control of the comparison unit to skip, in which 200 and 201 indicate states, and 202 indicates the direction of state transition. Each state consists of two processes, write and read, which are the same as when performing normal alignment.

In state 200, in the write process, a sorted data subset (1m) is input from the data input terminal 101,
The word is stored in a fixed address area of the memory 103 , and in a read process, one word is read from the fixed address area of the memory 103 and stored in the register 106 . This state 200 is a process performed only on the first word data input to the comparison unit to be skipped. When the processing in state 200 is completed, the process moves to state 201. In state 201, in a write process, the next data is input from the data input terminal 101 and stored in the same fixed address area of the memory 103, and at the same time, the data in the register 106 is transferred to the multiplexer 10.
9 to the output terminal 102, and in the read process, data is read from the fixed address area of the memory 103 and stored in the register 106, similar to state 200. This state 201 is repeated for data from the second word input to the comparison unit to be skipped.

〔Effect of the invention〕

As explained above, in the present invention, since the memory already existing in the comparison unit is used to skip the comparison unit, there is no increase in the amount of hardware due to the addition of the skip function, and the same processing as normal sorting processing is performed. Skip processing can be performed with two processes, reading and writing to the memory, so there is an advantage that control is easy.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a data alignment device according to the present invention, FIG. 2 is a state transition diagram for explaining the skip control in FIG. 1, and FIG. 3 is a configuration diagram of a conventional data alignment device. It is. DESCRIPTION OF SYMBOLS 10... Data alignment device, 20... Data input terminal of device 10, 30... Data output terminal of device 10, 40-1 to 40-U... Comparison unit, 101.
. . . Data input terminal of the comparison unit, 102 . . . Data output terminal of the comparison unit, 103. 104 . . . Memory. 106.107...Register, 108...Comparator, 109...Multiplexer, 110...Control circuit. Figure 2

Claims (1)

[Claims] (1) Multiple comparison units are connected in cascade, each comparison unit sorts and merges two sets of sorted data subsets input from the previous stage in parallel, and the sorted data subsets resulting from the merging are In a data sorting device that outputs data to a subsequent stage and sorts the data set in ascending or descending order of data values, when skipping a certain comparison unit, the memory for storing sorted data subsets in the comparison unit is used as a buffer. , a comparison unit skip method for a data alignment device, characterized in that data input from a previous stage is written into a memory, read out as is, and output to the next stage.