JPS61255169A - Horizontal drive pulse control circuit - Google Patents

Abstract

PURPOSE:To reduce remarkably jitter in a horizontal synchronizing circuit by detecting the phase of a flyback pulse with the high accuracy than the accuracy of a sampling clock so as to attain highly accurate phase information of the flyback pulse. CONSTITUTION:A synchronizing means 31 synchronizes a horizontal flyback pulse HFB by using a sampling clock phiS. Then a correction signal generating means 32 obtains a flyback phase correction signal FBDELTAtau being a difference between the phase of the synchronizing signal of the signal HFB and a pre scribed phase of the clock phiS. On the other hand, a horizontal drive means 34 uses the horizontal synchronizing signal to generate the horizontal drive pulse HD. The phase of the signal HD is controlled by a horizontal drive flyback pulse phase control signal DFB. The signal DFB is obtained by integrat ing the phase difference between the timing signal FBT synchronized with the period of the clock phiS and the horizontal synchronizing signal by a phase control means 33. Thus, the signal FB tau representing the phase information of the HFB in the finner unit than that of the period of the phiS is inputted to the phase control means 33 to correct the DFB thereby reducing the horizon tal jitter due to the HFB.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention is used in digital television receivers, and is a horizontal dry pulse control that emphasizes the phase relationship with horizontal fly pulses. Regarding circuits.

[Technical background of the invention]

Recently, due to advances in semiconductor technology, a Tezotal TV receiver has been developed that digitizes a paced video signal and performs various signal processing. Yong J! In order to achieve this, the frequency of the sampling clock is selected to be three or four times the color subcarrier frequency, and processing is performed to synchronize the sampling clock with the color burst signal. The wing aircraft is provided with means for adjusting the horizontal screen position, horizontal screen width, etc. using horizontal drive pulses. The horizontal drive pulse normally controls a horizontal oscillator with the output of an AFC circuit that synchronizes a horizontal synchronization signal and a horizontal flyback pulse,
It is created by waveform shaping the output of a horizontal oscillator. (Horizontal synchronization circuit) However, when viewed from a digital television receiver, the phase of the horizontal fly pulse is not particularly fixed with respect to the sampling clock.
In the case of a BC type digital television signal, the sampling clock has a frequency of about 14.3 Wms and a period of about 70 nwz. Digital television signals operate using the sampling clock as a basic clock. Therefore, if phase control is performed at the rate of the sampling clock in the horizontal synchronization circuit, s 70
ns@*o/ ivy will occur.

[Purpose of the invention]

This invention is based on the above circumstances 1cl! It was done by looking at
It is an object of the present invention to provide a horizontal dry f/4 pulse control circuit which can detect the phase of a flyback pulse with high precision and can significantly reduce jitter in a horizontal synchronization circuit.

[Summary of the invention]

For example, as shown in FIG.
The horizontal flyback pulse BiPB is synchronized with the sampling clock φ8. Next, the correction signal generating means 3
2, the phase of the synchronization signal of the flyback pulse m1 and! A flyback phase correction signal Flint is obtained which is the difference between the predetermined phase of the rotational torque El and φ8.

On the other hand, the horizontal t latch means 34 generates the horizontal P latch/fA-s HD using the horizontal synchronizing signal. Furthermore, the phase of horizontal drive/4 Lux HD is.

Horizontal drive fly-dimension pulse phase control signal DF
It is controlled by BK. The horizontal drive flyback pulse phase control signal DFB is obtained by integrating the phase difference between the timing r signal FBF synchronized with the cycle of the Sunburi driver φS and the horizontal synchronization signal using the phase control means 5syc. It has been obtained.

Therefore, a flyback phase correction signal FBΔτ is further inputted to this phase control means 33, which collects phase information of the flyback clock dJLl field 1 in h units finer than the period of the nutring clock φS, and Control signal D
By correcting FB, 7 rides Δ Lus II FB
Horizontal jitter caused by K can be reduced.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a digital horizontal synchronization circuit according to an embodiment of the present invention.
The digital converter 1111C converts the digital video signal DV8K using the sampling clock φS. In this embodiment, the frequency of the sampling quadrature φ8 is selected to be 1.04 times the color subcarrier frequency, and this clock is the basis of the entire system.The digital video signal DV51 is , the synchronization separation circuit 12 is supplied with the output clock phase detection circuit isI'C. The synchronization separation circuit 12 compares the levels of the digital high-speed signal Dv8 and the synchronization separation level SEP, and separates the synchronization signal. Then, a composite synchronization signal C8 is obtained. Composite synchronization signal CB is guided to horizontal synchronization detection circuit 14. The horizontal synchronization detection circuit 14 detects the pulse period and width of the composite synchronization signal, thereby obtaining a horizontal synchronization detection signal H8.

As explained in detail in Fig. 2 and Fig. 3, the inter-phase detection circuit IJ of the
The phase difference between φ8 and the rising edge of the horizontal synchronization detection signal H8 is detected to obtain a phase correction signal C8jτ.

The means for obtaining the nine-phase correction signal CBnot described above will be explained with reference to FIGS. 2 and 3.

In FIG. 2, the digital video signal Dv8 is shown in analog form for ease of understanding in FIG. What is actually obtained as a digital value is the part of the signal DV8 K marked with a black circle (sampling clock φ
Therefore, the rising edge of the composite synchronizing signal CB is synchronized with the rising edge of the RPCs and the rising edge of the composite synchronizing signal CB, and the horizontal synchronizing detection signal Ha detected from the composite synchronizing signal CB is also synchronized with the rising edge of the composite synchronizing signal CB. The phase is synchronized to the rising edge of the synchronization signal CS.

However, if the horizontal synchronization signal Ha rises at the 8 points shown in the figure, the time when the actual horizontal synchronization signal is synchronously separated and crosses the line sgp is 09, which is C8Δτ earlier than the point B shown in the figure. This is the point in time. By determining the above C8 τ, it is possible to detect the rising phase error of the horizontal synchronizing signal H8O with precision as fine as the period of the sampling clock φ8. Figure 3 shows the phase detection between sampling clocks that determines the above C8jτ as a phase correction signal. The separated level field point detection circuit JJJ, which shows the circuit IJ, obtains the team DM of the time point DM and the data DB of the time point B immediately before the rising edge detection time point B of the horizontal synchronization detection signal H8.

These data DA and DB are calculated by the phase calculation circuit 13.
2 is input. This arithmetic circuit 112 also uses the synchronization separation level SEP to perform the following arithmetic operation.

Here, the slope before and after the sync separation level of the video signal is
An approximation is made that it is constant. Through this calculation, a phase correction signal C8Δτ is obtained.

JIIE I II K M *? Theory'J t h
s, horizontal synchronization detection signal 11g, phase correction signal C8
τ is supplied to the horizontal phase error detection circuit IJ. The horizontal phase error detection circuit 15 forms a phase-locked loop with the horizontal loop filter J6 and the digitally controlled oscillator 1r, as detailed in Figure 4. The horizontal phase-locked loop with Horizontal counter output 11CTR') to horizontal synchronization signal,
The above-mentioned phase-locked loop will be explained with reference to FIG. 4.

The digitally controlled oscillator 11 is an all-digital oscillator whose oscillation period is controlled by the horizontal synchronization detection signal Ha, and is capable of highly accurate operation of 248 clocks or more. Digitally controlled oscillator JF has a horizontal counter 111. The horizontal counter 111 is reset by the horizontal counter reset signal R8, and counts the inputs φB.

The count output HCTR as a horizontal synchronization reproduction signal of the horizontal force sensor 111 is supplied to the -number construction circuit 122 and the latch circuit 1111flC in the horizontal phase error detection circuit 15.

The latch circuit 151 latches the horizontal count output H:rR using the previous horizontal synchronization detection signal HB, and supplies the value of 7 to the subtracter 152. The subtracter 152 is the latch circuit 15
The previous phase correction signal C8jτ is subtracted from the output value of 1. This corresponds to converting the phase of the horizontal synchronization detection signal Ha to the phase (value) of the horizontal counter output and subtracting the previous phase correction signal 08 no τ from this value.

The output of subtracter 152 is input to subtracter JJtJ.

The subtracter 153 further subtracts the output phase correction signal HCIτ of the horizontal counter 111 from the output value of the subtracter 151. This means that even if the count output phase of the horizontal counter 111 and the phase of the horizontal synchronization detection signal ll51 are in a predetermined phase relationship, true synchronization cannot be obtained if there is an error in the horizontal counter #111 itself. That's because there isn't.

Next, the output of the subtracter 153 is further supplied to a subtracter 154, where the horizontal counter target phase value Href is subtracted. In other words, the horizontal synchronization detection signal HB and the horizontal counter I'
If the output phase of ll has a predetermined relationship, the output value of the subtracter 154 can be calculated in advance. Therefore, by subtracting the horizontal counter target phase value Href from the output value of the subtracter 153 in the subtracter 154, the error between the target phase values Hr and f can be obtained.

The output of the subtracter 154 is supplied to the phosphor circuit x'ss. The ζtuter circuit 155 limits signals with large errors from the subtracter 154. This limiting circuit 155 is
The data circuit 155 works effectively to maintain stable operation of the circuit when the horizontal synchronization detection signal H8 is erroneously detected.
The output of is supplied to the loop filter 16.

The loop filter 16 determines the stability, convergence time, etc. of the feedback loop system. , the coefficients are multiplied by the coefficient multiplier 165. Coefficients a and b set the loop filter 160 time constant. The output of the coefficient multiplier 161 is integrated by an integrating circuit composed of an adder 162 and a latch circuit 163. The integral output is the adder 16411C
Then, it is added to the output of the coefficient multiplier 11111.

The output of the loop filter 16 is the horizontal periodic signal CH, which is the water-column periodic signal C1i that provides the oscillation period of the digitally controlled oscillator 11.

The horizontal periodic signal CH is divided into an integer component CHI (higher bits) and a decimal component CH2 (lower bits).
j is adder 1141f: 2I-integer component CH
I indicates the oscillation period in units of clock φS, and the decimal component C
HI means the oscillation period within one period of the φS.

Adder 1'13fIC performs addition of the integer component CHI and the horizontal indicator period value. Before, adder 114
constitutes an integrating circuit together with the latch circuit srs. Then, the carry C1ff of the adder 11- is added to the adder JFJ.

Now, the horizontal counter 171 counts four times φ8 in one horizontal period.
It is assumed that 910 are counted. Now, assuming that no phase error occurs at any location, the horizontal periodic signal CM is all 0's.

Here, if 910 is set as the horizontal indicator period value, the coincidence pulse R is output from the -scattering product output circuit 112 when the horizontal counter 111 counts 910 times
8 is obtained. This coincidence pulse R8 is the horizontal counter 1
21 is used as a reset signal and a signal for the child circuit 115.

Now, suppose that a phase shift of 48 minutes occurs in 4 horizontal periods, then as a decimal integral CHI, φ
Data for 0.25 minutes of SII period is available. This data is accumulated in the integrating circuit, becomes the first "at 4X0.25 (4 horizontal periods), and is input to the adder its as a carry. Therefore, at this time, the horizontal counter 111 is
When counting 910+1, it is reset by the coincidence pulse R8. Since the output of the latch circuit 175 is also fed to the horizontal phase error detection circuit 150 and the subtracter IS3, the above Rude performs phase correction as if one cycle of the clock φS was further broken down. . As mentioned above, the output of the child circuit 115 is the horizontal counter correction signal HCIτ.

The explanation will be returned to FIG. 1. The above circuit is first
The phase error of the horizontal synchronization detection signal H8 that exists due to the φ80 sampler cycle is obtained, and the phase of the horizontal count output is further corrected with an accuracy higher than the cycle of the clock φS.Furthermore, the phase of the horizontal count output is Correction can be made so that the PITEO signal has a predetermined phase with respect to the horizontal synchronization signal.

The above-mentioned horizontal counter correction signal HCnoτ and horizontal count output HCTR are supplied to the horizontal drive circuit 21, the fly 4
．． The phase error detection circuit 19fC is supplied to the phase error detection circuit 19fC.

The flyback phase error detection circuit 19 is used to set the phase relationship between the flyback pulse HFB of the television receiver and the horizontal synchronization signal to a predetermined phase. 1 of φS
The phase within the period is detected. This detection circuit is a Sandel-Indack interlock phase detection circuit 18.

The phase error detection circuit 18 supplies a phase correction signal FBΔT and a timing pulse FBT for reading this signal to the phase error detection circuit JjK. Fly d9-phase error detection circuit 19
is horizontal counter output HCTR and timing I4sisF
The phase difference information with BT (synchronized with the sampling clock) is detected, and then the flyback phase correction signal n
The phase difference information is corrected using lτ and the horizontal counter correction signal HCΔτ. Furthermore, the phase difference information corrected in this way is corrected by the horizontal screen position control signal 1 [PH. Horizontal image position information (1) is a signal given from the outside to the operator in order to adjust the screen position according to the characteristics of the receiver and according to the user's preferences.

The above flyback phase error detection circuit 1# is based on the flyback phase error detection circuit 1#.
A phase error signal ER2 is obtained. This signal I R-J
Fi, fly d, horizontal drive fly via croup filter 20 4. The signal is taken out as the Δ pulse phase control signal DFB and supplied to the horizontal serial generation circuit 21. Horizontal drive generation circuit 11Fi, horizontal drive 41 width kakunta explained in FIG. 7, and horizontal drive f@control signal H
It has a comparator that compares the horizontal P
Get D. In this case, horizontal? The phase of the live pulse HD has a phase relationship with the horizontal counter 111 (shown in FIG. 4),
and the flyback pulse HFB have a predetermined phase relationship. ζThe horizontal counter 171 has its phase relationship with the horizontal synchronizing signal corrected to a predetermined relationship, and
Sampling clock φ of flyback ΔRus IIFB
Phase information within one cycle of B is also obtained. Therefore, the horizontal dry fA pulse HD can obtain phase control with an accuracy of clock -8 or higher.

The above-mentioned configurations of the reverse phase detection circuit JJl, the flyback phase error detection circuit 1t, the loop fill 70, and the horizontal drive generation circuit XXO will be explained in more detail.

The gs diagram shows the black and white phase detection circuit 18.
．． FIG. 6 is a time chart for explaining the operation.

The fly d and r d pulses IffB are supplied to an r-) delay circuit 182 via an input terminal 181. r-t delay circuit 1szlds Sampling circuit 16
It is a series circuit of f-) delay elements. Therefore, each P-
) Delay element output IJ ~dJtij, fa6 Figure Vc shows! To 5? 1/1 of one period of φ8
The outputs d1 to 47g are shifted by 6 periods - the sampling clock φS
It is supplied to the child circuit iss, which is latched by the rising sand. The child circuit 188 has outputs corresponding to d1 to 416.
1 to 16, only the output 1 is supplied to the latch circuit 184, and the other outputs 02 to 1# are supplied to the latch circuit 185.
supplied to The latch circuits 114#i and ml are turned on at the rising edge of the sampling resistor φS, and their outputs are supplied to the clock input terminal of the latch circuit 185. Also,
The output of the latch circuit 184 is used as a reading timing signal FB'l' for the fly-dock phase correction signal FBjτ. U, the outputs f2 to 11g of the child circuit 185 are
It is supplied to a counting circuit 186. This counting circuit 186 is
The first m of the outputs f2 to tie is counted, and the value is output as the flyback phase correction signal FBnot.

Now, as shown in FIG. 6, at the rising time t61 of the sample printer φS, the fly d.

Assume that the phase information of the d Lus HFB is erased.

However, since the actual fly d and phase FB'l' rises at time t60, which is earlier than the time tel, FBΔf in the figure corresponds to the fly d and phase correction amount. Therefore, by counting the number of ``l'' in the latch circuit 185, the zero phase correction amount signal FBjf, which can be obtained by taking the deviation as the phase correction signal, can be calculated as follows:
Since it is necessary to read out within the cycle, the timing pulse FBT is configured to rise at the fall time t62 of the sampling clock φ8.

FIG. 7 shows the flyback phase error detection circuit 19, the loop filter 20, and the horizontal driver 41 generation circuit 21.

The count output HCTR from the horizontal counter 111 in the horizontal phase error detection circuit 15 is input to the latch circuit 191 as the previous timing pulse FBT.

It is latched at the rising edge. As a result, horizontal count output HCTR and phase information of timing pulse FBT are obtained. The output of the latch circuit 191 is the subtracter 192
supplied to 0 in the subtracter 192, latch circuit 191
The phase correction signal FB and f are subtracted from the output of . Further, the output of the subtracter 192 is supplied to a subtracter 19J, where the horizontal color 221110 phase correction signal H
CΔτ is subtracted. As a result, phase information can be corrected in units smaller than one cycle of the sampling clock φS. Further, the output of the subtracter 192 is transmitted to the subtracter 194.
The error between the horizontal screen position control signal HPH and the horizontal screen position control signal HPH is calculated. The output of the subtracter 194 is fed to a limiter 195 to limit large errors and is derived as a flyback phase error signal 'pans.

The fly d and the phase error signal IRj are passed through the loop filter 2.
A coefficient C is multiplied by a coefficient C of 0 in a coefficient multiplier 201, and the resulting signal is integrated by an integrating circuit composed of an adder 202 and a latch circuit 20B. The integrated output is then supplied to the subtracter 211 of the horizontal drive generation circuit 21 as the horizontal drive fly-dock pulse interphase control signal DFB.

The horizontal drive generation circuit 21 maintains a predetermined phase relationship between the fly d pulse and the horizontal r lie f pulse HD in which a phase error is detected as described above.

Phase control signal DFB is input to subtracter 211. The horizontal screen position control signal HPH is supplied to the subtraction allK. The subtracter 211 outputs a signal from the horizontal drive flyper to the horizontal screen position control signal EPH.
The inter-pulse phase control signal DPB is subtracted, and the rising phase of the horizontal dry f/4 pulse is determined. Subtractor 21
1, the delay of the fly pulse is corrected.

Next, the output of the subtracter 211 is supplied to an adder 212 and added to the horizontal counter phase correction signal HCΔτ. The slippage is corrected with a precision finer than one period of φS using the sampling dacro before comparison is made with the horizontal counter output HCT1 in units of φS, and as a result, the horizontal counter output HCT1 is corrected with an accuracy finer than one period of φS. This is to improve the accuracy of live pulse HD.

The integer portion CFJ of the upper pits of the output of the adder 211 is supplied to the coincidence circuit 213, and the decimal portion CFj of the lower pits is given to the selection circuit 211 as a control signal. In the coincidence circuit 213Vc, when the integer CFI and the horizontal count output HCTR match, the output pulse R8J is set.
is obtained, and this pulse R8J inverts the horizontal drive width counter 214 by seven times.

When the horizontal drive width counter 214 is reset or reset, it raises the drive pulse HDS in units of φS and counts -8 clocks.

This count value is compared in comparator 215 with the horizontal drive width control signal. Comparator 215 detects horizontal drive width counter 2 rather than horizontal drive width control signal HPW.
When the value of the output No. 14 becomes large, the drive pulse HDB is made to fall.

Drive pulse 11DB is P-) delay circuit 11g
supplied to This e-) delay circuit 215
It has the same configuration as the r-) delay circuit 182 shown in the figure, and obtains a plurality of drive pulses having a phase accuracy finer than the period of one clock φS. Any one of the plurality of drive pulses is selected by the selection circuit 211 and output as a true horizontal drive pulse HD. The selection circuit 217 selects the fractional component CF from the adder 212.
A selection pulse is determined according to J. The horizontal drive pulse HD is controlled to a phase with finer precision than the period of the sampling clock φS.

The horizontal flyper, the phase error detection circuit 19, the flyback pulse Rude filter 20, and the horizontal drive generation circuit 21 convert the rising phase of the horizontal flyback pulse field 1 into the horizontal flyback pulse field 111, as shown in figure flIc8. It works to match the value to the time point t81 when the value of the horizontal screen position control signal HPH coincides with the value of the horizontal screen position control signal HPH.For this purpose, the time from when the horizontal drive pulse HD is generated until the horizontal fly d and the horizontal fly Δ pulse HyB are obtained. Delay information, or DFB
is obtained by the phase error detection circuit 19 and the loop filter 20. In this case, the phase of the timing information obtained from the fly/threat pulse is subjected to a finer phase correction than that of black and riφS, and the phase of the timing information obtained from the count output of the horizontal counter 111 is also finer than that of black and riφS. Phase correction has been made. Then, the phase of the horizontal drive pulse HD is determined with high accuracy based on the horizontal r live fly-guard phase control signal DFB.

FIG. 9 shows the circuit of FIG. 7 further divided into blocks. As shown in FIG. 9, the synchronization means 31 synchronizes the horizontal fly d and the horizontal Δrus HFB with the sampling clock φS, and the correction signal generating means 32 synchronizes the horizontal fly d and the Δrus HFB with the sampling clock φS. fly d, which is the difference between the phase of the synchronization signal and the predetermined phase of the sampler φS;

Then, a phase correction signal FBΔτ is obtained.

On the other hand, the horizontal P live means 34 generates the horizontal drive pulse HD using the horizontal synchronization signal. Furthermore, is the phase of the horizontal drive pulse IiD horizontal? It is controlled by a live flyback pulse phase control signal DFB. Horizontal drive fly d, ri drus phase control signal DFB is:
It is obtained by integrating the phase difference between the inverter signal ymy synchronized with the period of the sampling clock signal S and the horizontal synchronizing signal in the phase control means 3a. , input the phase information of the flyback pulse HFH in layer units finer than the period of the sampler φS → input the phase correction signal FBΔτ, and input the phase control signal DFB
By correcting this, it is possible to reduce the horizontal jitter caused by fly d and ruth HFB.

〔Effect of the invention〕

As explained above, according to the present invention, the phase of the fly-d and r-d pulses is detected with higher accuracy than the accuracy of the sampling clock, and the phase information of the flyback pulse is made highly accurate. Horizontal phase of? It's fun to get live Luz.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, FIG. 2 is an operational waveform diagram for obtaining a horizontal synchronization correction signal, and FIG. 3 is a detailed diagram of the inter-clock phase detection circuit of FIG. 1. Figure 4 shows the horizontal synchronization reproduction signal generation section in Figure 111 in more detail, and Figure 5 shows the fly/blue clock in Figure 1.
Figure 6 shows the operating waveforms of the circuit in Figure 5, and Figure 7 shows the horizontal phase detection circuit in Figure 1. FIG. 8 is a waveform diagram showing the operation of the circuit of FIG. 1, and FIG. 9 is a diagram showing the circuit of FIG. 7 as an fvx block. 11.-Ana is da digital converter, Jj-..Synchronization separation circuit, 13..-Sampling clock phase detection circuit, 14.-Horizontal synchronization detection circuit, 15..-Horizontal phase error detection circuit, 2g-・・Horizontal loop filter, 11-digital control oscillator, Jj-・sampler dacro, inter-phase detection circuit, 19-・fly d, ri phase error detection circuit, JO-・flyback loop filter, 21・-horizontal Drive generation circuit / Patent attorney Takehiko Suzue Figure 2 Figure 3 t60 t61 t62 Figure 6

Claims (2)

[Claims] (1) In a digital television system that operates using a sampling clock as a basic clock, horizontal means for obtaining a drive/flyback pulse phase control signal; horizontal drive generation means for controlling the output timing of the horizontal drive pulse by the horizontal drive/flyback pulse phase control; and the flyback pulse and the sampling clock. means for obtaining a synchronization signal of the horizontal flyback pulse in a period shorter than the sampling clock cycle; and obtaining a horizontal flyback phase correction signal that is the difference between the synchronization signal and a predetermined phase of the sampling clock. , and means for correcting the phase control signal. (2) The means for obtaining the flyback phase correction signal includes a delay circuit that receives the flyback pulse with a plurality of delay elements to generate a delayed signal train, and a delay circuit that latches the delayed signal train at a predetermined phase of the sampling clock. a second latch circuit that latches one of the latch signals of the first latch circuit when the sampling clock is inverted to obtain the timing signal; 2. The horizontal drive pulse control circuit according to claim 1, further comprising counting means for counting 0 or 1 among the output signals and using that value as the flyback phase correction signal.