JPH0810904B2 - Digital synchronization circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a digital synchronizing circuit used as a horizontal synchronizing circuit of a digital television receiver.

[Technical Background of the Invention] With recent advances in semiconductor technology, television receivers for digitizing signal processing after a video signal have been put to practical use also in home television receivers. In this digital television receiver, the frequency of the sampling clock is often selected to be four times the color subcarrier frequency in order to facilitate color demodulation, and the phase is often synchronized with the color burst signal. In the case of NTSC signals, this sampling clock frequency is about 14.3 MHz and the period is 70 nsec. A digital television operates with this sampling clock as the basic clock of the system, but in the horizontal synchronizing circuit, even a jitter of 70nesc for one clock of this basic clock has a great adverse effect on the screen. For this reason, there is a demand for a horizontal synchronizing circuit which performs phase detection in the horizontal synchronizing circuit and the operation of the horizontal drive pulse generating section with high accuracy higher than the basic clock and has less jitter.

[Object of the Invention] The present invention has been made in view of the above circumstances, and it is possible to operate a digital horizontal synchronizing circuit with accuracy higher than the basic clock of the system, to reduce jitter in synchronous reproduction, and to integrate it. It is an object of the present invention to provide a digital synchronization circuit suitable for.

SUMMARY OF THE INVENTION The present invention uses a delay element in detecting phase error information between a synchronizing signal used in a synchronizing circuit as shown in FIG. 1 and a sampling clock which is the basis of the system. When the detection is performed, the offset of the delay element itself is detected by the monitor, and the detection information can be used to obtain the synchronization signal phase correction with higher accuracy.

Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings.

The input terminal 11 shown in FIG.
S is provided and this signal is converted in an analog-to-digital converter 12 into a digital video signal DVS. In the analog-digital converter 12, the sampling clock φ
s is used and is selected to be four times the color subcarrier frequency in this embodiment. Also, this sampling clock φs is
It is the basic clock for the entire system. The digital video signal DVS is supplied to the sync separation circuit 14 and the horizontal-clock phase detection circuit 19.

The sync separation circuit 14 compares the digital video signal DVS and the sync separation level sep to separate the sync signal, and outputs a composite sync signal CS. The horizontal sync detection circuit 17 to which the composite sync signal CS is supplied separates the horizontal sync detection signal HS and supplies it to the horizontal-clock phase detection circuit 19 and the horizontal phase error detection circuit 24. Horizontal-clock phase detection circuit 19,
When the horizontal sync detection signal HS is obtained, a predetermined calculation is performed from the values of the digital video signal DVS and the sync separation level SEP to detect the phase component of the horizontal sync signal within the sampling clock cycle, and this is used as the phase correction signal CSΔτ. Output. (The means for obtaining this phase correction signal CSΔτ will be described with reference to FIGS. 2 and 3).

The digitally controlled oscillator 21 has a horizontal counter output signal HCTR.
And a horizontal counter correction signal HCΔτ is generated. The horizontal phase error detection circuit 24 has a horizontal synchronization detection signal HS and a phase correction signal.
Inputting CSΔτ, the horizontal counter output signal HCTR and the horizontal counter correction signal HCΔτ, the detected horizontal synchronizing signal and the output of the digitally controlled oscillator are compared in phase to generate a horizontal phase error signal HSER. The horizontal phase error signal HSER is guided to the horizontal loop filter 26. Horizontal loop filter 26
Is to give a time constant to this control so that the feedback loop control is stably performed.
Is output. Horizontal period signal HSPS is a digitally controlled oscillator
Introduced in 21 to control the period of the oscillator. Horizontal period signal
The HSPS is supplied to the digitally controlled oscillator 21 and controls the oscillation cycle. (This loop will be described in detail in FIG. 4). The above control loop is a digitally controlled oscillator21
The output signal of operates so as to have a predetermined phase with respect to the horizontal synchronizing signal of the digital video signal, and in this case, by the synchronization correction using the phase correction signal CSΔτ, the offset of the horizontal counter itself inside the digital control oscillator 21 The deviation is also corrected by the horizontal counter correction signal HCΔτ.

The flyback-clock phase detection circuit 28 receives a horizontal flyback pulse HFB whose phase relationship with the sampling clock φs is not fixed, and comprises a phase component of the flyback pulse HFB with respect to the sampling clock φs by an inverter gate. A gate delay element is used for detection to obtain a signal FBT in which the flyback pulse HFB is synchronized with the sampling clock φs and a phase component FBΔτ with respect to the sampling clock φs.
(The specific configuration of the flyback-clock phase detection circuit 28 will be described with reference to FIG. 5).

The gate delay monitor circuit 32 monitors the relationship between the gate delay element output and the sampling clock φs period,
Delay amount monitor signal indicating whether or not the delay amount is a predetermined amount
Output GDN. The structure of the gate delay monitor circuit 32 will be described with reference to FIG.

The delay-clock unit correction circuit 34 unit-corrects the phase component FBΔτ that is represented by the number of stages of the gate delay so as to be a small number when the clock φs cycle is set to 1 by the delay amount monitor signal GDN, and The back phase correction signal FBΔτ1 is output. That is, if the preceding delay amount monitor signal GDN is different from the predetermined amount, the phase component FBΔτ that is represented by the number of stages of the gate delay also has a deviation due to the delay element. Correction is performed.

The flyback phase error detection circuit 36 uses the horizontal counter output signal HCTR and the horizontal counter correction signal HCΔτ as a reference, and a horizontal screen position control device HPH and a flyback pulse HFB.
And a phase error between the flyback phase correction signal FBΔτ1 and the flyback phase error signal FPER.
The flyback loop filter 39 gives a time constant to the flyback phase error signal FPER and generates a horizontal drive-flyback pulse phase control signal DFB. The horizontal drive phase generation circuit 41 uses the horizontal counter output signal HCTR and the horizontal counter correction signal HCΔτ as a reference, and according to the horizontal screen position control device HPH and the horizontal drive-flyback pulse phase control signal DFB, the horizontal drive rising timing signal H
Generates DH and horizontal drive-clock phase correction signal HDCR. This horizontal drive-clock phase correction signal HDCR
Is supplied to the clock-delay unit correction circuit 44.
The clock-delay unit correction circuit 44 converts the horizontal drive-clock phase correction signal HDCR, which is represented by a decimal fraction with the sampling clock cycle as 1, into the number of stages of gate delay, and outputs the horizontal drive-clock phase signal. HD
Get CR1. The horizontal drive pulse generation circuit 46 generates a horizontal drive pulse HD in the phase indicated by the horizontal drive rise timing signal HDH in clock units and the horizontal drive-clock phase signal HDCR1 and in the width indicated by the horizontal amplitude control signal HPW. .

 The main circuit portion of FIG. 1 will be described in more detail below.

FIG. 2 shows the rising portion of the horizontal synchronizing signal.
The digital video signal DVS is shown in analog form. Here, only the value B of the rising portion of the sampling clock φs is actually obtained as the value of the digital video signal DVS. Therefore, the composite sync signal CS rises in synchronization with the sampling clock φs, and the horizontal sync detection signal HS detected from the composite sync signal CS is also obtained in the same phase. However, the time at which the video signal actually seems to have crossed the sync separation level SEP is CSΔτ earlier than this.
The accuracy is improved by detecting this CSΔτ and correcting the phase detection of the horizontal synchronizing signal.

FIG. 3 shows a horizontal-clock phase detection circuit 19 for detecting the above CSΔτ. Separation level cross point detection circuit 50
When the horizontal sync detection signal HS is detected, outputs a value immediately before the sync separation level is crossed from the digital video signal DVS as A and a value immediately after that as B. The inter-clock phase operation circuit 53 performs the following operation using the signals A and B and the sync separation level SEP.

CSΔτ = (B-SEP) / (B-A) Here, it is approximated that the slope before and after the sync separation level of the video signal is constant, and this calculation results in a phase of a small number when the clock cycle is 1. The phase correction signal CSΔτ can be obtained as a component.

FIG. 4 shows blocks of the digitally controlled oscillator 21, the horizontal phase error detection circuit 24 and the horizontal loop filter 26 of FIG. The digitally controlled oscillator 21 has a horizontal cycle signal HSPS.
Is an all-digital oscillator in which the oscillation cycle is controlled by. The horizontal cycle signal HSPS is divided into a cycle integer (upper bit) 271 in clock units and a cycle fraction (lower bits) 272 less than a clock unit. The fractional period 272 is supplied to the integration circuit configured by the adder 101 and the latch circuit 102. The carry output 103 of the adder 101 is supplied to the carry input of the adder 104. The adder 104 adds the period integer 271, the horizontal standard period value 105, and the carry output 103. The horizontal standard cycle value 105 is set to be the cycle of a standard video signal when the horizontal cycle signal HSPS is zero. The output 106 of the adder 104 is matched with the horizontal counter output signal HCTR in the match detection circuit 107 to generate a horizontal counter reset signal 108. The horizontal counter reset signal 108 resets the horizontal counter 109 and simultaneously supplies a clock to the above-mentioned latch circuit 102. For example, if the value of the fractional period 272 is 0.25, the carry output of the adder 101
103 becomes "1" once every four horizontal cycles, and corrects the horizontal cycle with the clock φS as the basic clock by one clock. Then, the horizontal counter correction signal HCΔτ output from the latch circuit 102
Indicates an error component of the horizontal counter output signal HCRT that is less than the clock φS cycle.

The horizontal phase error detection circuit 24 has a horizontal counter output signal.
The HCTR, the horizontal counter correction signal HCΔτ, the horizontal synchronization detection signal HS from the horizontal-clock phase detection circuit 19, and the phase correction signal CSΔτ are supplied. The horizontal phase error detection circuit 24 obtains the phase error between the horizontal synchronization detection signal HS detected by the horizontal synchronization detection circuit 17 and the digitally controlled oscillator 21 with high accuracy and outputs the horizontal counter output signal H of the horizontal counter 109.
The CTR phase is controlled with higher precision than the clock cycle. The latch circuit 110 uses the horizontal sync detection signal HS
When is generated, the value of the horizontal counter output signal HCTR is latched. The output 111 of the latch circuit 110 is supplied to the subtractor 112, and the phase correction signal CSΔτ is subtracted. The result is further supplied to the subtractor 113 and subtracted from the horizontal counter correction signal HCΔτ. Therefore, the detection time of the horizontal synchronization detection signal HS is replaced with the value of the horizontal counter output signal, and the phase error between the detection time and the horizontal counter 109 itself is corrected within less than the clock φS cycle. The output of subtractor 113 is subtracter 1
14 and the horizontal counter target phase Href is subtracted. The output 116 of the subtractor 114 is supplied to the limiter 117, the signal having a large error is limited, and the output 116 is supplied to the loop filter 26 as the horizontal phase error signal HSER.

The loop filter 26 determines the stability of the feedback loop system, the convergence time, and the like. In this embodiment, the input horizontal phase error signal HSER is multiplied by the coefficient a in the coefficient multiplier 118 and integrated by the adder 119 and the latch circuit 120, and the horizontal phase error signal HSER is calculated in the coefficient multiplier 121. The value obtained by multiplying the coefficient b is added by the adder 122. The output 123 of the adder 122 is supplied to the digitally controlled oscillator 21 as a horizontal synchronization signal HSPS via the limiter 124. The limiter 124 is for limiting the horizontal cycle signal HSPS to a level within the corresponding range of the oscillation cycle of the digitally controlled oscillator 21.

As a result of the above feedback loop control, the output of the digital oscillator is set to the horizontal counter target value Hr
The horizontal sync detection signal HS comes to be located at the phase that is ef.

FIG. 5 shows a concrete circuit of the flyback-clock phase detection circuit 28 of FIG. Flyback pulse
The HFB is supplied to the gate delay circuit 200. The gate delay circuit 200 is configured by connecting 28 gate delay elements of an inverter in series. This is because the maximum number of gate delay stages corresponding to the clock cycle is 28 in this embodiment. The unit delay amount of this gate delay element may change due to element variation, temperature change, etc. when considering integration, but here one gate delay is 1/20 of the clock φS period. think of. The latch circuit 202 latches the gate delay outputs d1 to d28 at the rising timing of the clock φS. And 1
The latch output of the output d1 of the gate delay element is derived as a signal FBT in which the flyback pulse HFB is synchronized with the sampling clock φs. This signal FBT is further supplied to the latch circuit 203 and latched by the inverted signal of the clock φs. The output 204 of the latch circuit 203 is used as the latch pulse of the latch circuit 205. The 27-bit content of the latch circuit 205 is supplied to the counting circuit 206. The counting circuit 206 counts the number of 1s in 27 bits, and outputs the result as flyback-clock phase information in gate delay units, that is, the phase component FBΔτ for the clock φs, that is, the FBT synchronized with φs is the actual flyback. Pulse H
It is output as information that shows how much it deviates from FB.
FIG. 6 shows an example of a timing chart of the flyback-clock phase detection circuit 28. Flyback pulse HFB
Is detected with reference to the first gate delay output d1. In the illustrated example, the gate delay output d11 is "1", which is the delay information for the clock φS of the flyback pulse HFB. That is, the phase component FBΔτ for the clock φs is 10 unit gates. (Truncation less than unit gate delay). In this way, the flyback pulse HFB is divided into the signal FBT synchronized with the clock φs and the phase component FBΔτ indicating the deviation with respect to the clock φs.

Next, regarding the gate delay monitor circuit 32 of FIG.
This will be described with reference to FIGS. 7, 8 and 9. FIG. 7 shows a circuit block of the gate delay monitor circuit 32. The gate delay circuit 300 is composed of, for example, 31 gate delay elements, is arranged near other gate delay circuits when integrated, and is designed so that the difference in mutual delay amount can be ignored. A sampling clock φs is used as an input of the gate delay circuit 300, and outputs d1 to d31 of each gate delay element are supplied to the latch circuit 301. The latch circuit 301 latches the outputs d1 to d31 of each gate delay element by the timing signal 303 from the timing generation circuit 302, and supplies the output to the parallel shift register 308. FIG. 8 shows that the outputs d1 to d31 of the gate delay element are latched by the timing signal 303. The rising phase of the timing signal 303 is designed to allow a phase shift of about ± 2 gate delays around the phase shown in FIG. In the example of the timing chart of FIG. 8, 20 stages of gate delay correspond to one cycle of the clock φs, and the value of the output of the latch circuit 301 is “1100000” from the left.
000001111111111000000000 ". Next, using this data, it is detected how many gate delays the period of the clock φs corresponds to. The counter 304 in FIG.
Is a 6-bit counter that uses the clock φs as a clock. The timing generation circuit 302 generates timing signals 303, 306, 307 according to the counter output 305 as shown in the timing chart of FIG. The timing signal 306 is used as a load pulse of the parallel shift register 308, and the timing signal 307 is used as a clock. The parallel shift register 308 converts a 32-bit parallel input into a serial output, and supplies this output 309 to the first falling detection circuit 311 and the second falling detection circuit 311.

The first fall detection circuit 310 latches the contents of the counter 304 at the time of the first fall of the output 309. Second
The fall detection circuit 311 latches the contents of the counter 304 at the time of the second fall of the output 309. The latch outputs of the first and second fall detection circuits 310 and 311 are subtractors 31
2 is supplied and the difference is calculated. In the example of FIG. 9, the content of the first fall detection circuit 310 is “010010” (18 in decimal), and the content of the second fall detection circuit 311 is “100110”.
(38 in decimal). Therefore, the output 313 of the subtractor 312
Becomes 20 in this case, which is the same as the number of gate delay stages corresponding to the clock φs period. When this value is different from the predetermined value, it means that the delay amount of the delay element is offset, and it can be considered that a similar offset occurs in the other gate delay circuits. So this output 313
Is latched by the latch circuit 314 at the timing of the timing signal 315 and used as the delay amount monitor signal GDN. In this way, the gate delay amount corresponding to the clock φs cycle is constantly monitored.

FIG. 10 is a delay-clock unit correction circuit of FIG.
34, flyback phase error detection circuit 36, flyback loop filter 40, horizontal drive phase generation circuit 41, clock-delay unit correction circuit 44, and horizontal drive generation circuit
The structure of 46 is shown in more detail.

In this circuit loop, the phase of the horizontal drive pulse is controlled so that the rising phase of the horizontal flyback pulse HFB matches the horizontal screen position control signal HPH, and the width of the horizontal drive pulse is changed to the horizontal drive pulse width control signal.
Controlled according to HPW. FIG. 11 shows a timing chart of each part when the above circuit operates. The phase component FBΔτ in the gate delay unit is divided by the delay amount monitor signal GDN in the divider 400, converted into a fractional value in the clock unit, and output as the flyback phase correction signal FBΔτ1. Flyback phase error detection circuit Supplied to 36. In the divider 400, the number of stages (delay amount) of the gate delay represented by the phase component FBΔτ is normalized to the clock φs cycle. In this processing path, the operation bit string of the sampling clock φs in a cycle unit is assigned as an integer, and the operation bit string in a unit smaller than one period is assigned as a decimal.

Now, when the delay amount of one gate delay element is Δt and the clock φs period is Ts, the delay amount monitor signal GDN
Has a relationship of GDN = Ts / Δt, and when GDN becomes smaller,
This means that the delay amount of the delay element has increased, and that the increase of GDN means that the delay amount of the delay element has decreased.

Therefore, when FBΔτ1 = FBΔτ / GDN = FBΔτ × Δt / Ts is calculated, the change in φs due to the change in the delay amount of the delay element is given to FBΔτ. Since the amount of delay increases as GND decreases, FBΔτ1 also increases and the amount of correction also increases, and conversely GDN.
Is larger, the delay amount is smaller, so
FBΔτ1 also decreases and the amount of correction changes.

Latch circuit 401 of flyback phase error detection circuit 36
Latches the horizontal counter output signal HCTR at the timing of the signal FBT synchronized with the flyback pulse and outputs the signal FB
Take the timing of T as the count value of the horizontal counter. However, the flyback phase correction signal FBΔ
τ1 and the horizontal counter correction signal HCΔτ are not taken into consideration. Therefore, the subtractor 40 is output from the output 402 of the latch circuit 401.
The flyback phase correction signal FBΔτ1 is subtracted at 3 and the horizontal counter correction signal HCΔτ is subtracted at the subtractor 404.
Further, from the result, the horizontal screen position control signal HPH is subtracted by the subtractor 405. As a result, the phase relationship between the horizontal flyback pulse HFB and the horizontal screen position control signal HPH is required to be finer than the clock φs cycle and accurate with the offset of the gate delay amount.
The output of the subtractor 405 is derived as the flyback phase error signal FPER via the limiter 406 and supplied to the coefficient multiplier 407 of the flyback loop filter 39. Coefficient multiplier 407
Then, the coefficient c is multiplied, and the resulting signal is integrated by the adder 408 and the latch circuit 409, and is derived as the horizontal drive-flyback pulse phase control signal DFB. The horizontal drive-flyback pulse phase control signal DFB is subtracted from the horizontal screen position control signal HPH in the subtractor 410,
The horizontal counter correction signal HCΔτ is added to the result in the adder 411. Therefore, if the horizontal drive-flyback pulse phase control signal DFB is zero, the horizontal counter correction signal HCΔτ is added to the horizontal screen position control signal HPH, and the phase shift amount of the horizontal counter is corrected. Become. The output of the adder 411 indicates the phase for generating the horizontal drive pulse HD, the upper bit integer 412 is supplied to the match detection circuit 413, and the lower bit fraction is the horizontal drive-clock phase correction signal.
It is supplied to the multiplier 420 which constitutes the clock-delay unit correction circuit 44 as HDCR.

The coincidence detection circuit 413 receives the horizontal counter output signal HCRT,
When the integer 412 of the upper bits match, the horizontal drive rising timing signal HDT is generated and supplied to the reset terminal of the horizontal drive width counter 414. The comparator 415 compares the output of the horizontal drive width counter 414 and the horizontal width control signal HPW, and specifies the horizontal drive pulse 416 in units of clock φs by the horizontal width control signal HPW from the time when the horizontal drive rising timing signal HDT is obtained. Occurs for a period of time, and supplies this to the gate delay circuit 417. The gate delay circuit 417 is composed of 28 stages of gate delay elements like the above gate delay circuit 200, and the 28 delay outputs are 418.
Are supplied to the selection circuit 419. On the other hand, the multiplier 420 multiplies the horizontal drive-clock phase correction signal HDCR by the delay amount monitor signal GDN, and outputs the result as a horizontal drive-clock phase correction signal HDCR1 in date delay units. Here, the selection circuit 419 selects the output of the gate delay stage according to the content of the horizontal drive-clock phase correction signal HDCR1 and outputs it to the horizontal drive pulse HD.
Derive as.

The present invention is particularly characterized by using the gate delay monitor circuit 32. In a system that operates based on the sampling clock φs and uses a gate delay circuit, if the delay element itself has an offset or if an offset occurs, it will have an important effect on the synchronization relationship of the system. However, in the present invention, the delay amount monitor signal GDN from the gate delay monitor circuit 32 is effectively utilized.

FIG. 12 shows the structure for obtaining accurate phase data of the flyback pulse extracted from the embodiment. In this block, the signal HCTR from the horizontal counter 109 will be described as fully corrected and accurate. From the flyback-clock phase detection circuit 28, a signal FBT synchronized with the clock φs and a phase component FBΔτ indicating the deviation between the clock φs and the flyback pulse HFB are obtained. Since the output signal HCTR of the horizontal counter 109 is latched by the latch circuit 401 at the timing of the signal FBT, the timing of the signal FBT is replaced with the count content of the horizontal counter 109. Since the phase component FBΔτ is not taken into consideration in the output of the latch circuit 401, the latch circuit 401 is used in the subtractor 403.
The phase component FBΔτ may be subtracted from the output of. However, in the present invention, the possibility that the phase component FBΔτ itself includes the phase shift component due to the delay element is also taken into consideration, and the phase component FBΔτ is supplied to the subtractor 403 after passing through the multiplier 400. In the multiplier 400, the delay component monitor signal GND is used as described above, and the phase component FB
Correction of Δτ is performed.

[Effects of the Invention] As described above, according to the present invention, it is possible to improve the accuracy of horizontal synchronous reproduction, reduce the jitter of horizontal synchronous reproduction due to digital processing, and to reduce the amount of delay of the gate delay circuit. Since it can respond automatically, the integration of the digital horizontal synchronization circuit can be greatly improved.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart of a rising edge of a horizontal synchronizing signal, FIG. 3 is a block diagram of a horizontal-clock phase detecting circuit, and FIG. 4 is a digitally controlled oscillator. , Block diagram of horizontal phase error detection circuit and horizontal loop filter, Fig. 5 shows flyback-
A block diagram of the inter-clock phase detection circuit, FIG. 6 is a timing chart of the circuit of FIG. 5, FIG. 7 is a block diagram of the gate delay monitor circuit, FIG. 8 is a timing chart of the circuit of FIG. 7, and FIG. 7 is a timing chart of the circuit of FIG. 7, and FIG. 10 is a delay-clock unit correction circuit, flyback phase error detection circuit, flyback loop filter, horizontal drive phase generation circuit, clock-delay unit correction circuit and horizontal drive generation circuit. Block diagram of
FIG. 11 is a timing chart when the horizontal synchronizing circuit operates,
FIG. 12 is a circuit diagram showing a part of the circuit shown in FIG. 12 ... Analog-digital converter, 14 ... Sync separation circuit, 17 ... Horizontal sync detection circuit, 19 ... Horizontal-clock phase detection circuit, 21 ... Digital control oscillator, 24 ... Horizontal phase error detection circuit, 26 …… Horizontal loop filter, 28…
… Flyback-clock phase detection circuit, 32 …… Gate delay monitor circuit, 34 …… Flyback loop filter, 41 …… Horizontal drive phase generation circuit, 200 …… Gate delay circuit.

Claims (1)

[Claims] 1. A digital television circuit for digitizing and processing an analog video signal with a sampling clock, wherein a plurality of first gate delay element groups connected in series to which the sampling clock is input and the sampling clock are counted. A counter; a timing generation circuit that outputs first and second timing signals and a third timing signal having the same frequency as the sampling clock based on the counter output of the counter; Latch means for latching each delay element output of the gate delay element group, and a register in which latch data of the latch means is loaded by the second timing signal and this data is data-shifted by the third timing signal. , The output data of the register is from "0" The output value of the counter at the n-th time and the (n + 1) -th time (n is an integer) at either one of the change points of "1" or "1" and "0" is latched and the latched value is 2 A means for taking a difference between two values and obtaining as a sampling clock delay amount monitor signal data indicating how many delay amounts of the gate delay element correspond to the period of the sampling clock; and an input controlled signal. A plurality of second gate delay element groups connected in series, means for obtaining a signal obtained from a specific gate element of the second gate delay element group as a synchronized controlled signal, and the second gate Latch means for latching each delay element output of the delay element group with the sampling clock, and the input controlled signal and the sampling signal by using the content of the latch data of the latch means. Means for obtaining error information between specific phases of the ring clock and outputting it as a first phase correction signal of the synchronized controlled signal; and dividing the first phase correction signal by the sampling clock delay amount monitor signal. As a result, a second phase correction signal in which a phase change component corresponding to the phase fluctuation of the sampling clock itself is added to the first phase correction signal for correcting the phase of the synchronized controlled signal is generated. The result of latching the count output of the dividing means for obtaining and the counter whose value changes in the horizontal cycle with the synchronized controlled signal is further corrected by the second phase correction signal, and this corrected output is used as flyback pulse information. And a means for using the digital synchronizing circuit.