JPS61253694A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To make the action speed highly speedy by amplifying the electric potential difference between an input terminal and an inverting input terminal based upon the control signal to supply to the fifth MOS transistor. CONSTITUTION:At the place where the electric potential difference to occur between an input terminal 11 and an inverting input terminal 12 is opened to some extent by starting the reading action from the memory cell, a control signal CS is set to the high level and a MOS transistor 18 for control is made conductive, and then, the electric potential of connecting points N1 and N2 rises. Here, when the electric potential of the input terminal 11 is decreased, the channel resistance of a MOS transistor 13 comes to be high, the electric potential of the connecting point N1 rises, a MOS transistor 19 and a bipolar transistor 21 is made conductive and the electric potential of the input terminal 11 is decreased larger. At such a time, the electric potential of the inverting input terminal 12 is kept to the high level. On the other hand, when the electric potential of the inverting input terminal 12 is decreased by reading the information, in the same way, an MOS transistor 20 and a bipolar transistor 22 are made conductive and the fall of the electric potential is accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sense amplifier circuit of a semiconductor memory device provided on a bipolar CMOS (complementary metal oxide semiconductor) integrated circuit.

[Technical Background of the Invention] Conventionally, as this type of sense amplifier circuit, for example, a third
A latch type sense amplifier circuit as shown in the figure is used. In FIG. 3, a P-channel type MoS transistor 1 and an N-channel type MOS transistor 2 are
A P-channel type MOS transistor 4 and an N-channel type MOS transistor 5 constitute a second CMOS inverter 6, respectively. 2nd CMOS inverter 3, 6 people,
The output terminals are connected alternately to form a latch circuit. An input terminal 7 is connected to the connection point of the MOS transistor 1.2 and the gate of the MoS transistor 4.5.
The connection point of the above MOS transistor 4.5, and the MOS
Inverting input terminals 8 are connected to the gates of the transistors 1 and 2, respectively. Note that 9 is a power supply terminal to which a power supply voltage V is applied, and 10 is a control N-channel type MO whose conduction is controlled by a control signal C8 to control the operation of this sense amplifier circuit.
It is an S transistor.

In the above configuration, the input terminal 7 and the inverted input terminal 8 are connected to the bit line and the inverted bit line of the semiconductor memory device, respectively. When reading information from the memory cell, the bit line and the inverted bit line are set at a high level and the same potential, and when information is read from the memory cell, either The drop in one potential is amplified.

The operation of the sense amplifier circuit will be described in detail below.

When the control signal C8 becomes high level and the MoS transistor 10 is turned on, this sense amplifier circuit enters the operating state. Since the gates of the MoS transistors 2 and 5 are at a high level, both are turned on and work to lower the potential of the input terminal 79 and the inverting input terminal 8. At this time,
According to the information read from the memory cell, if there is a potential difference between terminals 1.8, MOS transistors 2, 5 and 1.
There is a difference in the conduction state of 4. Now, assuming that the potential of input terminal 1 is lower than the potential of inverting input terminal 8, MOS transistor 2 has a lower channel resistance than MOS l-transistor 5, and MOS transistor 1 has a channel resistance higher than MOS transistor 4. . Therefore, the potential drop at the input terminal 7 is faster than at the inverting input terminal 8. This tendency is accelerated as the potential difference between the terminals 7 and 8 increases, and when the potential of the input terminal 7 becomes less than the logic threshold of the inverter 6 composed of MoS transistors 4.5,
Since the channel resistance of MOS transistor 4 becomes lower than the channel resistance of MOS transistor 5, inverting input terminal 8 is charged and the potential begins to rise. Finally, the input terminal 7 becomes a completely low level, and the inverting input terminal 8 becomes a completely high level. On the other hand, when the potential of the input terminal 7 is higher than the potential of the inverting input terminal 8, the input terminal 7 similarly becomes a high level and the inverting input terminal 8 becomes a low level.

[Problems with the Background Art] By the way, in the latch type sense amplifier circuit shown in FIG. 3 above, when trying to increase the operating speed (when discharging a bit line or an inverted bit line quickly)
, it is necessary to increase the dimensions of each MOS transistor 1°2.4 and 5. However, these MoS
If the dimensions of transistors 1.2.4 and 5 were increased, the load on the bit line and inverted bit line would be increased, and there was a limit to speeding up.

[Object of the invention] This invention was made in view of the above circumstances,
The purpose is to provide a sense amplifier circuit that can shorten the time for discharging a bit line without increasing the load on the bit line, and can increase the operating speed.

[Summary of the Invention] In other words, in order to achieve the above object, the present invention uses bipolar transistors that can be used in bipolar CMOS embedded integrated circuits to shorten the discharge time of bit lines. and a first conductivity type first . a second MOS transistor, and a third MOS transistor of a second conductivity type, one end of which is connected to the other ends of the first and second MOS transistors, and the other end of which is commonly connected. a fourth MOS transistor, and these third and fourth MOS transistors;
a fifth MOS transistor of a second conductivity type connected between the common connection point on the other end side of the S transistor and the other side of the power supply and whose conduction is controlled by a control signal; 1. a sixth MOS transistor of the first conductivity type connected to the connection point of the third MOS transistor and the gate of the fourth MOS transistor;
A seventh MOS transistor of the first conductivity type connected to the connection point of the OS transistor and the gate of the third MOS transistor, and a seventh MOS transistor connected between the input terminal and one of the power supplies, and whose base is connected to the other end of the sixth MOS transistor. A sense amplifier circuit is constituted by a first bipolar transistor connected between the inverting input terminal and one of the power supplies, and a second bipolar transistor whose base is connected to the other end of the seventh MOS transistor.
The potential difference between the input terminal and the inverting input terminal is amplified based on a control signal supplied to the OS transistor.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The input terminal 11 and the inverting input terminal 12 in FIG. 1 each have an N-channel type (first conductivity type) first
．． The gates of sixth MOS transistors 13 and 14 are connected. One ends of these MOS transistors 13 and 14 are commonly connected to a ground point (one side of the power supply). The other ends of the MOS transistors 13 and 14 each have a P
The third channel type (second conductivity type). One ends of fourth MOS transistors 15 and 16 are connected. The other ends of these MOS transistors 15 and 16 are commonly connected, and this common connection point and a power supply terminal 17 to which a power supply (the other N source) is supplied.
A fifth control MOS transistor 18, which is a P-channel type and is made conductive by the control signal O8, is connected between the control signal O8 and the control signal O8. The gate of the MOS transistor 15 has a MOS
A connection point N2 between transistors 14 and 16 is connected,
A connection point N1 between MOS transistors 13 and 15 is connected to the gate of the MoS transistor 1G. Also,
The input terminal 111 and the inverting input terminal 12 each have N
Channel type 6th. 7th MOS transistor 19.20
One end of is connected.

The gate of the MOS transistor 19 is connected to the MOS transistor 19.
The connection point N1 between the transistors 13 and 15 is connected, and the gate i of the MOS transistor 20 is connected to the MOS transistor 20.
A node N2 between transistors 14 and 16 is connected.

Further, the input terminal 111 and the inverting input terminal 12 each have an NPN type first . Second bipolar transistor 21
．． The collectors of bipolar transistors 2i and 22 are connected to each other, and the emitters of these bipolar transistors 2i and 22 are connected to a ground point.

The other end of the MOS transistor 19 is connected to the base of the bipolar transistor 21, and the base of the bipolar transistor 22 is connected to the MOS transistor 19.
The other end of the transistor 20 is connected.

In the above configuration, a bit line and an inverted bit line are connected to the input terminal 111 and the inverted input terminal 12, respectively, and a plurality of memory cells are connected to these bit line pairs.

Next, the operation in the above configuration will be explained. Here, the input terminal 111 and the inverting input terminal 12 are at a high level and at the same potential before the operation of reading information from the memory cell, and the MOS transistor 18 is in a non-conducting state when the control signal C8 is at a low level. In this state, the MOS transistors 13 and 14 are conductive, so
Connection point N1. N2 is fixed at ground potential. As a result,
MOS transistors 19 and 20 are non-conductive, and bipolar transistors 21 and 22 are also non-conductive.

When a read operation from the memory cell is started, a potential difference is generated between the input terminals 111 and the inverting and inverting input terminals.

When this potential difference opens by about 0.5V, the control signal C8 is set to high level and the control MOS transistor 18
When conductive, the connection point N1. A state is reached in which the potential of N2 is about to rise. Now, if the potential of the input terminal 11 drops, the channel resistance of the MOS transistor 13 increases, and the potential of the connection point N1 rises. This increases the channel resistance of the MOS transistor 16, so that the potential at the connection point N2 is fixed at a low level. As a result, the MOS transistor 20 whose gate is connected to the connection point N2 remains non-conductive, while the MOS transistor 19 whose gate is connected to the connection point N1 becomes conductive, and base current is supplied to the bipolar transistor 21. , this bipolar transistor 21 becomes conductive. In this way, the potential of the input terminal 11, which has slightly decreased in potential due to reading of information from the memory cell, is further decreased by the conduction of the bipolar transistor 21. At this time, since the MoS transistor 20 and the bipolar transistor 22 remain non-conductive, the potential of the inverting input terminal 12 is maintained at a high level.

On the other hand, when the potential of the input terminal 11 remains at a high level and the potential of the inverting input terminal 12 decreases due to reading of information from the memory cell, the MOS transistor 20 and the bipolar transistor 22 similarly become conductive. , the drop in potential accelerates.

According to this configuration, since a bipolar transistor is used instead of a MOS transistor to drive the bit line, the drive ability of the sense amplifier circuit can be improved without increasing the load on the bit line.
It is possible to increase the operating speed.

FIG. 2 shows another embodiment of the invention.

In the figure, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. That is, the N-channel type eighth . 9th MOS transistor 2
3.24 is connected, and the above MOS transistor 2
The gate of the MOS transistor 24 is connected to the connection point N2, and the gate of the MOS transistor 24 is connected to the connection point N1.

According to such a configuration, when the MOS transistor 19 or 20 is in a non-conducting state, the MOS transistor 23 or 24 is in a conducting state and the base of the bipolar transistor 21 or 22 is connected to the ground point, so that the bipolar transistor on the non-conducting side It is possible to ensure that the circuit is shut off.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain a sense amplifier circuit that can shorten the time for discharging a bit line without increasing the load on the bit line, and can increase the operating speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a sense amplifier circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram for explaining another embodiment of the invention, and FIG. 3 is a diagram of a conventional sense amplifier circuit. FIG. 3 is a diagram showing the configuration. 11... Input terminal, 12... Inverted input-child, 13.
14.15°16, 18.19.20.23.24...
-Mo8 transistor, 21, 22...Bipolar transistor, 17...'1lli terminal, ■...Power supply (other power supply), C8...Control signal.

Claims (2)

[Claims] (1) First and second MOS transistors of a first conductivity type, each of which has its gate connected to an input terminal and an inverted input terminal, and whose one end is connected to one of the power supplies;
third and fourth MOSs of the second conductivity type, each of which has one end connected to the other end of the MOS transistor, and whose other ends are commonly connected;
a fifth MOS transistor of a second conductivity type that is connected between the common connection point on the other end side of the third and fourth MOS transistors and the other side of the power supply and whose conduction is controlled by a control signal, and one end of which is connected to the input terminal. a sixth MOS transistor of the first conductivity type, the gate of which is connected to the connection point of the first and third MOS transistors and the gate of the fourth MOS transistor; a seventh MOS transistor of the first conductivity type connected to the connection point of the second and fourth MOS transistors and the gate of the third MOS transistor;
a first bipolar transistor connected between the input terminal and one of the power sources, and whose base is connected to the other end of the sixth MOS transistor; and a seventh MOS transistor, which is connected between the inverting input terminal and one of the power sources, and whose base is connected to the other end of the sixth MOS transistor. a second bipolar transistor connected to the other end thereof, and amplifies the potential difference between the input terminal and the inverting input terminal based on a control signal supplied to the fifth MOS transistor. circuit. (2) an eighth MO of the first conductivity type connected between the base of the first bipolar transistor and one of the power supplies, and whose gate is connected to the connection point of the second and fourth MOS transistors;
an S transistor connected between the base of the second bipolar transistor and one of the power supplies, the gate of which is connected between the first and second bipolar transistors;
2. The sense amplifier circuit according to claim 1, further comprising a ninth MOS transistor of the first conductivity type connected to the connection point of the third MOS transistor.