JPS6126995A - Sensor circuit - Google Patents

Abstract

PURPOSE:To accomplish a stable action under a low voltage power source without adversely affecting a high speed of a current mirror-type circuit by providing a reverse conductive FET connected to the power source of a common node at one side of an FET controlled by means of a differential input, and controlling the output at the other side. CONSTITUTION:When a differential input Vin and its anti-Vin drops and rises, respectively, FETs Q13 and Q14 start turning on and off, respectively. An output Vout and its anti-Vout are connected to power sources VDD, and changed to be ''L'' and ''H'' through Q16 and Q17 for comprising a current mirror circuit, respectively. Then, after a common node at one side of the Q13 and Q14 is controlled by the output Vout, it is connected to the power source VDD, and the Q13, Q14 and a reverse conductive Q18 are turned on. Thus the common node at one end of the Q13 and Q14 goes to a voltage near to the power source VDD to turn off completely the Q13, and the output anti-Vout goes to a completely high level. Accordingly a stable action is made possible under a low power source voltage without adversely affecting a high speed of a current mirror-type sensor circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a sense circuit in, for example, a semiconductor memory.

[Technical background of the invention and its problems]

' In general, this type of sense circuit that requires particularly high-speed operation is constructed as shown in FIG. That is, the differential input signal Vin.

■A pair of differential input MO8FETs supplied with 1 Q
1.

One end of Q2 is commonly connected, and a ground point ■ss is connected to this common connection point via a MOSFET Q3 which is set to be conductive by the power supply voltage vDD. In addition, the above MO8FET
One ends of MOSFETs Ql and Q5 forming the current mirror circuit 11 are connected to the other ends of Q 1 and Q 2 . A power supply terminal 12 to which a power supply voltage vDD is applied to the other ends of the MO8FETs Ql and Q5, respectively;
．． 12. are connected, and the gates are commonly connected. The connection point between MOSFETs Q1 and Ql is connected to the gate common connection point of MO8FETs Ql and Q5. Then, differential amplified outputs Vout and Vo are obtained from the connection point between the MO8FET Q 2 and Q5 and the connection point between the upper Ne MOSFET Q 1 and Ql, respectively.
Get ut.

Next, the operation in the above configuration will be explained. M.O.
A differential input signal V is applied to the gates of SFET Ql and Q2.
When in and Vin are supplied, MOSFET Q
1 and Q2, one is in the on state and the other is in the off state.

As a result, the drain side node of the MOSFET that is in the on state is at a low level, and the MOSFET that is in the off state is at a low level.
When the drain side node of T is equal to 1, this is output as differential amplification outputs Vout and Voπ.

FIG. 7 shows the operating waveforms in FIG. 6 above.

Note that here, the power supply voltage vDD is set to 3V.

As shown, the differential amplified outputs Vout, Vout
is not symmetrical, and the output amplitude of ■π is small. This is the output Vout terminal of the sense circuit (MOSFET Q 1 and Q
(connection point with l) connects the drain and gate in common
Since it is resolved by OSFET Q 4, its potential is equal to the power supply voltage vDD, jl) P channel type MO8
This is due to the fact that the threshold voltage vTHP of FET Q4 is lowered and does not rise to around the power supply voltage vDD.

As described above, although the current mirror type sense circuit shown in FIG. 6 can achieve high-speed operation, since the amplitude of the output signal voltage Wπ is small, The disadvantage is that the level difference) cannot necessarily be made sufficiently large.

This becomes a big problem especially when the power supply voltage vDD is low.

FIG. 8 shows another configuration example of a conventional current mirror type sense circuit, in which the above-mentioned sense circuits are connected in two stages in cascade. In the figure, 13 is a first-stage sense circuit, 14 is a second-stage sense circuit, and the sense circuit 13 is
A pair of differential input MO3FETs Q6 and Q7 to which differential input signals Vin and Vin are supplied, current mirror circuits QB and Q9, and conduction controlled by a chip enable signal CE. MOSFET Ql O for wardown,
Ql 1 and MO8FE'l which is set to conduction with the power supply voltage vDD and works as a constant current source to increase sensitivity.
” Consists of Ql2.

Furthermore, since the second stage sense circuit 14 has the same configuration as the first stage sense circuit 13, this circuit 14 is shown with the same reference numeral as the sense circuit 13 with a dash added thereto. M.O.S.
Connection point between FET Q9 and Qll and MOSF
The output Vout aVout of the first stage sense circuit 13 obtained from the connection point between ET QB and QIO is the differential input MO8FET Q7' of the second stage sense circuit 14.
, Q 6' is supplied to the gate of MO8FETQ9
The output DO is obtained from the connection point between ' and Qllo.

FIG. 9 shows operational waveforms obtained by analyzing the operation of the circuit shown in FIG. 8 using the circuit simulator 5PICE. As shown in the figure, the output Do of the second stage sense circuit 14 is
The power supply voltage VDD is obtained around 3V. As mentioned above, this is due to the output ππ end of the first-stage sense circuit 13 (
The connection point between MO8FETQ8 and QIO) is pulled up by MOSFET QB whose drain and gate are commonly connected, so its potential is lower than the power supply voltage ■DD.
Channel type MO8FET Q8 threshold voltage vTI
This is due to the fact that the voltage decreases by P and does not rise to around the power supply voltage vDD. Therefore, the first stage sense circuit 13
The output π- is an intermediate potential between the power supply voltage DD and the ground potential vss. This intermediate potential is set as Noirepel, and the output V
When out becomes a low level, the differential input MO8FET Q 6'', Q in the next stage sense circuit 14
7'' may enter a region with poor sensing sensitivity and no longer sense. This becomes a problem especially when the power supply voltage vDD is low.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a sense circuit that can operate stably even at a low power supply voltage without impairing the high speed of the current mirror type sense circuit.

[Summary of the invention]

That is, in this invention, in order to achieve the above object, the differential input MO8FET Q in FIG.
A MOSFET of the opposite conductivity type to these MOSFETs Q 1 and Q 2 is provided between the common connection point on one end side of MOSFETs Q 1 and Q 2 and the power supply vDD, and the MOSFETs Q 2 and Q 5 are connected to each other.
The conduction is controlled by the potential Vout at the connection point.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, Q13. Q14 is a differential input signal Vin, a pair of differential inputs MO8 to which Vin is supplied.
FET, these MOSFET Q 13 , Q 1
4 are connected in common, and a ground point 6B is connected to this common connection point via a MOSFET Q 15 which is set to be conductive by the power supply voltage vDD. Above MO8FET Q
One ends of MOSFETs Q 16 and Q 17 configuring current mirror circuit No. 5 are connected to the other ends of 13Q to 14, respectively. This MOSFET Q 1'6
, Q17 has the power supply voltage V at the other end. A power supply terminal 16 to which D is applied. .

16□ are connected to each other, their gates are commonly connected, and MOSFET Q
The connection point between I J and Q16 is connected.

Furthermore, MOSFET Q 2 B is connected between the common connection point on one end side of the MO8FETs Q 13 and Q 14 and the terminal 163 to which the power supply voltage connection points are connected. And the above MO8FET Q14 and Q
17, output signal Vout from the connection point with MOSFET
The output signal ■π is obtained from the connection point between Q13 and Q16.

Next, the operation of the above configuration will be explained with reference to the waveform diagram of FIG. 2. Input signal Vin is constant (3■
), when Vin starts to drop this much, the MOSFET
Q l,? begins to turn on and Q14 begins to turn off. Therefore, the output signal Vout changes to a no-y level, and - changes to a low level. At this time, MOSFET Q 1 B is turned off because the output signal Vout is at a high level, and operates in the same manner as the circuit shown in FIG. 6 above. , On the other hand, the input signal ■1 rises and becomes constant at 3V, and vin
When begins to drop below this, MO8FET Q14 begins to turn on and Q13 begins to turn off. As a result, the output signal Vout changes to low level and Vout changes to high level. At this time, MOSFET Q18 is not in the on state because the output signal Vout is at a low level.
The potential at the common connection point on one end side of SFET Q13 and Q14 rises near the DD level.

This allows MOSFET Q 13 to be completely turned off, causing the output signal port to rise to /.

According to such a configuration, the MOSFET can be operated even at a low power supply voltage.
Q1.9 can be completely turned off, resulting in stable operation. Note that the high speed, which is an advantage of the current mirror type sense circuit, is not impaired.

FIG. 3 shows another embodiment of the invention, in which the sense circuits described above are connected in two stages in cascade.

Note that here, a power-down MOSFET whose conduction is controlled by the chip enable signal CE is provided.

That is, the differential input signals Vin and Vin are input to the pair of differential inputs MO8FE constituting the first stage sense circuit 17.
It is supplied to the gates of T Q 19 and Q20, respectively. These MO8FETQ19. One end of Q20 is commonly connected, and a ground point "ss" is connected to this common connection point via a MOSFET Q21 which is set to be conductive at the power supply voltage vDD.
The other ends of Q20 each have a chip enable signal C.
MOSFET Q22, Q23 whose conduction is controlled by E
, and MOSFETs forming the current mirror circuit
The power supply voltage ■DD is applied via Q24 and Q25, respectively.
Power supply terminals 19□ and 19□ to which is applied are connected.

Above MO8FETQ;! 4. The gates of Q25 are commonly connected, and the MOSFET is connected to the common gate connection point.
The connection point between Q22 and Q24 is connected. Further, a common connection point on one end side of the MO8FETs Q19 and Q20 and a power supply terminal 19 to which the power supply voltage vDD is applied. A MOSFET Q 2 t; is connected between this MOS
The gate of FET Q26 is MOSFET Q
The connection point between 20 and Q23 is connected. ”2, the output node of the first stage sense circuit 17 (MOSFET Q, ?
,? Contact point between and Q24 and MOSFET Q2
3 and Q25), there is a second-stage sense circuit 18.
A pair of differential input MO8FETs Q 27 ,
The gates of Q 2 B are connected respectively. The above Mo
5Fzr Q27, Qz/? One end is connected in common, -4 This common connection point is connected to the ground point vs through MOSFET Q 29 which is set to be conductive at the power supply voltage vDD.
8 is connected. On the other hand, the above MO8FET Q 27
.

The other ends of Q2B each have a chizo enable signal CE.
MOSFET Q30, Q31 whose conduction is controlled by -MOSFET Q which constitutes a current mirror circuit
32.

Q.? 3 to which the power supply voltage vDD is applied, power supply terminals 201.20. is connected. The above MOSFET
Q32. The gates of MOSFETs Q 30 and 93 are commonly connected, and the connection point of MOSFETs Q 30 and Q32 is connected to this common connection point. And the above MO8FET Q
An output signal Do is obtained from the connection point between Q31 and Q33.

Figure 4 shows the operating waveforms of the circuit shown in Figure 3 above.
This is based on the circuit simulator 5PICE. As shown in the figure, the sensing operation starts when the power supply voltage vDD is around 25 V, and it can be seen that the characteristics at low power supply voltages are improved compared to FIG. 9 described above.

FIG. 5 shows still another embodiment of the invention,
The differential amplification output V□ut in the circuit shown in FIG.
A load is provided between the output terminal of Vc)π and the power supply. In the figure, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. That is,
The connection point between MOSFET Qzs and Q16, the connection point between MOSFET Q24 and Q17, and the power supply terminal 21 to which the power supply voltage DD is applied. ．． MO8FETQ34.212 and MO8FETQ34. Q35 is connected.

The MO8FETs Q 34 and Q 35 are set to be conductive at the ground potential vss, and function as a load.

According to such a configuration, when the output is output, the potential of the output node (the connection point between MOSFETs Q73 and Q16 and the connection point between MOSFETs Q14 and Q17) is changed by MOSFETs Q34 and Q35 as loads. Since one side is raised to around the power supply voltage vDD,
The amplitude of the output signal can be increased. Here, MOSF
The channel width/channel length of ET Q, 14, Q35 is the channel width/channel length of MOSFET Q16, Q17.
If the channel length is set sufficiently small, circuit operation at high power supply voltages will not be affected.

In each of the above embodiments, the differential input MO8FET is an N-channel type, and the load MO8FET is a P-channel type.
This means that the N-channel type has higher carrier mobility and faster fall drive, and when used in a memory, the bit line potential as the input signal V 1 n * V i n is equal to the power supply voltage ■DD. This is because the signal is close to 9, but if you want the signal to rise quickly, or if the input signal
+ If you want to amplify Vtn, use differential input MO8F
Of course, E'r may be of P-channel type and the load MO3FET may be of N-channel type.

〔Effect of the invention〕

As explained above, according to the present invention, 1. A sense circuit that can operate stably even at a low power supply voltage without impairing the high speed performance of the current mirror circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a sense circuit according to an embodiment of the present invention, FIG. 2 is an operational waveform diagram of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. Figure 4 is the 3rd figure above.
A diagram showing circuit simulation waveforms in the circuit shown in the figure,
FIG. 5 is a circuit diagram showing another embodiment of the present invention, FIG. 6 is a diagram showing a conventional sense circuit, FIG. 7 is an operating waveform diagram of the circuit shown in FIG. FIG. 9, a diagram showing another sense circuit, is a diagram showing circuit simulation waveforms in the circuit of FIG. 8. Vin, Vin-differential input signal, Ql3,
Q14...1st and 2nd MOSFET, Q16
, Q 17...3rd. 4th M08FF:T,
Q18-...5th MOSFET, Vout, V
oui: differential amplification output, vss: first potential supply source, vDD: second potential supply source. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 5 VSS Figure 6 Figure 7 Hankaku-' Figure 8 Figure 9 Denbo Too (Vl-

Claims (3)

[Claims] (1) A pair of first conductivity type first and second MOSFETs whose one ends are commonly connected and to which a differential input signal is supplied;
, a current source connected between one end side common connection point of the second MOSFET and the first potential supply source; and a second conductive current source connected between the other end of the first MOSFET and the second potential supply source, the gate of which is connected to the drain. the third MOSFET of the shape and the second MOSFET of
a fourth MOSFET of a second conductivity type connected between the other end of the OSFET and a second potential supply source and having a gate connected to the gate of the third MOSFET;
a fifth MOSFET of a second conductivity type connected between a common connection point on one end side of the MOSFET and a second potential supply source and whose conduction is controlled by the potential of the connection point of the second and fourth MOSFETs; 3rd MOSFET and 2nd and 4th M
A sense circuit characterized by obtaining differential amplified outputs from respective connection points of OSFETs. (2) The first and third MOSFETs and the second and fourth MOSFETs
2. The sense circuit according to claim 1, further comprising a load element between the connection point of the OSFET and the second potential supply source. (3) The sense circuit according to claim 1, wherein the input terminal of the next stage receiving the output of the sense circuit is composed of a first conductivity type MOSFET.