JPS61251281A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain an output level of 2VP-P with a complete dynamic range even by a power source voltage of 5V by using an image output amplifier and a clamp circuit in a recording system and a reproducing system in common, and disposing a switch circuit to select the video signal of the recording system and the reproducing system in a prestep of the clamp circuit. CONSTITUTION:In a video signal processing circuit comprising a recording system and a reproducing system, an image output amplifier 33 used for the recording system and the reproducing system in common, a first switch circuit 32, a squelch circuit 31, a clamp circuit 30 used for the recording system and the reproducing system in common and a second switch circuit 29 are provided. The first switch circuit 32 selectively connects an output of the clamp circuit 30 and an output of the squelch circuit 31 to an input of the image output amplifier 33 and the second switch circuit 29 selectively connects the video signal of the recording system and the video signal of the reproducing system to an input of the clamp circuit 30, thereby the video signal from the recording system can be obtained when recording, and the video signal from the reproducing system when reproducing can be obtained from the image output amplifier 33.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention is applicable to a portable VT which requires low power supply voltage operation.
The present invention relates to video signal processing such as R, and particularly to a video signal processing circuit suitable for outputting a signal level of 2 VP-P.

[Background of the invention]

° Length L Vol, 2B, A 5 (Jtl, ns 5982
#)) Discussed in the document entitled "Signal processing and control IC for VTR1-'" in K. Yu. Literature 1.
1. An amplifier is installed in each of the recording system and the re-engineering system, and the amplifier can be used for both the recording system and the reproduction system, and the synchronization signal tip potential in the recording system and reproduction system, which is a cause of bus generation in the RF converter, can be reduced. No consideration was given to fluctuations.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal processing circuit capable of obtaining a 2VP-P level output with a sufficient dynamic range even at a power supply voltage of 5V.

[Summary of the invention]

In order to achieve this object, the present invention uses a video output amplifier and a clamp circuit that clamps the video signals inputted thereto for both the recording system and the playback system, and the video output amplifier for the recording system and the playback system is connected to the front stage of the clamp circuit. The feature is that by providing a switch circuit for selecting , the variation in the clamp potential is minimized to ensure the dynamic range of the video output amplifier, and the video output amplifier is of a feedback type to reduce distortion.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

fst diagram is a block diagram showing an embodiment of a video signal processing circuit according to the present invention, in which 1 is an input terminal for a video signal, 2 is an input terminal for a video signal;
is the AGC circuit, and 5 is the LPF.

4 is an emphasis circuit, 5 is an FM modulator, and 6 is a 1 (PF
, 7 is BPF, 8 is ACC circuit, 9 is chromaticity signal processing circuit (chroma processing circuit), 10 is frequency conversion circuit, 11 is L
PF, 12 is a mixer, 15 is a recording amplifier, +4 is a video head (for recording), 15 is a magnetic tape, 16 is a video head (for reproduction), +7 is a reproduction amplifier (preamplifier),
+8 is HPF, 19 is FM demodulator, 20 is de-emphasis circuit, 21 is LPF, 22 is I, PF, 25 is AC
C circuit, 24 is a frequency conversion circuit, 25 is a BPF, 26 is a comb filter, 27 is a chromaticity signal processing circuit (chroma processing circuit), 2B is a mixer, 29 is a second switch circuit (hereinafter simply referred to as the switch circuit 29). 50 is a clamp circuit, 51 is a squelch circuit, 52 is a first switch circuit (hereinafter simply referred to as switch circuit S2), 55 is a video output amplifier, 54 is a video signal output terminal, 55 is a third switch circuit (hereinafter simply referred to as switch circuit S5), 56 is an LPF
, 57 is a synchronous separation circuit, 58 is a composite synchronous signal output terminal,
59 is a squelch potential.

In the same figure, during signal recording, a video signal input from an input terminal 1 is opened to a specified level by an AGC circuit 2, and then the chromaticity signal component is removed by an LPF 5. The luminance signal is processed by the HPF6. On the other hand, the video signal from the input terminal 1 is processed by the BPF 7 to extract the chromaticity signal component, and the ACC circuit B to set the burst level to a specified level.The chromaticity signal processing circuit 9, the frequency conversion circuit 10, and the L P Fll The chromaticity signal is processed. These signals are mixed in a mixer 12 and then sent to a magnetic tape 1 via a recording amplifier 15 and a video head 14.
Recorded in 5.

Note: During playback, after the playback video from the video head 16 is amplified by the playback amplification #A organ 7, the HPF 18 extracts the luminance signal processing, and the FM demodulator 19, de-emphasis circuit 20, and LPF 21 perform the luminance signal processing. be done, while LP
The chromaticity signal extracted by F22 is subjected to chromaticity signal processing in an AGC circuit 25, a frequency conversion circuit 24, an HPF 25, a comb filter 26, and a chromaticity signal processing n-path 27. mixed in.

The video signal selected by the switch circuit 29, which switches between recording and playback, is passed through the switch circuit 52 during recording and playback after making the tip potential of the synchronization signal constant in the clamp circuit 50.
The signal is input to the video output amplifier 55 via. On the other hand, during squelch, the switch is connected in the opposite direction to that shown in the figure, and the squelch potential 59 is input to the video output amplifier f155. The squelch circuit 52 prevents an extremely difficult-to-read reproduction surface from appearing on the television monitor during the several seconds required for the magnetic tape/video head to be set in its proper position and the servo system to lock.

Further, the luminance signal during recording and the luminance signal during reproduction are input to the switch circuit 55. These signals are LPF56
After removing noise and the like, the synchronization separation circuit 57 separates the composite synchronization signal.

Next, the video output amplifier 55, which is the main part of the video signal processing circuit according to the present invention, will be explained.

FIG. 2 is a specific circuit configuration diagram of a video output amplifier 55 that outputs a 2 VP-P video signal, in which 51 is a video signal input terminal, 52-56 are transistors, 57-66 are resistors, 67, 68kt I Cf) Hiy, 69haV
The video output terminal of the TR, 70 is the video input terminal of the monitor TV, 71 to 75 are capacitors, 74 is an IC, 75
is a monitor television. The output of the differential amplifier composed of transistors 52 and 55 is fed back to the base of transistor 55 via transistor 54, a resistor 61 connected in parallel, and a capacitor 75, thereby performing a negative feedback operation.

It is assumed that the level of the video signal input to the input terminal 51 is, for example, tVp-p, and the synchronization tip potential is clamped. In order to output a 2VP-P video signal, the amount of feedback should be halved. The amount of feedback is determined by the ratio of the resistor 61 and the parallel resistance of the resistor 59 and 60.
The DC potential of the base of 5 is determined by the resistance ratio of resistors 59 and 60.

In order to widen the output dynamic range of the differential amplifier consisting of transistors 52 and 55, transistor 5
2. The base potential of 55 should be as low as possible, -
As an example, the resistor 59 is set to SS&Ω, the resistor 60 is set to 12Ω, and the DC potential applied to the base of the transistor 55 is 1V.
shall be. From this, the resistance 61 that determines the amount of feedback is 2.57
&Ω. The value of the resistor 58 cannot be increased in consideration of the ground capacitance of the IC pin 67. Here, as an example, Ω is set to 1.8. The collector potential of transistor 55 is determined by the value of resistor 57. FIG. 3 shows the relationship between the collector potential of the transistor 55 and the differential gain and differential phase of the transistor 54 which outputs a 2 VP-P video signal. In the figure, 76 indicates differential gain, and 77 indicates differential phase. Generally, it is desired that the differential gain be within 5% and the differential phase within 5 degrees. From the diagram s5, the synchronizing signal tip potential of the collector of the transistor 55 is preferably about 1.8V.

Therefore, if the synchronizing signal tip potential of the transistors 52 and 55 is 1V, the voltage drop between the base and emitter (VB
, ) are 0.7V, so the value of the resistor 57 is 84Ω.

The emitter current of the transistor 54 needs to have a current value that can drive the load consisting of the terminal resistor 66 of the monitor television shown by the output resistors 65 and 75 of VTf'L. As is well known, the output resistance 65' of the VTR has a value of 75Ω, and the terminal resistance of the monitor television 75 has a value of 75Ω. 2 Since the load resistance is 150Ω for the VP-P video signal, it is approximately 15Ω.
9 charge current of WLA. Here, as an example, it is assumed that the emitter current of the transistor is about 2 ohmA. For this reason, transistors 55 and 56 are used as current mirrors, 20 m of current flows to transistor 56, and 20 m of current flows to transistor 55.
A Let it flow. - As an example, change the value of resistor 63 to 2Ω
By setting the value of the resistor 64 to 1500 and the value of the resistor 62 to 150, the differential phase becomes worse due to the ground capacitance of the IC pin 67. Capacitor 72 in FIG.
This assumes a grounding capacitance of 7 (actually, capacitor 72 is not included). FIG. 4 shows the differential gain and differential phase with respect to the capacitance value of the capacitor 72. In the figure, 78 indicates differential gain, and 79 indicates differential phase. The capacitance of a general KIC pin to ground is about 5 pF to 157P. Fourth
From the figure, the capacitance between ground and IC pin 76 is 5PF to tsPF.
It can be seen that the differential gain can be satisfied within 5% and the differential phase can be satisfied within 5 degrees, even if the difference is small.

In addition, in the configuration shown in FIG. 2, if the capacitor 72 is not provided, the gain will increase by about adB at a frequency of about 10.5 MHz, as shown in FIG. 3, which will cause S/N deterioration. As shown in Figure 2, a capacitor 75 of approximately 51 F is attached to increase the amount of high-frequency feedback, and the sixth
As shown in the figure, the high frequency characteristics can be flattened. A similar effect can be obtained by connecting the capacitor 75 between the collector and base of the transistor 55.

Putting the above numbers together, we get the following.

Resistance 57: 84Ω, resistance 58 = 1.8 &Ω, resistance 59 = + = 15 &Ω.

Resistance 60 = 5.2 &Ω, resistance 61 = 257Ω, resistance 6Z = +SΩ.

Resistance 65 = 2Ω, resistance 64 = 1500. resistance 65=7
50° capacitor 7+=470μF, capacitor 75=
51F.

In this way, the intended purpose of the circuit configuration shown in FIG.
It becomes possible to obtain vy+-p output.

Note that the above numerical values are vfl of transistors 52 to 56.
, is a constant value (0.7V) and the emitter resistance is 00. Actually, it is necessary to take these into consideration and make some corrections.

Moreover, these numerical values are merely examples for satisfying the purpose of the present invention, and do not limit the present invention. For example, it goes without saying that the level of the video comment input to the input terminal 51 may be set to o, 5Vp-p, and the amount of feedback may be set to 1.

On the other hand, as shown in FIG.
56, the resistors 62 and 65 are integrated inside the IC 74, and the current value for driving the load such as the resistors 65 and 66 is
A configuration in which the value is set by a resistor 64 provided outside the C is also conceivable.

Furthermore, as shown in FIG. 8, a configuration in which the resistor 64 is also integrated inside the IC 74 is also conceivable. However, the problem with these configurations is that the resistance value of the resistor 62 is about 15Ω, so it is difficult to integrate it inside the IC. Further, the accuracy of the absolute value of the resistance can only be secured to about ±20%. Also, a high voltage is applied to the output terminal 69 of the VTR (
For example, if the DC voltage of the monitor television 75 fluctuates), the transistor 54 may be destroyed. If the above problems are solved, the configurations shown in FIGS. 7 and 8 can provide the same performance as the configuration shown in FIG. 2.

Next, the clamp circuit 50 and squelch circuit 5 shown in FIG.
1. One embodiment of the switch circuit 52 will be explained with reference to FIG. The same parts as in FIGS. 1 and 2 are given the same reference numerals, and some explanations will be omitted.

In FIG. 9, 101 to 105 are IC pins, 106
is a clamp capacitor, 107-124 is a transistor, 125-155 is a resistor -1+54 is a DC voltage source,
Reference numeral 155 indicates a control signal input during squelch, 156 indicates an input terminal for a reproduced luminance signal, and 157 indicates an input terminal for a reproduced chromaticity signal.

As mentioned earlier, in order to provide a margin for the dynamic range of the output amplifier 55, it is necessary to clamp the synchronization signal tip potential of the input signal, and the synchronization tip potential of the input signal to the output amplifier 550 is different from that at the time of signal recording. It is better not to change during playback.

That is, between the clamp circuit and the output amplifier 550.

It is better not to include a circuit. Therefore, a mixer 28 is provided before the clamp circuit to mix the reproduced luminance signal inputted from the input terminal ts6 and the reproduced chromaticity signal inputted from the input terminal 157, and the AGC circuit 2 which is the video signal output during recording is provided.
The configuration is such that switching is performed between the output of the switch circuit 29 and the switch circuit 29. This allows the clamp circuit and video output circuit to be used in both the recording system and the playback system.

During signal recording and signal reproduction, a video signal in which the tip potential of the synchronizing signal is clamped by the clamping capacitor 106 and the clamping transistor 115 is supplied to the base of the transistor 1140. On the other hand, the DC potential output during squelch is applied to the base of the transistor 70. This clamp potential and the squelch DC potential are configured to be approximately the same potential.

Here, as an example, from the connection point between the resistor 126 and the collector of the transistor 107 of a reference voltage generating circuit consisting of resistors 125, 126 and transistors 107, 108,
The squelch potential is transistor 10, 122°125,
1271.

Further, a reference pressure E1 is supplied to the base of the transistor 118. An input terminal 155 is connected to the base of the transistor 119 so that the transistor 11B is turned off and the transistor 119 is turned on at the time of squelch.

At times other than squelch, a control signal is input that turns on transistor 11 and turns off transistor 119.

Therefore, during signal recording and signal reproduction, the transistor +
14 and +15 are turned on, and the video signal supplied to the base of transistor 114 is transferred to transistor 1 of the buffer piece.
The signal is input to the video output amplifier 55 via 20. on the other hand,
During the squelch period, transistors 6 and tt7 are turned on, so the DC potential supplied to the base of the transistor 117 increases the video output through the buffer transistor 120. Can be interrupted.

In this way, by adopting a configuration in which the video signal during recording and the video signal during playback are switched and then clamped, fluctuations in the synchronization signal tip potential during recording and playback can be eliminated, so that the video output amplification circuit 53 It is possible to secure sufficient dynamic range.

Next, the AGC circuit 2 and the mixer 2 for mixing the reproduced luminance signal and the reproduced chromaticity signal will be explained using FIGS. 9 and 10.

There are three modes for a VTR: recording mode, playback mode, and squelch mode.
Possible switching is recording mode → squelch mode → playback mode → recording mode. That is, although the reproduction mode is instantly switched to the recording mode, the recording mode is not instantaneously switched to the reproduction mode, and after passing through the squelch mode for several seconds, the reproduction mode is switched.

FIG. 10 shows an input waveform (same as the output waveform) of the video output amplification circuit 55 shown in FIG. 1st
In Figure 0, rα and Td indicate the recording mode, %Tb indicates the squelch mode, and To indicates the reproduction mode.

In Fig. 9, if the DC voltage output from the AGC circuit 2 during recording and the DC voltage output from the mixer 28 during playback are the same, the output of the video output increase @'a55 will be as shown in Fig. 10 (α). As shown, the tip potential of the synchronization signal is TcL, T, , T
The period d will be the same. However, since the video signals during recording and reproduction have completely unrelated signal contents, the tip potential of the synchronization signal naturally changes between recording and reproduction. Therefore, when switching from the playback mode to the record mode, if the synchronization signal tip potential of the record mode is high, it takes some time for the capacitor 106 to discharge and reach the clamp potential, and the first
As shown in the Td period in Figure 0 (A), the video signal rises. This causes overmodulation of the ordinary F converter installed after the video output amplifier, resulting in the generation of pass sound (the video signal enters the audio signal band and is considered as sound).

To prevent this, the DC voltage of the output of the mixer 28 in FIG. 9 is equal to the DC voltage of the output of the AGC circuit 2.
Increase it by about 1v. When setting 5, the top potential of the sync signal in the recording mode is lower than the potential in the playback mode, so the capacitor 106 is charged instantly and the potential of the sync signal tip changes immediately. It becomes a clamp potential. Also, when switching from recording mode to playback mode, squelch mode enters during that time, so
As shown in FIG. 10(c), the discharge of the capacitor 106 is completed during the squelch period indicated by TA, and in the reproduction mode T, the tip potential of the synchronous signal becomes the same as that in the recording mode °Tα, Td. Therefore, no bass sound is generated in the RF converter.

Finally, we will explain how to extract the video signal input to the synchronization separation circuit.

FIG. 1 shows a configuration in which the video signal during recording is taken from the output of LPF 5, and the video signal during playback is taken from the output from LPF 2+, and after being switched by switch circuit 55, it is input to synchronization separation circuit 57 via LPF 56. Ta.

As shown in FIG. 11, the video signal during reproduction may be taken out from the output of the mixer 28.

In addition, in Figures 1 and 11, the video signal at the time of recording is
Although the output is taken out after the AGC circuit 2, it may be taken out from the output of the AGC circuit 2.

In addition, as shown in FIG.
As shown in the figure, a configuration may be adopted in which the output of the clamp circuit 50 is extracted.

【Effect of the invention〕

As explained above, according to the present invention, the clamp circuit that clamps the video signal in the recording system and the playback system and the video output amplifier that amplifies the video signal to a level of 2 vp-p can be used together, so the circuit can be In addition to being simple, it is possible to eliminate variations in output voltage, and even with a low power supply voltage of 5V class, it is possible to secure a dynamic range of video output of 2 VP-P with plenty of margin, and it is also possible to drive a load such as a monitor TV. The present invention can greatly contribute to lower power consumption and miniaturization of VTRs, and can provide a video signal processing circuit with excellent functions, while eliminating the drawbacks of the prior art described above.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the video signal processing circuit according to the present invention, FIG. 2 is a circuit side diagram of the video output amplifier in FIG. 1, and FIGS. 3 to 6 are shown in the t$2 diagram. Figures 7 and 8 are diagrams of other circuits of the video output amplifier, Figure 9 is a diagram explaining input switching of the video output amplifier, and Figure 10 is a diagram explaining Figure 9. 11 to 15 are block diagrams for explaining how to increase the input signals of the synchronization signal separation circuit. ...Video signal input terminal, 2.AGC circuit, 5.
...LPF, 2B...Mixer, 29...Switch circuit, 50...Clamp circuit, 51...Squelch circuit, 52...Switch circuit, 55...Video output amplifier, 54...・Video signal output terminal, 52-56...Transistor, 57-66...Resistor, 67.68...I
C nohi y, 69-・V T FL no output fi child, 7o
...Monitor TV input terminal, 71, 75...Capacitor, 75...Monitor TV. Tomi Z Zu Atsushi + Zu Ko〉day i ri 2 brown f JL (PF) Tomi 5 Figure # 7 Bin Collection (〃z) Ten thousand figures Iqi number (〃z) Man 7 Figure 10 Figure

Claims (4)

[Claims] (1) In a video signal processing circuit consisting of a recording system and a reproduction system, a video output amplifier that serves both the recording system and the reproduction system, a first switch circuit, a squelch circuit, and a video signal processing circuit that serves as both the recording system and the reproduction system. a clamp circuit and a second switch circuit are provided, the first switch circuit selectively connecting the output of the clamp circuit and the output of the squelch circuit to the input of the video output amplifier; The second switch circuit selectively connects the video signal of the recording system and the video signal of the reproduction system to the input of the clamp circuit, thereby connecting the video signal from the recording system during recording and the video signal from the reproduction system during playback. A video signal processing circuit characterized in that the circuit is configured to be able to obtain a signal from the video output amplifier. (2) In the video signal processing circuit according to claim (1), the video output amplifier has first and second transistors forming a differential amplifier, and a video signal is connected to the base of the first transistor. a DC voltage source is connected to the base of the second transistor, and the emitter of a third transistor whose base is connected to the collector of the second transistor is connected to the base of the second transistor, A video signal processing circuit characterized in that the video signal processing circuit is configured to extract a video signal from the emitter of the third transistor. (3) In the video signal processing circuit according to claim (2), the clamp circuit for clamping the video signal is connected to the base of the first transistor, and the second switch circuit is provided before the clamp circuit. A video signal processing circuit characterized in that: (4) In the video signal processing circuit according to claim (3), one of the DC potentials of the video signal from the recording system and the video signal from the playback system input to the clamp circuit is set higher than the other. A video signal processing circuit characterized in that the circuit is set to.