JPH0659010B2 - FM signal demodulator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a demodulator of a frequency-modulated (hereinafter abbreviated as “FM”) signal, and in particular, it can be operated at a low voltage and can generate a large signal. The present invention relates to an FM signal demodulator used as an output circuit for outputting.

[Background of the Invention]

The output circuit of a conventional demodulator of this type is as follows.
As described in No. 6, the multiplier was used as an output circuit, and the voltage generated in the resistor connected to the power supply was the output of the demodulator. However, in this conventional circuit, (1) the dynamic range of the output becomes stricter as the power supply voltage becomes lower, (2) the size of the output signal cannot be increased, and there is a problem in the signal-to-noise ratio (S / N). There was no consideration for the point.

FIG. 8 shows a conventional FM signal demodulation circuit diagram, and FIG. 9 shows operation waveforms of respective parts thereof. The problems of the prior art will be described below with reference to FIGS. 8 and 9. In FIG. 8, signals having opposite phases to each other are inputted from the FM signal input terminals 1 and 2 as shown by 51 and 52 in FIGS. 9 (a) and 9 (b).
Here, the base potential of the transistors Q24 and Q25 is V _B , and the base-emitter voltage is V _BE . First, the transistor Q
1, Q3 is off, Q2 and Q4 are on, capacitor C1
Is charged and is in a steady state. At this time, the collector potential of Q3 becomes V _CC -V _BE, and the emitter potential of Q4 (collector of Q2) becomes V _CC -2V _BE as indicated by 54 in FIG. 9 (d). Also, the emitter potential of Q3 (collector of Q1) is determined from the emitter potential of Q4 because Q3 is off, and if the voltage across capacitor C1 is ΔV, then as shown at 53 in FIG. _CC- 2V _BE + ΔV
Becomes

Next, when the input FM signals 51 and 52 are inverted at t = t ₁ ,
1 is on, Q2 is off, and the current is Q4, C1, Q1.
, And the emitter potential 53 of Q3 decreases linearly as shown in FIG. 9 (c). At this time, the collector potential of Q4 is Q
It is clamped by 32 and is V _CC -V _BE , and Q3
The base potential is V _B -V _BE. Therefore, when the emitter potential 53 of Q3 where the discharge is continued becomes V _B -2V _BE , Q3
3 is turned on, and the discharge of the capacitor C1 is completed. At this time, t = t ₂ . When t = t ₂ , the moment Q3 turns on Q
Base potential of 4 drops to V _B -V _BE Q4 is turned off. Since the circuit shown in FIG. 8 is not a completely symmetrical circuit, Q1, Q
Fig. 9 shows the state when 3 is on and Q2 and Q4 are off.
This is the same as exchanging the state of t ≦ t ₁ of the waveforms 53 and 54 in (c) and (d) between 53 and 54. That is, the emitter potential of Q3 is V _CC -2V _BE and the emitter potential of Q4 is V _CC -2V _BE.
It becomes + ΔV.

Further, at t = t ₃ , the input FM signals 51 and 52 are inverted again, and Q1
Is turned off and Q2 is turned on, a current flows through Q3, C1 and Q2 and is discharged.

As described above, the circuit shown in FIG. 8 repeats the above-mentioned operation for each cycle, and shows operation waveforms as shown in FIGS. 9 (a), (b), (c) and (d).

By the way, the voltage ΔV across the capacitor C1 in the steady state is
Since Q3 and Q4 are the emitter potential differences of the transistors immediately before switching at t = t ₂ , ΔV = V _CC −2V _BE (V _B −2V _BE ) = V _CC −V _B. Therefore, the potential difference between before and after the discharge of the capacitor is V _CC −2V _BE + ΔV− (V _B −2V _BE ) = 2AV.

Next, paying attention to the states of Q3 and Q4, the emitter potentials of Q5 and Q6 have signal waveforms such as 55 and 56 shown in FIGS. 9 (e) and (f), which are the input FM signal 51, The signal is delayed from 52. The delayed signals 55 and 56 are multiplied by the input FM signals 51 and 52 in the multiplication circuit of the next stage, and Q7, Q8, Q9,
The collector potential of Q10 has signal waveforms such as 57, 58, 59 and 60 shown in (g), (h), (i) and (j) of FIG. Further, if a load resistor 41 is connected to the output terminal 5, a current flows through the terminal 5 only when Q11 or Q14 is turned on, and a signal 61 shown in FIG. 9 (k) is output. That is, only when Q11 or Q14 of the base potentials of 11 to Q14 (collector potentials of Q7 to Q10) is kept at the highest potential, a current flows through the load resistor 41 connected to the terminal 5 and a voltage drop occurs, During the other periods, the power supply voltage is always maintained. That is, the current is I _O ,
If the load resistance is R _L , the discharge period (delay period) is V _CC −
The waveform of the signal 61 is repeated so that it falls to R _L I _O and becomes V _CC for the other period. By the way, since the discharge changes linearly as shown in FIG. 9, the discharge time (= delay time) τ _d (= t ₂ −
t ₁ ), where C is the sum of the capacitances of the capacitors C1 and C2 and I _D is the current of the constant current source, τ _d = (2C · ΔV) / I _D (1) and the output voltage of the terminal The average value of 61 is the input FM
Let the signal cycle be T Therefore, the second term on the right side is proportional to the frequency of the FM signal = 1 / T. FIG. 10 shows the relationship between the average output voltage of the terminal 5 and the frequency of the FM signal. As shown in FIG. 10, the output voltage is linearly changed from V _CC to V _CC -I _O R _L, becomes minimum when the maximum demodulation frequency _max.

As described above, the FM signal demodulation circuit can be realized by the circuit configuration of FIG. 8, but such a conventional circuit has the following problems. That is, the output of the multiplier is connected between the collector of the transistor and the power supply to take out the output voltage. In order to operate the transistor in the circuit in the linear region and secure the output dynamic range, the power supply voltage is , The output signal cannot be increased, and the S /
There was a problem that it was difficult to secure N.

On the other hand, by having an amplifier in an integrated circuit (IC) that constitutes the circuit and amplifying to an appropriate level, it is possible to prevent ripple noise from being mixed in the ground line of the FM signal demodulator, and to suppress S / Although it is conceivable to improve N, however, the demodulator output has a large amplitude including a harmonic signal, and the dynamic range of the amplifier cannot be secured.

[Object of the Invention] An object of the present invention is to solve the above-mentioned problems in the prior art, to provide an output circuit capable of sufficiently increasing the dynamic range even at a low power supply voltage, and to provide a load resistance for an FM signal demodulator output. Another object of the present invention is to provide an FM signal demodulator which can also serve as a load resistance for recording comb filter output during recording.

[Outline of Invention]

In the present invention, in order to achieve the above object, a PNP transistor and an NPN transistor that forms an inverted Darlington amplifier in combination with this transistor are provided at the output of the multiplier of the FM signal demodulator, and the PNP transistor The emitter and the collector of the NPN transistor are connected to each other, and the output signal current is taken out through the inverted Darlington amplifier and converted into an output voltage at a place having a sufficient dynamic range.

Example of Invention

 An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, Q40 and Q41 are PNP transistors, and Q
42 to Q45 are NPN transistors, 34, 38, 39 and 40 are resistors, and other symbols are the same as in the conventional circuit of FIG.

The characteristic of the circuit shown in Fig. 1 is that the output of the multiplier is directly connected to the output resistor 41.
This is because the output signal current is taken out through the inverted Darlington amplifier composed of Q41 and Q42, without being connected to this (also serving as the matching resistor of the low pass filter LPF46).

A constant current source is constituted by Q43 and the resistor 34, and a constant base voltage is supplied to Q41 by this constant current source, the diode Q40 and the resistor 39. The collector voltage of the transistors Q11 and Q14 of the multiplier output is fixed to the emitter voltage of Q41. Here, for example, if the voltage drop of the resistor 38 is set to 0.2V, the resistor 38 is set to 100Ω, and the collector current of Q20 is set to 1mA, the total current flowing through Q11 and Q14 is 1mA when no signal is input, and Q41 and Q42 are Total current flowing is 1mA
Becomes When a signal current flows through Q11 and Q14, the current flowing through the resistor 38 is always 2 mA. Therefore, a signal current having the same value as that of the signal current but having the opposite polarity flows through Q41 and Q42. In this way, the signal current flows back to the ground potential side in the inverted Darlington amplifier. Next, if Q44 and Q45 are made to have a current mirror structure as shown in the figure, the signal current returned to the ground potential side will be returned to the power supply voltage side again via Q45 forming the current mirror. Then, the signal voltage is output to the output terminal 5. Of course, since Q44 and Q45 are current mirrors,
It goes without saying that current can be amplified by connecting a resistor between the grounds.

For example, if a signal having a magnitude of 0.5 V _pp is to be obtained as an output signal, harmonic components are added and a signal having a magnitude of about 2.5 V _pp is output as a multiplier output signal. 2.
In order to take out a signal as high as 5 V _pp to the output, in an IC where the constant power supply voltage is being advanced (for example, portable V
In the case of TR, V _CC = 5V), and it is difficult to take out the signal directly from the multiplier output as in the conventional case. By taking out the signal current of the multiplier output through the inverted Darlington amplifier as in this embodiment. A circuit with a sufficient dynamic range can be constructed, and a signal voltage of 2.5 V _pp can be taken out. Further, according to this embodiment, current amplification is performed by using a current mirror in the output stage, and a signal voltage with sufficiently good S / N can be obtained.

Another feature of the circuit of this embodiment is that the resistors 35, 32, Q26
Is to supply the base voltage of Q20 and Q43 with the bias circuit constructed in (4). That is, when the collector current of Q20 is to be increased, if the current flowing through Q41 and Q42 is not increased, a large signal current will not flow and the output signal will be distorted. Further, it is important to externally attach the output resistor 41 and the maximum demodulation sensitivity adjusting resistor 35. For temperature characteristics, it is better to enclose the resistors 41 and 35 in the IC as well, but to output the demodulated output generated in the resistor 41 to the outside of the IC with an emitter follower is necessary for matching with the LPF46. This results in a loss of 6 dB, which is a problem in securing S / N of a small amplitude signal. However, if the emitter follower is removed and the output is directly output from the resistor 41 to the outside of the IC, the variation in absolute value of the resistor 41 becomes ± 30%, and it cannot be used as a matching resistor of the LPF 46. For the above reason, the resistor 41 is an external resistor. At this time,
Considering the variation of the output signal voltage and the temperature characteristic, it is preferable that the resistor 35 is also externally attached.

The reason why the inverted Darlington configuration is used in FIG. 1 is as follows. If only Q41 is used without Q42, a current of 1 mA flows through Q41 when no signal is input.
At this time, the input impedance of the emitter of Q41 is about 26.
It becomes Ω. Therefore, in this state, the small signal current is Q11Q.
When flowing through the collector of 14, the signal current is distributed by the input impedance of the resistor 38 and the emitter of Q41, of which {100Ω / (100 + 26) Ω} × 100 = 80 (%)
Flows, and 20% flows on the resistance 38 side. On the other hand, Q
When the current flowing through 11 and Q14 becomes 1.5mA, Q41
A current of 0.5mA flows through the Q41, and the impedance of Q41 with respect to a minute signal current is about 52Ω.
The current will flow. In this way, the input impedance of the emitter of Q41 greatly changes with respect to the bias current, so that the ratio of the current flowing through the collector of Q41 greatly changes.

On the other hand, in the inverted Darlington configuration,
Since the current across Q42 is controlled by the voltage (about 0.7 V) generated across the resistor 40, there is an equivalent effect of significantly reducing the input impedance. For example, if the resistance 40 is 7 kΩ, the base-emitter voltage of Q42 is almost
Since it is 0.7 V, a current of about 0.1 mA will flow. Therefore, when there is no signal input, of the current of 1 mA that flows into Q41 and Q42, approximately 0.1 mA will flow to the Q41 side and the remaining 0.9 mA will flow to the Q42 side. . At this time, the conductance gm of Q42 is about
Since the input impedance of 34 mν and Q41 is 260 Ω, the current ΔI flowing with respect to the minute voltage change ΔV of the emitter is expressed by the following equation.

Therefore, the input impedance R _in is Therefore, of the signal currents of Q11 and Q14, Flows on the inverted Darlington side.

On the other hand, when a current of 0.5 mA flows to the inverted Darlington side, the base-emitter voltage of Q42 is almost the same as when it is 1 mA.
0.4mA flows. Therefore, the input impedance R _{in at} this time is as follows, considering the same as described above.

Therefore, at this time, of the signal currents of Q11 and Q14, Flows on the inverted Darlington side. In this way, when the currents flowing in Q11 and Q14 are 1 mA and 0.5 mA, the difference in the current flowing in the inverted Darlington side is only 1%, which significantly reduces the occurrence of waveform distortion. You can

FIG. 2 shows a circuit diagram of another embodiment of the present invention. The difference from FIG. 1 is that without using a current mirror in the output section,
The point is that the LPF 46 is driven directly from the inverted Darlington amplifier. It goes without saying that the same effect as the embodiment shown in FIG. 1 can be obtained.

FIG. 3 shows a circuit diagram of still another embodiment of the present invention. In this, the output signal current of the multiplier is taken out by a current mirror composed of a PNP transistor, is further returned to the power supply voltage side by an NPN current mirror, and a signal voltage is output to an output terminal 5. The emitter size of the transistor in the case of FIG. 3 may be arbitrarily selected.

4 and 5 are circuit diagrams of still another embodiment of the present invention, respectively, which is different from FIG. 3 in that an inverted Darlington circuit is added to the PNP current mirror.

FIG. 6 shows an example of a VTR system using the FM signal demodulator of the present invention. This is because the servo control method is Automatic Track Find (Automatic Track Find).
ing, hereinafter abbreviated as ATF) A method for frequency-multiplexing a signal for control method (hereinafter, referred to as a pilot signal) with a video signal (for example, for reducing low-pass conversion chroma signal), and frequency modulation for an audio signal. FIG. 3 is a block diagram of a VTR equipped with a method of frequency multiplexing with a video signal (for example, multiplexing between an FM luminance signal and a low frequency conversion chroma signal).

First, the basic configuration of FIG. 6 will be described. During recording, the switch circuits 205, 266 and 120 are contact points 101, 103 and 121, respectively.
Connected to. The composite video signal input from the input terminal 201 is feedback-controlled by the AGC circuit 202 via the AGC detection circuit 200 so that the input signal of the pre-emphasis circuit 212 becomes a specified level. The output of the AGC circuit 202 is a switch circuit. After being clamped by the clamp circuit 267 via 266, it is amplified by the video output amplifier 268 and output to the video output terminal 269.

On the other hand, the composite video signal whose level is controlled by the AGC circuit 202 is a Y composed of a trap 203, subtraction amplifiers 204 and 208, a switch circuit 2051H delay line 206, and addition amplifiers 207 and 209.
A / C separation circuit A (details of which will be described later) separates the luminance signal and the chroma signal. The separated luminance signal is band-limited by the LPF 210 via the switch circuit 120, and the waveform is pre-shot so that the energy clipped by the recording equalizing circuit 211 is reduced. Next, after the high-frequency signal is emphasized by the nonlinear and linear emphasis circuit 212, it is modulated by the frequency modulation circuit 214 via the clip circuit 213 for avoiding overmodulation. After that, A with HPF215
The pilot signal for TF, the voice signal, and the low-frequency conversion chroma signal component are removed and the result is supplied to the adder 216.

On the other hand, the chroma signal separated by the Y / C separation circuit A is supplied to the BPF 220 via the switch circuit 219 to remove unnecessary signals, and a recording chroma processing circuit 221 including at least an ACC circuit, a burst emphasis circuit and a chroma emphasis circuit. Is subjected to recording chroma processing by the reference carrier generator 222 and frequency conversion circuit 223 for low-frequency conversion. Further, after unnecessary components are removed by the LPF 224 and the trap 225, they are supplied to the adder 230.

Further, the audio signal input from the audio signal input terminal 226 is passed through a noise reduction circuit 227 including an emphasis circuit for improving S / N and a compression circuit for compressing the audio signal according to the amplitude to reduce crosstalk. The frequency modulation circuit 228 produces an FM audio signal, which is supplied to the adder 230. On the other hand, the pilot signal generator 229 supplies the ATF pilot signal to the adder 230.

The three signals added by the adder 230 are further added by the adder 216.
Is added with the above luminance FM signal. Then, it is amplified by a recording amplifier 231 having a constant current characteristic and recorded on a magnetic tape 233 via a video head 232.

During playback, the switch circuits 205, 266, and 120 each have contact 1
It is connected to 02, 104, 122. The signal reproduced from the video head 232 is amplified by the reproduction amplifier circuit 251. HPF2
52 extracts only the luminance FM signal from the amplified reproduction signal and sends it to the peaking circuit 253. The peaking circuit 253 compensates the transmission characteristics of the tape head system, the AGC circuit 254 controls to a specified level, and the limiter circuit 255 shapes the waveform. The waveform-shaped signal is demodulated by the demodulation circuit 256,
After passing through the switch circuit 120 and the LPF 210, the de-emphasis circuit 257 for restoring the emphasis performed in recording is sent. Then, the reproduction processing is performed in the de-emphasis circuit 257, the high frequency noise component is suppressed in the noise cancellation circuit 258, and then the signal is supplied to the adder 265.

On the other hand, the low frequency conversion chroma signal is transmitted to the trap 259 and LPF2.
After being taken out at 60 and reproduced by the reproduction chroma processing circuit 261 including at least the ACC circuit and the burst de-emphasis circuit, the reference carrier generator 222 and the frequency conversion circuit 262 restore the original carrier color signal. After that, the signal is sent to a regenerative C-shaped comb filter composed of a 1H delay line and a subtraction amplifier 208 through a spurious eliminating BPF 263 and a switch circuit 205 to remove adjacent crosstalk, and a regenerative chroma processing circuit 264 including at least chroma deemphasis. Regeneration processing is performed and the result is supplied to the adder 265. The reproduction signal that is added to the luminance signal that has been subjected to the reproduction processing described above by the adder 265 and becomes a composite video signal is the switch circuit 26.
After being clamped by the clamp circuit 267 via 6, it is amplified by the video output amplifier 268 and output to the video output terminal 269.

The audio FM signal is extracted by the BPF 270 from the reproduction signal output from the reproduction amplification circuit 251, and demodulated by the demodulation circuit 271. After that, a noise reduction circuit 272 including at least an LPF, a decompression circuit, and de-emphasis removes spurious components, and decompression restores the decompression performed during decompression and decompression performed to restore the compression performed during recording. Reproduction processing is performed and the sound is output from the audio output terminal 273.

Further, of the reproduction signals output from the reproduction amplifier circuit 251, only the pilot signal is extracted by the BPF 274 and output from the pilot signal output terminal 273. This pilot signal is used as an ATF control signal.

Although the basic recording / reproducing mode of FIG. 6 has been described above, the characteristic of the circuit of FIG. 6 is that the LPF 210 is used for both recording and reproduction. An example of a specific circuit for this purpose will be described with reference to FIG. In FIG. 7, reference numeral 800 is a recording comb filter circuit, 600 is an FM demodulation circuit, and 300 is an amplification circuit at the time of recording. Each circuit is conventionally used and will not be described in detail. The characteristic of FIG. 7 is the LPF.
210 matching resistors are recorded Comb filter output and FM
That is, the output is also used for the signal demodulator. That is, the collector and F of the recording comb output transistor Q820
The collector of the M modulator output transistor Q664 is connected, and the matching resistors of the LPF 210 connected between the power supply voltages are used as load resistors. Q when recording
A high potential is supplied to the base of 656, the current of the FM demodulator does not flow, and Q664 cuts off. Also, during playback,
A high potential is supplied to the base of Q803, the current in the recording comb circuit does not flow, and Q820 cuts off. As described above, the load resistance can be shared between recording and reproduction. However, the gain of the recording comb amplifier is 822
And the load resistance outside the IC, the temperature compensation becomes a problem. Therefore, as shown in FIG. 7, a grounded base amplifier composed of a transistor Q364 is provided after the LPF 210, and the gain is determined by the resistance R1 outside the IC and the resistance R363 inside the IC. Perform temperature compensation of the circuit.

〔The invention's effect〕

According to the present invention, it is possible to realize an output circuit that can sufficiently secure a dynamic range even at a low power supply voltage, improve the S / N of the demodulator output, and load the FM signal demodulator output. The resistance, the load resistance for the recording comb filter output at the time of recording, and the LPF having this load resistance as a matching resistance can be used for both recording and reproduction.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS. 2, 3, 4, and 5 are circuit diagrams of other embodiments of the present invention, respectively.
FIG. 6 is a circuit configuration diagram of a VTR using the present invention, FIG. 7 is a partial concrete circuit diagram in FIG. 6, FIG. 8 is a circuit diagram showing an example of a conventional FM demodulator, and FIG. Is a waveform diagram of each signal in FIG. 8, and FIG. 10 is an average output voltage of terminal 5 and F in FIG.
It is a figure which shows the relationship with M signal frequency. <Description of symbols> 1, 2 ... FM signal input terminal 35 ... Maximum demodulation voltage adjustment resistance 44 ... Maximum demodulation frequency adjustment resistance 41, 42 ... LPF matching resistance Q40, Q41 ... PNP transistor Q42 ... Q45 …… NPN transistor

Claims (1)

[Claims] 1. An FM signal demodulator comprising a delay circuit for delaying an input signal and a multiplier for multiplying the output signal of the delay circuit and the input signal, wherein an output resistance of the multiplier is NPN type. The first transistor is connected to the collector of the first transistor and the emitter of the second transistor of PNP type, the base of the first transistor is connected to the collector of the second transistor, and this connection is connected through a resistor to the first transistor. The third which is connected to the emitter and constitutes a current mirror circuit
And a common base end of the fourth transistor is connected to the collector of the third transistor and the emitter of the first transistor, and a demodulated output is obtained from a resistor connected between the collector of the fourth transistor and the power supply. The collector of the fifth transistor constituting the output circuit of the recording comb filter is also connected to the connection between the resistor connected between the collector of the fourth transistor and the power supply and the collector of the fourth transistor. An FM signal demodulator having a resistance for both recording and reproduction.