JPS62143505A - Fm signal demodulator - Google Patents

Abstract

PURPOSE:To enlarge fairly the dynamic range of an FM signal demodulator by installing a pnp transistor and npn transistor which constitutes an inverted Darlington amplifier together with the pnp transistor to the output section of the multiplier of the demodulator. CONSTITUTION:The output of a multiplier is not connected with an output resistance 41 directly, but its output signal current is taken out through an inverted Darlington amplifier composed of a pnp and npn transistor Q41 and Q42. An npn transistor Q43 and resistance 34 constitute a constant-current source and a fixed base voltage is supplied to the pnp transistor Q41 by means of the constant-current source and a diode Q40 and resistance 39. The collector voltages of transistors Q11 and Q14 which are the output of the multiplier are fixed to the emitter voltage of the pnp transistor Q41 and the signal current is turned back and made to flow to an earth potential side at the inverted Darlington amplifier. The signal current is again turned back and made to flow to the supply voltage side through a transistor 45 constituting a current mirror and outputted to an output terminal 5.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a demodulator for frequency modulation (hereinafter abbreviated as FM) signals, and has a special feature in that it can be operated at low voltage and can handle large signals. fi' as an output circuit that outputs
Regarding an M signal demodulator.

[Background of the invention]

The conventional output circuit of this type of demodulator is the Japanese Patent Publication No. 5B-51
As described in No. 446, the multiplier is used as an output circuit, and the voltage generated across the resistor connected to the power supply is 01
It was the output of the lAl device.

However, in this conventional circuit, as the power supply voltage becomes lower, the dynamic wrench of the output becomes more difficult.

(2) No consideration was given to two points: the inability to increase the size of the output signal and the problem with the signal-to-noise ratio (S/#).

FIG. 8 shows a diagram of a conventional FM signal demodulation circuit, and FIG. 9 shows operating waveforms of each part thereof. Figure 8 below.

The problems of the prior art will be described with reference to FIG.

In Fig. 8, the FM signal input terminals 1 and 2 are connected to each other as shown at 51.52 in Fig. 9 (αl, (hl).
Signals having a negative phase relationship at 5° are input. Here, the base potential of transistors 024 and 025 is VB, and the base-emitter voltage is VBx c! :do. First, transistor 0
1,03 are off, C2, C4 are on, capacitor C1
Assume that is charged and in a steady state. At this time, since the collector potential of C3 becomes VCC-VEE, the emitter potential of 04 (collector of C2) becomes FCC-2VBE as shown at 54 in FIG. 9[d]. Also, Q! Since C3 is off, the emitter (collector of 01) potential is C
4, and if the voltage across the capacitor C1 is ΔV, then VC
It becomes C-2VBIt+ΔV.

Next, when the input FM signal 51.52 is inverted at t - tl, Ql is turned on and l'22 is turned off, and the current is 04.52.
CI, (1) 1 flows, and the emitter potential 53 of C5 decreases linearly as shown in FIG. 9, 1ty+.

At this time, the collector potential of C4 is clamped by Q32 and is VCCVBE, and the base potential of C3 is VB VBE. Therefore, when the discharge continues and the emitter potential 53 of C3 reaches VB2VEE, C6 turns on and the discharge of the capacitor C1 ends. At this time, 1 = 1! shall be. At 1-1°, C
The moment Q4 turns on, the base potential of Q4 drops to VB-VBII and C4 turns off. Since the circuit shown in Figure 8 is not a completely symmetrical circuit, the state when Q1pQ3 is on and C2 and C4 are off is as shown in Figure 9 (cl, (53.54 of di).
This is the same as exchanging the state of t≦t of the waveform between 53 and 54. In other words, the emitter potential of C3 is VCC
”'-2VBII s The emitter potential of Q4 is FC
C-2V ER+ΔV.

Sarabanko 1. -13, the input FM signal 51.52 is inverted again, Ql is off and C2 is on, the current is C3, C1
, C2 and discharge.

As described above, the circuit shown in FIG. 8 repeats the above-mentioned operation every cycle, and the circuit shown in FIG. 9 (αl, (Al, (cl).

Is the voltage ΔV the emitter potential difference between both transistors immediately before C3 and C4 switch at t - zt? ΔV=Vcc
2Vnx (FB-2Vnx)=Vcc-Vrr
becomes. Therefore, the potential difference between the time before the capacitor starts discharging and the time when it ends is VCC2VBE+ΔV ('B-2Vnx)-2AV.

Next, the emitter potentials of C5 and C6 should be determined by paying attention to the state of C3+Q'.
The signal waveform becomes as follows, which is the input FM signal 51.5
2 is delayed. This delayed signal 55.5
6 is multiplied by the input FM signal 51.52 in the next stage multiplication circuit, resulting in Qy, Qa, )9. The collector potential of qlo is (q) in Figure 9, (AI, fLl, I, i
The signal waveforms are 57.5B and 59.60 shown in 1.

Furthermore, if a load resistor 41 is connected to the output terminal 5, the terminal 5
A current flows only when Q1] or Q14 is turned on, and a signal 61 shown in FIG. 9 is output. That is, the base potentials CQ7 to Q of Q1) to Q14
Q 1) or Q 14 of 10 collector potentials)
Only when is kept at the highest potential, current flows through the load resistor 41 connected to the terminal 5, causing a voltage drop, and is always kept at the power supply voltage during other periods. In other words, if the current is I and the load resistance is RL, the discharge period (delay period) is VCC
-RLIO, and repeats the waveform of the signal 61 such that it becomes FCC during other periods. By the way, since the discharge changes linearly as shown in Figure 9, the discharge time (-delay time) τ
Bar 1. -1. ) is τ, <-(
2C・ΔV)/ID ・・・・・・+11,
Further, the average value of the output voltage 61 of the terminal 5 is 4ΔV, RLCI, where T is the period of the input FM signal.

VDC='CC-×1. ””” becomes +21,
The second term on the right side is proportional to the frequency f-1/7'' of the FM signal. Figure 10 shows the relationship between the average output voltage of terminal 5 and the frequency of the FM signal. As shown in Figure 10, The output voltage varies linearly from VCC to VCC-IoRL, and is minimum at the maximum demodulation frequency frn.

As described above, an FM signal demodulation circuit can be realized with the circuit configuration shown in FIG. 8, but such a conventional circuit has the following problems. In other words, as the output of the multiplier, a resistor is connected between the collector of the transistor and the power supply to extract the output voltage. Furthermore, the output signal cannot be increased, and the signal S/
There was a problem that it was difficult to secure N.

On the other hand, by having an amplifier in the integrated circuit (IC) that makes up the circuit and amplifying it to an appropriate level, it is possible to prevent ripple noise from entering the ground line of the FM signal demodulator, and to prevent ripple noise from entering the ground line of the FM signal demodulator. It is possible to improve N, but since the demodulator output includes large harmonic signals, it is difficult to ensure a dynamic range.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an FM signal demodulator equipped with an output circuit that can solve the above-mentioned problems in the prior art and can sufficiently widen the dynamic range even at low power supply voltages.

[Summary of the invention]

In order to achieve the above object, the present invention provides the output section of the multiplier of the FM signal demodulator with a PNP transistor and an NPN transistor that forms an inverted Darlington amplifier in combination with this transistor.
The emitter of the transistor is connected to the collector of the NPN l transistor, and the output signal current is taken out through this inverted Darlington amplifier and converted into an output voltage within a sufficient dynamic range.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, C40 and C41 are PNP transistors, Q42 to Q45 are NPN l-transistors, and 34
38 and 39.40 are resistances, and the other symbols are the same as in the conventional circuit shown in FIG.

The feature of the circuit in Figure 1 is that the output of the multiplier is directly connected to the output resistor 4.
1 (this also serves as a matching resistor for the low-pass filter LPF46), and the output signal current is taken out through an inverted Darlington amplifier composed of 041.042. be.

Q43 and resistor 34 constitute a constant current source, and this constant current source, diode Q40, and resistor 39,
A constant base voltage is supplied to Q41.

The collector voltage of multiplier output transistors 011 and 014 is fixed to the emitter voltage of Q41. Here, for example, if the voltage drop across the resistor 38 is 0.2V, then the voltage drop across the resistor 38 is 1V.
000, if the collector current of Q20 is set to 1 mA, 011. The total current flowing through C14 is 1 mA, and the total current flowing through C41 and C42 is also 1 mA. 013. ') When a signal current flows through 14, the current flowing through resistor 3 is always 2 mA, so a signal current with the opposite polarity and the same value as this signal current flows through 041. C4
It will flow to 2. In this way, the signal current flows back to the ground potential side in the inverted Darlington amplifier. Next, if Q44 and 045 are configured as a current mirror as shown in the figure, the above signal current that has been turned back to the ground potential side will be turned back to the power supply voltage side via Q45 that constitutes the current mirror. As a result, a signal voltage is output to the output terminal 5. Of course, 044. Since Q45 is a current mirror, it goes without saying that current can be amplified by connecting a resistor on the emitter side of the transistor or between the emitter and ground.

For example, if you are trying to obtain a signal with a magnitude of 0.5 Vpp as an output signal, harmonic components will be added, and approximately 2,
A signal with a magnitude of 5 V is output as the multiplier output signal. In order to output a signal as high as 2.5 Vpp, it is necessary to use (
For example, for portable VTR compatible Vcc -5V),
It is difficult to extract the signal voltage directly from the multiplier output as in the conventional method, but by extracting the signal current of the multiplier output through an inverted Darlington amplifier as in this embodiment, a circuit with a sufficient dynamic range can be created. Can be configured,
It is also possible to extract a signal voltage of 2.5 VPp.

Further, according to this embodiment, current amplification is performed by using a current mirror in the output stage, and a signal voltage with sufficiently good S/H can be obtained.

Another feature of this example circuit is that the resistance is 35°32,
Q20 and Q4 with a bias circuit composed of Q26
It is to supply a base voltage of 3. In other words, Q 2
When trying to make the collector current 0, Q41. Q4
If the current flowing through 2 is not made uniform, a large signal current will not flow and the output signal will be distorted. In addition, the output resistor 41. It is important to provide the maximum demodulation sensitivity adjustment resistor 35 externally. For temperature characteristics, resistor 41.3
5 is also preferably contained within the IC, but outputting the demodulated output generated at the resistor 41 to the outside of the IC using an emitter follower is difficult due to matching with LFF 46.
This results in a loss of 6 dE per 1 dE, which is a problem in securing the S/N ratio for small amplitude signals. However, if the emitter follower is removed and the output is directly output from the resistor 41 to the outside of the IC, the absolute value of the resistor 41 will vary by ±30 inches, making it impossible to use it as a matching resistor for the LP146. For the above reasons, the resistor 41 is an external resistor. At this time, in consideration of variations in the output signal voltage and temperature characteristics, it is preferable that the resistor 35 is also provided externally.

The reason why the inverted Darlington configuration is used in FIG. 1 is as follows. Now, if Q42 is not provided and only Q41 is used, a current of 1 mA flows through Q41 when no signal is input. At this time, the input impedance of the emitter of Q41 is approximately 260.

Therefore, when a small signal current flows through the collectors of 013 and 014 in this state, the signal current is divided by the input impedance of the resistor 38 and the emitter of Q41, and
On the 41 side, (100rV' (100+26)
Ω)Xi 0O=80 (chi) flows, and 2 is on the resistor 38 side.
0chi flows. On the other hand, when the current flowing through 011,014 becomes 1.5mA, 0.5mA flows into Q41.
Since a current of mA flows and the impedance of Q41 with respect to the minute signal current is approximately 520, a current of approximately 67 cm flows on the Q41 side. In this way, Q41
Since the input impedance of the emitter of Q41 changes significantly with respect to the bias current, the proportion of current flowing to the collector of Q41 changes significantly.

In contrast, in the inverted Darlington configuration,
Due to the voltage (approximately 0.77) generated across the resistor 40,
Since the current in Q42 is controlled, the effect is that the input impedance is significantly reduced under equal constraints. for example,
If the resistor 40 is 7xΩ, the voltage between the base and emitter of Q42 is approximately 0.7V, so a current of approximately 0.1+aA will flow. Therefore, when no signal is input, Q41
．． Of the current 1rnA flowing into Q42, approximately 0.1m
A will flow through the Q41 side, and the remaining 0.9mA will flow through the Q42 side. At this time, Q 42 conductance h
is about 34 mv, and the input impedance of 041 is 26
Since 0Ω, the current ΔI flowing with respect to the minute voltage change Δr in the emitter section is expressed by the following equation.

ΔV Δz = 26, ('+7'ΩKou'-
xl 0O-99 (ch) 100Ω+1.10 flows on the inverted Darlington side.

On the other hand, when a current of 0.5 mA flows to the inverted Darlington side, the base-emitter voltage of Q42 needs to be approximately the same as when it is 1 mA, so Q41
0.1mA flows to Q42, and 0.4mA flows to Q42. Therefore, the input impedance Ri at this time is considered as follows in the same manner as described above.

R,,,260wa2,4Ω Ln 1+7. .OMEGA. In this way, when the current flowing through Qu and Qu is 1 mA and 0.5 mA, the proportion of current flowing to the inverted Darlington side differs by only 1 inch, which greatly reduces the occurrence of waveform distortion. can do.

FIG. 2 shows a circuit diagram of another embodiment of the present invention.

The difference from FIG. 1 is that the L P F 46 is directly driven from an inverted Darlington amplifier without using a current mirror in the output section. Needless to say, this embodiment has the same effects as the embodiment shown in FIG.

FIG. 6 shows a circuit diagram of still another embodiment of the present invention. This takes out the multiplier output signal current using a current mirror made up of PNP transistors, returns it to the power supply voltage side using an NPH current mirror, and outputs the signal voltage to the output terminal 5. The emitter size of the transistor in the case of FIG. 6 may be arbitrarily selected.

4 and 5 are circuit diagrams of still other embodiments of the present invention, which differ from FIG. 3 in that an inverted Darlington circuit is added to the PNP current mirror.

FIG. 6 shows an example of a VTR system using the FM signal demodulator of the present invention. This is because the servo control method is automatic track finding (A, Lto, atit).
, Tratyk Finding (hereinafter abbreviated as ATF)
There are two methods: frequency-multiplexing the Isa signal (hereinafter referred to as the pilot signal) for the control method with the video signal (for example, multiplexing it on the low frequency of the low-frequency conversion chroma signal), and one method that frequency-modulates the audio signal and converts it into the video signal. 1 is a block diagram of a VTR equipped with a frequency multiplexing method (for example, multiplexing between an FM luminance signal and a low frequency converted chroma signal); FIG.

First, the basic configuration shown in FIG. 6 will be explained.

Switch circuits 205, 266, 120 during recording
are connected to contacts 101, 103, and 121, respectively. The composite video signal input from the input terminal 201 is feedback-controlled via the AGC detection circuit 200 so that the input signal of the pre-emphasis circuit 212 becomes a specified level in the AGC circuit 202, and the output of the AGC circuit 202 is as follows.
After being clamped by a clamp circuit 267 via a switch circuit 266, it is amplified by a video output amplifier 268 and output to a video output terminal 269.

On the other hand, the composite video signal controlled to a specified level by the AGC circuit 202 is sent to the trap 203. Subtraction amplifier 204, 2
08, switch circuit 205. A Y/C separation circuit A (details will be explained later) consisting of an IH delay line 206 and summing amplifiers 207 and 209 separates the signal into a luminance signal and a chroma signal. The separated luminance signal is sent to switch circuit 1
The waveform is band-limited by the LPF 210 via the LPF 20, and the waveform is pre-sheeted by the recording equalization circuit 211 so that the clipped energy is reduced. Next, after the high-frequency signal is emphasized by a nonlinear and linear emphasis circuit 212, it is modulated by a frequency modulation port [214] via a clip circuit 213 to avoid overmodulation. After that, HPF
At step 215, the pilot signal for ATF, the audio signal, and the low frequency conversion chroma signal components are removed and the signal is supplied to an adder 216.

On the other hand, the chroma signal separated by the Y/C separation circuit A is supplied to the EPF 220 via the switch circuit 219, where the negative signal is removed and the chroma signal is sent to the recording chroma processing port, which is composed of at least an ACC circuit, a burst emphasis circuit, and a chroma emphasis circuit. j1g 221 performs recording chroma processing, and a reference carrier generator 222 and frequency conversion circuit 2
23 for low frequency conversion. Furthermore, after unnecessary components are removed by the L P F 224 and the trap 225, the adder 23
0.

In addition, the audio signal input from the audio signal input terminal 226 is processed through a noise reduction circuit IM 227 consisting of an emphasis circuit to improve the S/N and a compression circuit that compresses the audio signal according to the amplitude to reduce crosstalk. Through,
The frequency modulation circuit 228 converts it into an FM audio signal, and the adder 2
60. On the other hand, the pilot signal generator 229
A pilot signal for the ATF is supplied to the adder 230.

The three signals added by adder 230 are further added to the previous luminance FM signal by adder 216.

Thereafter, the signal is amplified by a recording amplifier 231 having constant current characteristics, and recorded onto a magnetic tape 233 via a video head 232.

During playback, switch circuits 205, 266, 12
0 are connected to contacts 102, 104, and 122, respectively.

The signal reproduced from the video head 232 is amplified by a reproduction amplification circuit 251. The HP F 252 extracts only the luminance FM signal from the amplified reproduction signal and sends it to the peaking circuit 8253. A peaking circuit 253 compensates for the transmission characteristics of the tape head system, an AGC circuit 254 controls the signal to a specified level, and a limiter circuit 255 shapes the waveform. The waveform-shaped signal is demodulated by a demodulation circuit 256 and sent to a switch circuit 12o.

The signal is sent via the LPF 210 to a de-emphasis circuit 257 that undoes the emphasis applied during recording.

Then, a de-emphasis circuit 257 performs reproduction processing, and a noise cancellation circuit 258 suppresses high-frequency noise components, and then the signal is supplied to an adder 265.

On the other hand, the low frequency converted chroma signal is transmitted by trap 259 and L
After being extracted by the P F 260 and subjected to reproduction processing by a reproduction chroma processing circuit 261 consisting of at least an ACC circuit and a burst de-emphasis circuit, the original carrier color signal is restored by a reference carrier generator 222 and a frequency conversion circuit 262. Ru. After that, E P F 2 for spurious removal
6'5. The signal is sent through a switch circuit 205 to a regenerative C-comb filter consisting of a 1H delay line and a subtracting amplifier 208.
Adjacent crosstalk is removed, reproduction processing is performed in a reproduction chroma processing circuit 264 including at least chroma de-emphasis, and the signal is supplied to an adder 265 .

The reproduced signal, which is added to the luminance signal subjected to the above-described reproduction processing in the adder 265 and becomes a composite video signal, is clamped by a clamp circuit 267 via a switch circuit 266, and then amplified by a video output amplifier 268. Video output terminal 26
9.

Further, the audio FM signal is extracted from the reproduced signal outputted from the reproduction amplification port k1g 251 by the B P F 270 and modulated by 41 by the demodulation circuit 271. Thereafter, a noise reduction circuit 272 consisting of at least an LPF, an expansion circuit, and a de-emphasis removes spurious components, and decompression is performed to restore the compression performed during recording, and de-emphasis is used to restore the emphasis performed during recording to its original state. A playback process is performed to restore the sound, and the sound is output from the audio output terminal 273.

Furthermore, only the pilot signal is extracted by the BPF 274 from the reproduced signal output from the regenerative amplifier circuit 251,
The pilot signal is output from the pilot signal output terminal 273. This pilot signal is used as an ATF control signal.

The basic recording/reproducing mode shown in FIG. 6 has been explained above, and the feature of the circuit shown in FIG. 6 is that the LPF 210 is used for both recording and reproducing. An example of a specific circuit for this purpose will be explained using FIG. 7. In FIG. 7, 800 is a recording comb filter circuit, 600 is an FM demodulation circuit, 3
00 indicates an amplifier circuit during recording. Each circuit is conventionally used and will not be described in detail. A feature of FIG. 7 is that the matching resistor of the LPF 210 is used for both the recording comb filter output and the LPF output.

That is, the collector of the recording comb output transistor Q820 and the collector of the FM demodulator output transistor Q664 are connected, and the matching resistors of the LPF 210 connected between the power supply voltages are used as load resistors. During recording, a high potential is supplied to the base of Q656, and F
No current flows through the M demodulator and Q664 is cut off.

Furthermore, during reproduction, a high potential is supplied to the base of Q803, no current flows through the recording comb circuit, and Q820 is cut off. In the manner described above, the load resistance can be used for both recording and reproduction. However, since the gain of the recording comb amplifier is determined by the ICC low resistance 822rc external load resistance, temperature compensation becomes a problem. Therefore, as shown in FIG. 7, a common base amplifier consisting of a transistor Q364 is provided after the L PF 210, and the ICC low resistance R1
Temperature compensation of the comb circuit is performed by configuring the ICC low resistance R566 gain to be determined.

〔Effect of the invention〕

According to the present invention lζ, it is possible to realize an output circuit that can sufficiently secure a dynamic range of 23 degrees even at a low power supply voltage, and it is possible to improve the S/N ratio of the demodulator output.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 6, 4, and 5 are circuit diagrams of other embodiments of the present invention, FIG. 6 is a circuit configuration diagram of a VTR using the present invention, and FIG. 7 is a part of FIG. 6. A specific circuit diagram, Fig. 8 is a circuit diagram showing an example of a conventional FM demodulator, Fig. 9 is a waveform diagram of each part of the signal in Fig. 8, and Fig. 10 is an average output voltage of terminal 5 in Fig. 8. It is a figure showing the relationship between a value and an FM signal frequency. Explanation of symbols> 1.2... FM signal input terminal 35... Maximum demodulation frequency adjustment resistor required... Maximum demodulation frequency adjustment resistor 41.42... LPF matching resistor Q40. Q41
...pNp 1-transistor Q42-Q45...
NPN transistor 19 Diagram crown + O diagram procedural amendment (method) Display of the case Showa 60 Patent Application No. 282805 Person making the amendment Relationship with the case Patent application Person name Title
(510) Hitachi, Ltd.
Target of human correction.

Claims (3)

[Claims] (1) In an FM signal demodulator consisting of a delay circuit that delays an input signal and a multiplier that multiplies the output signal of this delay circuit and the input signal, the output resistance of the multiplier is set to NPN.
The base of the first transistor is connected to the collector of the second transistor, and this connection is connected to the first transistor through a resistor. the common base end of the third and fourth transistors constituting the current mirror circuit is connected to the collector of the third transistor and the collector of the first transistor; An FM signal demodulator characterized in that the demodulated output is obtained from a resistor connected between a collector and a power source. (2) Connecting the base of the second transistor to the base and collector of a fifth transistor of the same conductivity type as the second transistor, and disposing a constant current source between this connection and ground; The emitter of the transistor is connected to a power supply for driving the demodulator through a resistor, the base of the sixth transistor constituting the constant current source, and the base of the seventh transistor constituting the constant current source of the multiplier. 2. The FM signal demodulator according to claim 1, further comprising potential adjusting means for connecting and variably adjusting the potential of this connecting portion. (3) The collector of the eighth transistor constituting the output circuit of the recording comb filter is also connected to the resistor connected between the collector of the fourth transistor and the power source, and the collector is connected to the resistor connected between the collector of the fourth transistor and the power supply. 3. The FM signal demodulator according to claim 1, wherein the FM signal demodulator is used for both recording and reproduction.