JPS61242398A - Josephson storage circuit - Google Patents

Abstract

PURPOSE:To attain a high degree of integration of a Josephson storage circuit by forming a groove on a silicon substrate with two Josephson junctions holding the groove between them, forming a ground plane and a lower electrode along the groove and providing an upper electrode on an insulated layer after filling the groove with the insulated layer to obtain a memory cell. CONSTITUTION:An Si substrate 13 has a face (100) on its surface, and a V- groove is formed on the substrate 13 with 2mum width. An SiO or SiO2 layer is formed as the 1st insulated layer 15 and an Nb film is formed on the layer 15 by a sputtering process. Then a lower electrode 16 is formed in a pattern by a photoetching process. An SiO or SiO2 layer is formed on the electrode 16 to fill the V-groove. Thus the 2nd insulated layer 17 is produced with its flat surface. Then the junction holes are formed to the layer 17 and the electrode 16 exposed through the hole 18 is oxidized for formation of a junction oxide film. An upper electrode 19 is formed on the oxide film and the 3rd insulated layer 20 is formed on the electrode 19 by a vapor deposition process. Furthermore a control line 21 of Pb-In-Au is formed in a pattern on the layer 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a quantum interference type single flux quantum memory cell that enables high integration.

Up until now, integrated circuits using silicon (Si) semiconductors have generally been used, and as a method of processing large amounts of information at high speed, increasing capacity by miniaturizing unit elements is being promoted.

That is, development has progressed from RC to LSI, and from LSI to VLSI, and it has become possible to integrate elements with more than several dozen bits on one chip.

However, on the other hand, heat generation of elements due to miniaturization has become a problem.
Various cooling methods have been put into practical use.

In other words, from the conventional cooling method using fins to forced air cooling,
Development is also progressing from water cooling to liquid cooling using liquid nitrogen.

The recently developed Josephson element is an active element that exhibits strong nonlinearity, and it performs ultra-high-speed switching operation of less than 10 ps, generates only a small amount of heat at about 10-J, and generates less than 1μ- after switching. It has low power consumption characteristics and can be highly integrated.

This performance is about two orders of magnitude faster than current Si elements.
Moreover, it is attracting attention as a computer element because it has a three to four order of magnitude superiority in power consumption.

[Conventional technology]

Quantum interference type single flux quantum memory is generally used as the main memory cell used in Josephson computers.

FIG. 4 shows a conventional cross-sectional view (A) and a plan view (B), in which a ground brain 2 made of, for example, niobium (Nb) with a thickness of approximately 4,000 is placed on an St substrate 1; A lower electrode 4 made of, for example, Nb with a thickness of about 2000 μm is patterned through a first insulator N3 made of silicon oxide (Si0) with a thickness of about 3000 μm.

Next, after forming a second insulating layer 5 having a Si0 layer with a thickness of about 3,000, for example, with a window opening in the Josephson element forming area, a lower electrode is formed using a method such as RP plasma oxidation or thermal oxidation. A tunnel insulating film is formed in the window opening 4.

Next, on top of this, for example, about 4000 people of lead/bismuth (
After patterning an upper electrode 6 made of lead, indium, gold (Pb-Bi), and coating the third insulating layer 7 made of SiO to a thickness of about 7,000 yen, for example, A single magnetic flux quantum memory cell is completed by patterning a control line 8 of approximately 1 μm thick consisting of .U).

That is, the two Josephson junctions 9 and 10 are connected to the upper electrode 6.
By connecting with the lower electrode 4, a quantum interference type mono-
A magnetic flux quantum memory cell is formed.

FIG. 4(B) is a plan view of two memory cells, the upper cell shows a state in which a control line 8 is patterned, and the lower cell shows a state in which the control line 8 is removed. On the other hand, regions 11 surrounded by broken lines each indicate an area where the second insulating layer is opened to form a Josephson element.

This embodiment is designed with a pattern rule of 2 .mu.m, and the size of the unit cell is 30 .mu.m long and 17 .mu.m wide, thereby realizing an integrated circuit consisting of 16 bit cells on a 1 cm square chip.

In order to increase the degree of integration to 64 bits or more, the pattern rule must be made smaller and process control must be more strictly controlled, but there are other dimensional constraints.

In other words, in the Josephson memory cell design, L, XI, = Φ1/2 ・・・・・・・・・・・・
(1) Here, Ll...loop inductance of memory cell 11...
・It is necessary to maintain the following conditions: maximum Josephson current Φ1...magnetic flux size of one magnetic flux quantum, where Ll is L1=[μ(λ+d)
L)/W...(2) Here, μ...Magnetic permeability of the second insulating layer λ...London penetration depth of the superconducting material d...
There is a relationship between the thickness L of the second insulating layer, the distance W between the two Josephson junctions, and the width of the Josephson junction.

Therefore, once the superconducting material to be used and the thickness of the interlayer insulating film are determined, the relationship between L and W is determined, and as shown in Figure 4 (B), as long as the design is based on the 2 μm rule, the distance between the two junctions is 1211. Since this rule is required, there is a problem in that the cell cannot be made smaller as long as this rule is used.

[Problem that the invention seeks to solve]

The 2 μm rule is used in the design of Josephson integrated circuits, and 16 bits are integrated on a 1 cm square chip, but in order to achieve even higher density, the pattern rule must be made smaller than 2 μm. is necessary.

However, this requires greater precision in manufacturing process control and significant changes in the manufacturing process.

Therefore, it is desired to achieve high integration using the conventional 2 μm rule, but the problem is that the memory cell cannot be made smaller due to the loop inductance limit of the memory element.

[Means for solving problems]

The above problem is solved in a Josephson memory circuit using a single magnetic flux quantum memory cell, in which a groove is provided in the silicon substrate, two Josephson junctions are provided across the groove, and a ground brain and lower electrode are placed along the liquid groove. The problem can be solved by using a method for manufacturing a Josephson memory circuit, which is characterized in that after forming a liquid groove and filling the liquid groove with an insulating layer, an upper electrode is provided on the insulating layer to form a memory cell. can.

[Effect]

The present invention adheres to the 2 μm rule and forms Josephson junctions on both sides of the substrate with grooves as a method of downsizing the memory cell without changing the loop inductance.
By burying this groove when providing an insulating layer, the effective memory cell area is reduced without changing the loop inductance, thereby achieving higher density.

〔Example〕

FIG. 1 shows a memory cell in which the present invention is implemented, and FIG. 1(A) is a cross-sectional view, FIG. 1(B) is a plan view, and
The figure is a sectional view showing another embodiment of the invention.

The only difference from the conventional structure shown in Figure 4 is that there is a groove between the two Josephson junction forming parts, and this groove is filled in when forming the second insulating layer to form a flat insulating layer. ing.

The device structure and method for manufacturing a memory mole according to the present invention will be explained below.

FIG. 3 explains the implementation process of the present invention, in which a Si substrate (hereinafter abbreviated as substrate) 13 having a (100) plane is used, and an anisotropic etching solution such as caustic potash (KOH) is used. By using it, a V-groove with a width of 2 μm is formed on the surface as shown in FIG.

Next, a ground plane 14 is formed by forming an Nb film with a thickness of about 30 000 by the sputtering method.

This condition is, for example, an Ar gas pressure of 20 mm Torr.

Perform with electric power IK-.

Next, a Si0 layer or Si layer is formed as the first insulating layer 15 on top of this.
02 layer is formed to a thickness of about 3,000 layers.

Here, SiO is formed by a vacuum evaporation method, and SiO2 is formed by a sputtering method.

A Nb film is formed on this layer to a thickness of about 2000 mm using a sputtering method, and a lower electrode 16 is patterned using photolithography. (B in the same figure) Here, a pb alloy film may be used as the lower electrode, but the patterning method when using Nb is to form a pattern with a resist, and then add 5% carbon tetrafluoride (CF a ). 0 of
It is made by plasma etching in an atmosphere doped with 2.

Next, by forming a layer of SiO or Si02 thereon, vl is filled and a second insulating layer 17 with a flat surface is formed. (Figure C) This planarization can be done by using silicone resin (polyladder organosiloxane), embedding it using a spin code method, and thermally decomposing it, or by forming a Si0 layer or ST
Embedded using a combination of o 2 N formation and spin code method,
It can also be obtained by dry etching to a desired thickness using a reactive etching method.

Next, the second insulating layer 17 is opened to form a bonding hole 18.

For example, if reactive ion etching is performed using methane trifluoride (CHF 3 ) and an RF power of 100 W in an atmosphere of 10 II Torr, the etching rate will be approximately 300 people/m2.
Etching progresses at a speed of in and stops at the Nb layer constituting the lower electrode 16.

Next, the lower electrode 16 exposed from the bonding hole 18 is oxidized to form a bonding oxide film, and then the upper electrode 19 is formed thereon.

That is, the junction oxide film is Ar + 3% oz and the gas pressure is 7 am.
' RF plasma oxidation can be performed for about 1 minute at a cathode bias of 150 V in a Torr atmosphere.
Immediately after the formation of the bonding oxide film is completed, the upper electrode 19 is patterned using a Pb-Bi gold alloy to a thickness of about 4,000 mm using a vacuum evaporation method. (D in the same figure) Next, as in the conventional method, a thickness of about 7,000
After forming the third insulator N20, Pb-
By patterning control lines 21 made of In--Au, a memory mol to which the present invention is applied is completed as shown in FIG. 1(A).

Note that FIG. 4(B) is a plan view showing two memory cells, and corresponds to the conventional FIG. 4(B).

In this way, by applying the 2 μm pattern rule, the width of the V groove is 2 μm.
When forming a memory cell with micrometers, the conventional junction spacing is 1
While it was 2 μm, it can be shortened to 6 μm, thus making it possible to reduce the area occupied by the memory cell by 20%.

In addition, in the embodiment, after forming the vs using an anisotropic Si etching solution, it was buried flat in the second insulating layer 17, but the second insulating layer was formed in a similar shape as it was, and the upper electrode was placed on top of the second insulating layer. 19 may be provided, and in this case, the bonding interval will be 9 μm.

Further, instead of forming the VS on the substrate 13, as shown in FIG. 2, an insulating layer 22 may be formed on the substrate 13 and grooves may be formed thereon to obtain the same effect.

〔Effect of the invention〕

As described above, according to the present invention, the junction spacing of memory cells in a Josephson memory circuit can be determined three-dimensionally and the two-dimensional spacing can be reduced, making it possible to increase the integration of the Josephson memory circuit. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a memory cell embodying the present invention, FIG. 1A is a sectional view, FIG. 2B is a plan view, and FIG. 3(A) to 3(D) are cross-sectional views explaining the present invention in detail, and FIG. 4 shows the configuration of a conventional memory cell.
A) is a sectional view, and (B) is a plan view. In the figure, 1.13 is an St substrate, 2.14 is a ground plane, 3.15 is a first insulating layer, 4 and 16 are lower electrodes, and 5.
17 is the second insulating layer, 6.19 is the upper electrode, 7.20
is the third insulating layer, 8.21 is the control line, and 9.10 is the Josephson junction. Patent applicant Director of the Agency of Industrial Science and Technology Tatsumine Todoroki 3rd day

Claims (1)

[Claims] After the quantum interference type single magnetic flux quantum memory provides a groove in the substrate, a first ground plane is formed sequentially along the groove.
An insulating layer and a lower electrode, a second insulating layer formed by filling the groove, and two layers formed by forming an upper electrode after opening a window in the second insulating layer to form a bonding hole. A Josephson memory circuit comprising: a Josephson junction; and a control line patterned through a third insulating layer on the upper electrode.