JPH0945915A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform multi-connection of a group of fine semiconductor islands and a group of thin wires in a form where they are interconnected and to extract that function as an electrical signal. SOLUTION: In a semiconductor device containing a semiconductor layer on an insulation layer, one portion of the semiconductor layer is machined thinner than another part, thinly machined semiconductor layers 2 and 3 are held by a thick region 1 which is not thinly machined, and the length of the semiconductor layer 2 which is thinly machined is controlled, thus setting one portion into tunnel insulation property and the remaining part into complete insulation property.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device utilizing a tunneling phenomenon such as a single electron tunnel or an intersubband tunnel, or a semiconductor charging effect.

[0002]

2. Description of the Related Art Quantum effect elements such as Coulomb blockade elements not only dramatically reduce power consumption and the like compared with conventional MOS type elements, but also act as functional elements that have never existed before. Is a feature. For example, if the Coulomb blockade phenomenon is used, it is possible to fabricate a turnstile element that transfers electrons one by one, a pump element that moves charges in the direction opposite to the voltage, and these elements can be used as a current standard. . In addition, the binary decision graph (Binary Decision Diagram (Binary
It has been shown that a basic unit device (BDD device) for logical operation based on the theory of BDD) can be easily manufactured, and minute Coulomb blockade islands (hereinafter referred to as minute islands) are arranged vertically and horizontally. It is possible to build a quantum cellular automaton using electrostatic interaction. It is also shown that some functional elements can be assembled by using a quantum wire structure instead of a small island. An electron waveguide similar to the optical waveguide can be manufactured by arranging the two one-dimensional thin wires so as to be close to each other to a tunnelable distance. In addition, the BDD device described above can be manufactured by applying this electron waveguide. In order to realize these functional elements, it is necessary to fabricate a group of minute islands or a group of fine wires that are tunnelable with each other or have an electrostatic interaction with each other. As an insulator connecting these groups of small islands and groups of fine wires, another substance having a wide bandgap may be used, but a bandgap expansion effect by thinning the same substance may be used. The latter has a simple process in that the same substance is used, and the characteristics of some devices have been evaluated. However, up to now, although there are some that use the film thickness non-uniformity that naturally occurs at the time of thin film deposition, the function has not yet been achieved using a multiple connection structure such as micro islands in a controlled manner.

[0003]

As described above, according to the conventional method, it is difficult to connect the micro-island groups and the fine wire groups in a multiple manner so that they interact with each other, and to take out this effect as an electric signal. .

An object of the present invention is to provide a semiconductor device in which a group of minute semiconductor islands and a group of fine wires are multiply connected in a form in which they interact with each other and the function of which can be taken out as an electric signal.

[0005]

In order to solve the above problems, the present invention provides a semiconductor device including a semiconductor layer on an insulating layer, wherein a part of the semiconductor layer is processed thinner than the other part, In addition, a part of the thinly processed semiconductor layer has a tunnel insulating property and the remaining part has a complete insulating property (corresponding to, for example, the examples of FIGS. 1 to 8).

Further, in a semiconductor device including a semiconductor layer on an insulating layer, a part of the semiconductor layer is processed thinner than the other part, and the processed semiconductor layer is sandwiched between thick regions. By controlling the length of the thinly processed semiconductor layer, a part thereof has a tunnel insulating property and a remaining part has a complete insulating property (see, for example, FIG.
(Corresponding to the embodiment of FIG. 8).

Also, a part of the thick region is a one-dimensional thin line sandwiched by thin regions on both sides, and a thin region having a tunnel insulating property is sandwiched between the one-dimensional thin line and the second thick region. Is included (corresponding to the embodiment of FIG. 5A, for example).

Further, a part of the thick region is a one-dimensional thin line which is sandwiched by thin regions on both sides. The thick region has two thick regions, and each thin line has a thin region of tunnel insulation. It is characterized in that it has a third thick region sandwiching a thin region having a tunnel insulating property or a completely insulating property in the vicinity of at least one of the two thin wires (for example, FIG. (corresponding to the example of b)).

Further, the thick region connected to at least one of the two one-dimensional thin lines is separated into at least two branches separated from each other by a thin region having a complete insulating property. (Corresponding to the embodiment of FIG. 5C, for example).

Further, it is characterized in that it has an island-shaped minute thick region surrounded by thin regions on four sides, and at least two thick regions sandwiching a thin region having a tunnel insulating property in the vicinity thereof. (For example, it corresponds to the embodiment of FIGS. 6 to 11).

In addition, there are at least two minute islands each of which is an island-like minute thick area surrounded by thin areas on four sides, and these minute islands have a small tunnel insulating property with the adjacent minute islands. It is characterized in that they are arranged so as to sandwich a region (corresponding to, for example, the examples of FIGS. 6, 7, 8, and 10).

[0012] Further, there are minute islands which are island-shaped minute thick areas surrounded by thin areas on four sides, and two thick areas sandwiching a thin area having a tunnel insulating property in the vicinity thereof.
In the vicinity of the small island, an island-shaped thick region surrounded by thin regions on four sides, a second small island sandwiching this island and the thin tunnel insulating region, and a second small island and thin tunnel insulating region. It has a thick region sandwiching the region (for example, corresponds to the embodiment of FIG. 9).

In addition, there are at least two or more micro islands composed of island-shaped micro thick areas surrounded by thin areas on four sides, and these micro islands are adjacent to each other and have tunnel insulating properties. Of the multi-connected island structure as a basic unit, and at least two or more of the basic units are arranged on a plane with another basic unit and a thin complete insulating region. Each basic unit is capacitively coupled to at least one basic unit (for example, corresponds to the embodiment of FIG. 10).

Further, a micro island composed of an island-shaped micro thick region surrounded by thin regions on four sides, two thick regions sandwiching a tunnel insulating thin region in the vicinity thereof, and two thick regions. One of the two small islands, a second small island sandwiching the thin tunnel insulating region, a third thick island sandwiching the second small island and the thin tunnel insulating region, and the two small islands. Both are characterized by having a fourth thick region adjacent with a thin region of full insulation or tunnel insulation (eg corresponding to the embodiment of FIG. 11).

Further, the semiconductor is silicon, and the film thickness of the thin portion of the semiconductor layer is 5 nm or less.

According to the present invention, it is possible to multiple-connect minute semiconductor island groups and fine wire groups in a form in which they interact with each other, and take out the function thereof as an electric signal.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION First, the basic characteristics of the thick-thin structure for realizing the functional elements shown in the subsequent embodiments in the first embodiment will be described.

Example 1 FIG. 1 (a) shows a structure in which a thin region (3) having a narrow length L and connected to a thin region (2) is sandwiched by a thick region (1). FIG. 1B shows a structure without a narrow thin region (3), which is shown for comparison. 1 (c) is shown in FIG.
The MOSFET structure which added the gate to the whole structure of (a) is shown. FIG. 2D shows the gate voltage dependence of the source / drain current of this element, and the thickness of the thin region is changed. In the structure not including the thin region (3) (FIG. 1B), the characteristics of a normal MOSFET are obtained. this is,
The thick area (1) acts as a conduction area and the thin area (2)
Indicates that it is acting as a completely isolated region. On the other hand, in the structure having the thin region (3), the film thickness is 6n.
In both m and 4 nm, the threshold value is shifted to the high voltage side. This indicates that the threshold value is determined by that of the thin region (3). In addition, a weak current flows even below the threshold value. This is a thin area (3)
It is a current that has passed through the barrier of (1) due to the tunnel effect, and shows that the thin region (3) functions as a tunnel barrier. However, in the case of 6 nm, the tunnel characteristic does not appear significantly. This is because the barrier height is not enough
This is because the current component that is thermally excited and exceeds the barrier increases.

Thus, the thick region can be used as a conductive region. On the other hand, the thin region can be selectively used as a tunnel insulating region and a complete insulating region by changing its length. In order to explain this principle in detail, an example of a thick-thin structure manufacturing method and a band diagram of the thick-thin structure are shown in FIG. 3 (e) to 3 (j) are manufacturing examples when the semiconductor is Si. As shown in FIG. 3E, 2 is an insulating film, 1 is a silicon layer on the insulating film 2, 3 is a silicon substrate, and 4 is an insulating film formed on the silicon layer 1. The silicon layer structure on the insulating film is, for example, SIMOX (separated by implanted oxygen) in which oxygen is ion-implanted into a single crystal silicon substrate to form an oxide film.
An SOI layer such as a wafer, a bonded wafer obtained by bonding a silicon oxide film and a silicon substrate, or a polycrystalline Si layer deposited on an oxide film.

First, the insulating film 4 is processed as shown in FIG. The insulating film 4 is, for example, an oxide film or a nitride film. Alternatively, a resist for exposure may be used. Subsequently, the insulating film 4 is used as a mask to thermally oxidize the upper layer of the silicon layer 1 to thin the unmasked portion (FIG. 3).
(G)). At this time, oxygen may be introduced with an extremely low partial pressure, and silicon may be etched by the reaction of Si + O ₂ → 2SiO. Alternatively, etching may be performed with a gas containing halogen such as Cl or F. In addition, NH ₄ OH /
Chemical etching using a solution such as H ₂ O ₂ or HNO ₃ / HF / H ₂ O may be performed. Alternatively, dry etching such as RIE may be used. Finally, FIG. 3 (h), (i),
As shown in (j), the upper insulating film may be removed and a uniform insulating film may be formed again.

In the thickness-thin structure thus manufactured, when the thickness of the thin portion becomes sufficiently thin, a two-dimensional subband is formed by quantum confinement in the thickness direction. And because the ground level of the two-dimensional subband is above the normal bottom of the conduction band (for holes, this is below the top of the valence band), the band gap of the apparent silicon is Spreads (Fig. 3 (k)). Therefore, this acts as a barrier for the electrons existing in the thick portion.
FIG. 4 (l) shows the Si film thickness dependence of the thin portion of the barrier. It can be seen that the barrier becomes remarkable when the Si film thickness is 5 nm or less. The effect of this barrier increases as the length L of the thin portion increases. Therefore, when the length is narrow, the tunnel current flows, but when the length is wide, the insulating current is completely insulated.

Since the thin portion having a long L is used as a completely insulating region, it is possible to substitute the insulating film such as an oxide film by crushing the thin film so that the film thickness in this region becomes zero. However, in order to do this, for example, in FIG. 1A, it is necessary to mask the regions (1) and (3) to etch the region (2). The nanometer size required for a quantum effect device has problems such as alignment and is difficult to manufacture. In particular, it is extremely difficult to manufacture the multiple connection structure shown in the following examples. In this respect, if a long thin region is adopted as the complete insulating region, the connection structure can be easily produced by using FIGS. 3 (e) to 3 (j) of the production process diagram. Examples 2 to 2 below
7 shows an element structure made possible by combining these two functions of the thin portion (tunnel insulation and complete insulation). In the element structure diagrams below, the white portions represent thick regions (conduction regions), the dark regions represent thin regions having complete insulation, and the dark regions represent thin regions having tunnel insulation.

Example 2 In FIG. 5 (a), a part of the thick regions (1)-(2) is made into a thin wire, and a thin region having a tunnel insulating property is sandwiched between the electrodes (3) at the side of this thin wire. However, it has a structure in which an electrode (4) is added across a thin region of complete insulation. In this structure, the tunnel current flowing from the thin wire portion to (3) can be modulated by sweeping the gate electrode (4), and a negative resistance reflecting the one-dimensional subband structure of the thin wire portion can be expressed. it can.

In FIG. 5 (b), a thick film region (1)-(2) having a thin line portion, a thick film region (3) having a dead end narrow line at the tip, and a complete insulating film between each thin line are formed. It is a structure having the gate electrodes (4) and (5). In the same structure, the thin region between the two thin wires has tunnel insulation. This structure changes the gate electrode voltage,
It is possible to control the time interval at which the electron tunnel transition from the (1)-(2) thin line to the (3) thin line occurs. Thus, the conductance between (1)-(2), (1)-
It becomes possible to modulate the conductance between (3) and it can function as an electron waveguide. In addition,
Either one of the electrodes (4) and (5) may be used,
Tunnel insulation may be provided between the thin wires.

A BDD device can be manufactured by dividing the electrode (1) having the structure shown in FIG. 5B into several branches. (1-1) and (1- in FIG. 5C)
2) and (1-3) are messengers (in this case, electronic)
It is an inflow branch of, and this may be any number as long as it is two or more. The electrodes (4) and (5) are external input terminals, and the output (branch through which electrons flow) changes to (2) (yes) or (3) (no) depending on the voltage there.

Example 3 As shown in FIG. 6 (a), (2) near the small island (1),
A single electron transistor (single electron transistor (single electron transistor) utilizing the Coulomb blockade effect is provided by placing the conductive portion represented by (3) and attaching the gate as shown in the first and second embodiments.
(nister): SET) can be prepared. At this time, the thin regions between (1) and (2) and (1) and (3) become tunnel insulating parts, and the other thin regions become completely insulating parts. The equivalent circuit of this element is as shown in FIG. In FIG. 6A, the width of the connecting portion to the island (1) in (2) and (3) is drawn to be the same size as the island, but this width may be wider. This also applies to the following examples.

Further, as shown in FIG. 6C, a thick film region represented by (4) is added instead of the upper gate electrode,
This can also be used as a gate electrode. At this time, the thin area between (1) and (4) is set wider than the intervals of (1) and (2) and (1) and (3).
It is desirable to keep it completely insulating.

Further, as shown in FIG. 6 (d), three micro islands are arranged, and (4) and (1), (1) and (2), (2) and (3), and (3). A turnstile element can be manufactured by leaving a tunnel insulating property between (5) and adding a gate electrode (6) to the center island (2).
At this time, it is desirable that the (2) and (6) be completely insulated. The equivalent circuit of this element is as shown in FIG. This device periodically changes the potential of (6) to generate one electron per cycle (4).
And (5) can be transferred. It should be noted that the number of micro islands may be any number as long as it is three or more, and the electrodes (6) may be in the vicinity of any island except the islands at both ends.

Further, as shown in FIG. 7 (f), two small islands are arranged to form a tunnel between (3) and (1), (1) and (2), and (2) and (4). Insulated and islands (1), (2)
A pump element can be manufactured by adding gate electrodes (5) and (6) to each of the above. At this time, it is desirable to completely insulate between (1) and (5) and between (2) and (6). The equivalent circuit of this element is as shown in FIG. This element vibrates the electrodes (5) and (6) with a certain phase difference,
Electrons can be transferred against the electric field between (3) and (4). It goes without saying that (5) and (6) may be on the same side.

Example 4 In FIG. 8A, between (5) and (1), (1) and (2), (2) and (3), (3) and (6), and (2 ) And (4), between (4) and (7) are tunnel insulating, and between (2) and (8) are completely insulating. The structures thus manufactured are both controlled between (5)-(7) and (5)-(6) by the gate (8).
It can be regarded as a double turnstile structure with two current paths between them. In this structure, the charge transfer is changed by (5)-(6) and (5)-(7) by changing the center voltage (offset voltage) when the voltage of (8) is oscillated.
Can be divided into two routes. Therefore,
It can function as a BDD device.

Further, as shown in FIG. 8B, (2)
Electrodes (5), (6), (7), and (8) can be treated equivalently by placing a small island (9) between and (8), and charge transfer between the electrodes can be performed. It will be possible.

Example 5 If a structure as shown in FIG. 9 is produced, it can function as a memory element. In the figure, (4) and (5),
Tunnel insulation is provided between (4) and (6), (1) and (2), and between (1) and (3), and complete insulation is provided between (1) and (5). I will keep it. (1) and (4)
Is a small island, and (5) is not necessarily a small island. By applying a voltage to the electrode 6, this structure
Since charges are accumulated in the island (5), it can function as a memory element using this as a storage node. Read the SET ((2)-
(3)).

Embodiment 6 FIGS. 10A and 10B show a side gate (4) and SET.
It is a quadruple island structure having (1), (2), and (3) in the vicinity, and is a basic unit structure of a quantum cellular automaton. The four islands of the quadruple island should be able to tunnel each other,
The side gate (4) and the small islands (1) of SET are arranged so as to have complete insulation and to be coupled only capacitively. In addition, there is a net of +2 or -2 beforehand on the quadruple island.
The electric charge (e) of is induced. Since these two charges repel each other, either (a) or (b) will be arranged. In this case, (a) and (b) are energetically equivalent to each other, and whichever is less likely to occur. When a voltage is applied to the side gate 4,
Since the states of (a) and (b) have different energies, the state of the quadruple island can be changed from the one state to the other state by the voltage of the side gate. This difference in state can be detected by the SET placed in the vicinity,
Finally, the quadruple island state can be extracted as a current value.

By using this quadruple island structure as a basic unit and arranging it in various patterns, a logic circuit can be assembled. The basic unit is represented by the symbol shown in FIG. Here, black circles represent electrons or holes. If the difference between the internal charge states is 0 and 1, the inverter can be manufactured by arranging as shown in FIG. The input at this time is the side gate voltage, and the output is the current value of SET. Similarly, AND and OR circuits can be manufactured. In arranging these basic cells, it is important that they are completely insulated from each other and that they are only capacitively coupled.

Excitation of two charges to the basic cell is, for example,
The insulating layer below the semiconductor layer may be thinned to have a tunnel insulating property, and a substrate voltage may be applied to perform tunneling of electrons with the substrate. Similarly, an upper gate may be installed to exchange charges with it.

The basic unit cell may be a double island, a triple island, a five island or the like as shown in FIG. 10E, in addition to the above-mentioned quadruple island. In the case of double islands and triple islands, only one charge may be excited.

Embodiment 7 If processed into a structure as shown in FIG.
A type of inverter can be made. Tunnel insulation is provided between (3) and (1), (1) and (5), (5) and (2), and (2) and (4). Keep it insulating. The equivalent circuit of this element is as shown in FIG.

Example 8 Up to now, the length of the thin Si layer sandwiched between the thick Si layers was controlled to produce two types of tunnel insulation and complete insulation. It goes without saying that the completely insulating region is effective in the structures of FIGS. 1 to 11 if the Si layer can be completely eliminated (completely oxidized or completely etched). . That is, in the above-mentioned embodiment, the portion which does not need to have the tunnel insulating property has a structure in which the interval of the thick portion is widened to reduce the tunnel probability, but this is effectively removed by completely removing the Si layer. By separating with SiO ₂ , the tunnel probability can be suppressed to a sufficiently low level, it is not necessary to unnecessarily increase the interval, and the space factor is improved. For example, in the example shown in FIG. 10C, as shown in FIG. 12, the semiconductor layers around the four islands are removed so that the semiconductor layers are completely separated, so that the distance between the adjacent four islands can be narrowed. Therefore, the electrostatic coupling with the adjacent island is strengthened, and the transferability of the charge arrangement in the island to the next four island groups is enhanced.

Example 9 In Example 8, the Si in the completely insulating region was completely eliminated, but it is not always necessary to completely eliminate Si.
By making it thinner than the tunnel insulating region, it is possible to effectively make it completely insulating.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the scope of the invention. .

[0041]

As described above, according to the present invention,
The semiconductor film on the insulating layer is stepped into a thick portion and a thin portion, the thick portion is used as a conductive region, the length of the thin portion is controlled, a part is a tunnel insulating region, and the other part is a completely insulating region. It becomes possible to fabricate a structure in which minute islands, thin wires, etc. are multiply connected in a form that interacts with each other, whereby a SET, a turnstile element, a pump element, a CMOS type inverter, a memory element, Functional devices such as electron waveguides, BDD devices, and quantum cell automaton devices can be realized. Also,
Since the thin portion having a long length is used as a complete insulating region, it is possible to substitute the insulating film such as an oxide film by crushing the thin film and setting the film thickness of this region to zero. However, in order to do this, it is necessary to mask other regions, so there are problems such as alignment at the nanometer size required for quantum effect devices, and its fabrication is difficult, but in that respect, complete insulation If a long thin region is adopted as the region, the connection structure can be easily manufactured.

[Brief description of drawings]

1A is a plan view of a barrier structure, FIG. 1B is a plan view of a structure not including a barrier, and FIG. 1C is a plan view of a device structure with a gate.

FIG. 2D is a diagram showing an example of gate voltage dependence of source / drain currents.

3 (e) to (j) are process cross-sectional views showing an example of a thick-thin structure manufacturing process, and (k) is a potential band diagram of the thick-thin structure.

FIG. 4 (l) is a diagram showing the Si film thickness dependence of the barrier height in a thin region.

5A is a plan view of a quantum effect device for detecting a tunnel characteristic from a thin wire, FIG. 5B is a plan view of an electron waveguide, and FIG. 5C is a plan view of a BDD device using the electron waveguide. is there.

6A is a plan view of SET, FIG. 6B is an equivalent circuit diagram of SET, FIG. 6C is a plan view of SET with a gate provided on a side, and FIG. 6D is a plan view of a turnstile element. e) is an equivalent circuit diagram of the turnstile element.

7 (f) is a plan view of the pump element, and FIG. 7 (g) is an equivalent circuit diagram of the pump element.

8A is a plan view of a BDD device using a turnstile structure, and FIG. 8B is a plan view of a composite BDD device using a turnstile structure.

FIG. 9 is a plan view of a memory element.

10A and 10B are plan views of a basic structure of a quantum cellular automaton, FIG. 10C is an explanatory view of abbreviated symbols of basic units,
(D) is a plan view of an inverter using a quantum cellular automaton, and (e) is a diagram showing an example of a basic unit.

11A is a plan view of a CMOS type inverter, and FIG. 11B is an equivalent circuit diagram of the CMOS type inverter.

FIG. 12 is a schematic view of a case where a completely insulating region is manufactured by separation.

[Explanation of symbols]

(1) ... Conductive thick film region, (2) ... Insulating thin film region, (3) ... Tunnel insulating thin film region, 1 ... Silicon layer, 2 ... Insulating film, 3 ... Silicon substrate, 4 ... Insulation film.

Claims (11)

[Claims] 1. A semiconductor device including a semiconductor layer on an insulating layer, wherein a part of the semiconductor layer is processed thinner than the other part, and the thinned part of the semiconductor layer is tunnel insulating. A semiconductor device characterized in that the remaining portion has complete insulation. 2. A semiconductor device including a semiconductor layer on an insulating layer, wherein a part of the semiconductor layer is processed thinner than the other part, and the processed semiconductor layer is sandwiched between thick regions. A semiconductor device characterized by controlling the length of the thinly processed semiconductor layer so that part thereof has a tunnel insulating property and the remaining part has a complete insulating property. 3. A part of the thick region is a one-dimensional thin line sandwiched by thin regions on both sides, and a thin region having a tunnel insulating property is sandwiched between the one-dimensional thin line and a second thick region. The semiconductor device according to claim 1, further comprising: 4. A one-dimensional thin wire, in which a part of the thick area is sandwiched by thin areas on both sides, has two thick areas, and each thin wire has a thin area of tunnel insulation. The third thick region is sandwiched by at least one of the two thin wires and has a third thick region sandwiching a thin region having a tunnel insulating property or a complete insulating property. Semiconductor device. 5. A thick region connected to at least one of the two one-dimensional thin lines is separated into at least two branches separated from each other by a thin region having a complete insulating property. The semiconductor device according to claim 4. 6. An island-shaped minute thick region surrounded by thin regions on four sides, and at least two thick regions sandwiching a tunnel insulating thin region in the vicinity thereof. The semiconductor device according to claim 1. 7. At least two micro islands each having an island-like micro thick area surrounded by thin areas on four sides are provided, and these micro islands are adjacent to each other and have a thin tunnel insulating property. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged so as to sandwich the region. 8. A micro-island composed of island-shaped micro-thick regions surrounded by thin regions on four sides, and two thick regions sandwiching a tunnel insulating thin region in the vicinity thereof, In the vicinity of the micro island, a thick island-like region surrounded by thin regions on four sides, a second micro island sandwiching this island and the thin tunnel insulating region, and a second micro island and the thin tunnel insulating region. The semiconductor device according to claim 1, wherein the semiconductor device has a thick region sandwiched between the regions. 9. At least two or more micro islands each having an island-shaped micro thick area surrounded by thin areas on four sides,
These micro-islands are arranged with adjacent micro-islands sandwiching a region having a thin tunnel insulating property, and the multi-connection island structure is a basic unit, and at least two or more of the basic units are other basic units. 2. A semiconductor device according to claim 1, wherein the semiconductor device is arranged on a plane with the unit and a thin insulating region sandwiched therebetween, and each basic unit is capacitively coupled to at least one basic unit. 10. A micro-island composed of island-shaped micro-thick regions surrounded by thin regions on four sides, two thick regions sandwiching a thin region having a tunnel insulating property in the vicinity thereof, and two thick regions. One of the two small islands, a second small island sandwiching the thin tunnel insulating region, a third thick island sandwiching the second small island and the thin tunnel insulating region, and the two small islands. 2. The semiconductor device according to claim 1, wherein both have fourth thick regions adjacent to each other with a thin region having a complete insulating property or a tunnel insulating property interposed therebetween. 11. The semiconductor device according to claim 1, wherein the semiconductor is silicon, and a film thickness of a thin portion of the semiconductor layer is 5 nm or less.