JPS61241906A - Semiconductor ceramic composition and semiconductor ceramicsand capacitor using the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a grain boundary insulated semiconductor with improved electrical characteristics, particularly a small temperature coefficient, a high dielectric constant, and easy handling. The present invention relates to a composition for ceramics, and semiconductor ceramics and capacitors using the composition.

[Conventional technology]

In recent years, as electronic circuit boards and electronic devices have become lighter and smaller, capacitors, which are one of the electronic components, are desired to be smaller and have higher performance, and materials are being actively developed. Among them, BaTiO3-based semiconductor ceramic compositions have a very large dielectric constant of 5 x 104 to 7 x 104, and also have a small temperature change rate of capacitance and a small dielectric loss value.
rT1O3-based semiconductor ceramic compositions are attracting attention.

[Problem that the invention seeks to solve]

However, when a BaTiO3-based semiconductor ceramic composition is used, the voltage dependence of capacitance is large, the temperature change rate of capacitance is large, waveform distortion occurs, and noise is generated due to electrostriction. It has drawbacks such as high dielectric loss under high voltage AC, large change over time, and high susceptibility to thermal shock.

On the other hand, the SrT+03-based semiconductor ceramic composition is as follows.

Compared to BaTiO3 type, -electricity is small.

The disadvantage is that process control in manufacturing capacitors is extremely difficult.

Furthermore, in the case of 5rT1O3 system.

Although the rate of change in capacitance with temperature is smaller than that of the BaTiO3 system, it is still not sufficient.

Particularly in these days when electronic technology is progressing at a rapid pace, it is necessary to improve the mechanical properties, including the above-mentioned properties, in order to obtain more sophisticated and high-performance devices.

In particular, there is a strong desire to develop capacitors that have a high dielectric constant and a small temperature coefficient of the dielectric constant. However, when using conventional capacitor materials, the relationship between the dielectric constant and its temperature coefficient is As you increase the value of the temperature coefficient, the value of the temperature coefficient increases, and conversely, as you decrease the value of the temperature coefficient,
The dielectric constant was said to be smaller.

In addition, grain boundary insulated semiconductor porcelain formed using conventional materials also has the disadvantage of being easily broken.

〔the purpose〕

The present invention has been made in view of the above points, and it is an object of the present invention to provide a composition for semiconductor ceramics whose characteristics are significantly improved compared to conventional ones, and a semiconductor device and a capacitor using the composition. purpose.

Another object of the present invention is to provide a composition for semiconductor ceramics that has improved electrical characteristics, and semiconductor ceramics and capacitors using the composition.

Yet another object of the invention is to provide semiconductor ceramics and capacitors having a high dielectric constant and a small value of their rate of change with temperature.

Another object of the present invention is to provide a semiconductor device and a capacitor that are extremely easy to control during manufacturing.

[Means for solving problems]

The composition for semiconductor ceramics of the present invention has MgTiO3 of 16.
0-60.5ma1%, S r T i 03 is 24.
5 to 69 mol %, BaTiO3 is 5 to 40 m
It is characterized by containing 0.01 to 0.2so1% of an element selected from rare earths or elements belonging to Group 5 of the periodic table as a grain interface improver and a valence control agent. .

Further, the semiconductor device and capacitor of the present invention are characterized by having the above-mentioned structure as a main structure.

[For production]

By adopting the configuration shown in letter L, it is possible to significantly improve the characteristics, especially the electrical characteristics, and it is also possible to extremely facilitate the process control during manufacturing.

〔Example〕

MgTiO3, which is one of the constituent materials in the present invention, generally has a positive temperature coefficient of dielectric constant and Q
Although the value of BaTiO3 is large, it has the disadvantage of a low dielectric constant. However, according to the results of intensive research by the present inventors, BaTiO3, which has a high dielectric constant, has a negative temperature coefficient and a high dielectric constant. However, by coexisting with 5rT1O3, which is easy to convert into semiconductor porcelain, in a specific amount range, and adding a grain interface improver and a valence control agent, a high dielectric constant, which was not expected when each was used alone, was achieved. At the same time, it is possible to obtain semiconductor ceramics or capacitors whose dielectric constant has a significantly smaller temperature change rate than conventional ones.

Furthermore, even if there is variation in the amount of the diffusion material applied to the sheet metal during manufacturing, the effect on the properties is extremely small, making process control extremely easy.

MgTi03 is one of the features of the present invention.

The amounts of 5rT1O3 and B a T i 03 ty) are limited to the values mentioned above for the following reasons.

That is, when M g T i O3 is less than 16.0 mol% or 5rT1O3 is more than 69 mol%, the absolute value of the temperature coefficient becomes large, and BaTiC)3 is less than 40 mol%.
If it exceeds 1%, the absolute value of the temperature coefficient increases and the Q value also decreases.

When MgTiO3 exceeds 60.5 mol%, the dielectric constant decreases significantly, or when 5rT1O3 is less than 24.5 mol%, the dielectric constant decreases, and when BaTiO3 exceeds 5 mol%.
%, the dielectric constant decreases significantly and the Q value also decreases slightly. For these reasons, MgTiO3, S rTf03
and BaT1O3c7) is preferably limited to the above range.

In the present invention, in order to provide an insulating region, that is, an insulating crystal grain boundary layer at the crystal grain boundary of the semiconductor ceramic to be formed, the crystal grain boundary layer contains, for example, Ca, Cr, M.
At least one of n, Cu, and TRI is added as an insulating additive.

These insulating additives are applied to the surface of the primary fired semiconductor porcelain that is created through the secondary firing process.

Usually, it is applied in the form of an oxide in the form of a paste, and then diffused into grain boundaries during secondary firing to provide insulation.

In this case, in the present invention, S r 02 *B i
By adding a grain interface modifier such as 2O3, it is possible to improve the dielectric properties of semiconductor ceramics and capacitors obtained.

The function of this grain interface improver is that after the insulation additive is applied to the surface of the semiconductor porcelain to be fired, it is fired in air.
When diffusing the above-mentioned insulating additive into the grain boundaries, it is thought that by uniformly diffusing the insulating additive to the grain boundaries and to the diffusion surface, properties are stabilized and made uniform. It will be done.

In the present invention, the amount of grain interface improver to be added is appropriately determined according to desire, but in the case of SiO2, it is preferably 0.3 to 6.5 mol%, and in the case of B i 2O3, it is preferably 0.3 to 6.5 mol%. is set to 0.02 to 0.14 mol%.

SiO2 as grain interface modifier. Bi2O2 may be used alone or in combination, but it is preferable to add at least 5to2.

When using a mixture of SiO2 and B i 2O3,
The amount added may be within the same range as in the case of each component alone.

In the present invention, SiO2 and B i as grain interface modifiers
In the case of SiO2, when the amount of 2O3 added is below this range, the absolute value of the temperature coefficient tends to increase and the Q value tends to decrease, and when it exceeds it, the dielectric constant tends to decrease. Therefore, in the case of B i 2O3, it tends to show at least a decrease in the dielectric constant and an increase in the absolute value of the temperature coefficient, so it is desirable to have the amount in the above range. be done.

The valence control agent used in the present invention is an element belonging to Group 5 of the periodic table, especially Nb.

Suitable components include vanadium elements such as Ta, nitrogen group elements such as sb, and rare earth elements such as Y, La, and Ce, and these are usually used in the form of oxides.

The valence control agent is not limited to one type, but may be used in plural types, but preferably, it is a rare earth element, or a valence control agent from the fifth group of the periodic table.
It is desirable to have multiple types of group elements.

The amount of the valence control agent to be added is appropriately determined as desired depending on the required characteristics of the semiconductor ceramic or capacitor to be produced, but semiconductor formation can be performed by firing treatment in a reducing atmosphere. Further, if the amount falls outside of this range, it becomes extremely difficult to convert it into a semiconductor by firing in a reducing atmosphere, so it is set at 0.01 to 0.2 go1%.

1 and 2 show an example in which the present invention is applied to a grain boundary insulated semiconductor ceramic capacitor. FIG. 1 is a schematic perspective view of a capacitor, and FIG. 2 is a schematic cross-sectional partial view.

In the capacitor shown in the figure, electrodes 11 (only the top electrode is shown in the figure) made of An, Au, etc. are provided on the upper and lower surfaces of a grain-boundary insulated cliff conductor ceramic M12, respectively. It is being The semiconductor ceramic layer 12 is a dielectric layer (insulator region) formed by forming a large number of semiconductor ceramic crystal grains 22 at grain boundaries.
Contains 21 in an interposed form.

The size of the crystal grains is appropriately determined depending on the required electrical properties, the amount of constituent materials, the firing conditions, etc., but usually IILm to 100gm, preferably 2#Lm to 8
It is desirable to set it to 0gm.

In order to obtain semiconductor porcelain with the composition ratio shown in Table 1,
Each raw material was weighed and pulverized and mixed in a wet □ ball mill for 12 hours. After drying this material, a small amount of polyvinyl alcohol was added as a binder, and it was granulated into 24 to 80 meshes, and then granulated with a hydraulic press to a diameter of 20 mm and a thickness of 0.8 mm.
It was molded into a disc.

Next, this molded disk was calcined at 950° C. for 1 hour at atmospheric pressure to burn off the binder. After cooling this material to room temperature, it was heated to 1360° C. in a reducing atmosphere consisting of 70% by volume of nitrogen and 30% by volume of hydrogen.

It was baked for 2 hours.

Approximately 30 mg of a paste prepared by kneading CuO and pheno in a weight ratio of 1:1 was applied to the semiconductor porcelain thus obtained, and the paste was fired in air at 1400° C. for 1 hour to form an insulating type at the grain boundaries. Gold was deposited on both hands of this object by vapor deposition to form a capacitor as an electrode, and the electrical characteristics of each were measured.

The results are shown in Table 2.

As illustrated in Tables 1 and 2, the grain boundary insulated semiconductor ceramic composition that satisfies the composition within the scope of the present invention has a temperature coefficient of dielectric constant of -2O0 to -730ppm/'C. On the other hand, it has a dielectric constant of 3,100 to 4,600, which is extremely high compared to conventional products, and furthermore, it is industrially useful because process control during manufacturing is extremely easy.

Furthermore, it was confirmed that other electrical characteristics were also improved compared to the conventional ones.

■-2Ll 1st self--1--2 Shishi O Mugisa) 27-36 Comparative example basket-U for comparison with the present invention Part 2 - Yo Shigeru C Hikari) Measured at 125℃ and 1 frequency IKHz.

Temperature range -10~+85℃ based on zero 125℃
Calculated from the measured value.

〔Effect of the invention〕

As can be seen from the above description, the present invention provides semiconductor porcelain and capacitors that have a high galvanicity rate, a small rate of temperature change in charge rate, easy manufacturing process control, and excellent reproducibility. can be obtained at low cost.

In addition, it is less likely to break than conventional grain-boundary insulated semiconductor porcelain, and is extremely easy to handle when processed into capacitors, etc. In addition to the above-mentioned characteristics and manufacturing process control, it is also suitable for industrial use from a processing perspective. Above all, it is extremely useful.

[Brief explanation of drawings]

FIG. 1 is a schematic perspective view of a capacitor, and FIG. 2 is a schematic cross-sectional partial view of the capacitor shown in FIG.

Claims (16)

[Claims] (1) (a) MgTiO_3 16.0-60.5mo
(b) SrTiO_3 24.5 to 69 mol%, (c) BaTiO_3 5 to 40 mol%, (d) Grain interface modifier, and (e) Rare earths or elements belonging to Group 5 of the periodic table. A composition for semiconductor ceramics containing 0.01 to 0.2 mol% of a selected element. (2) The composition for semiconductor ceramics according to claim 1, wherein the grain interface improver is SiO_2. (3) The composition for semiconductor ceramics according to claim 1, wherein the grain interface improver is Bi_2O_3. (4) The composition for semiconductor ceramics according to claim 1, wherein the rare earth element is selected from Y, La, and Ce. (5) Elements belonging to Group 5 of the periodic table are Nb, Sb, and T.
The composition for semiconductor ceramics according to claim 1, which is selected from a. (6) (a) MgTiO_3 16.0-60.5mo
(b) SrTiO_3 24.5 to 69 mol%, (c) BaTiO_3 5 to 40 mol%, (d) Grain interface modifier, and (e) Rare earths or elements belonging to Group 5 of the periodic table. A semiconductor ceramic containing 0.01 to 0.2 mol% of a selected element and having a large number of semiconducting crystal grains in which insulator regions are formed at grain boundaries. (7) The insulator region contains Ca, Cr, Mn, Cu and T.
7. The semiconductor porcelain according to claim 6, which contains at least one selected from the following. (8) The semiconductor porcelain according to claim 7, wherein the grain interface improver is SiO_2. (9) The semiconductor porcelain according to claim 7, wherein the grain interface improver is Bi_2O_3. (10) The semiconductor ceramic according to claim 7, wherein the rare earth element is selected from Y, La, and Ce. (11) Elements belonging to Group 5 of the periodic table are Nb, Sb,
The semiconductor ceramic according to claim 7, which is selected from Ta. (12) sandwiched between a pair of electrodes, (a) MgTiO_3 16.0-60.5 mol%, (b) SrTiO_3 24.5-69 mol%, (c) BaT1O_3 5-40 mol%, ( d) grain interface modifier; and (e) contains 0.01 to 0.2 mol% of an element selected from rare earths or elements belonging to Group 5 of the periodic table, and provides insulation at grain boundaries. A capacitor comprising a layer having a large number of semiconductor crystal grains in which a body region is formed. (13) The capacitor according to claim 12, wherein the grain interface modifier is SiO_2. (14) The capacitor according to claim 12, wherein the grain interface modifier is Bi_2O_3. (15) The capacitor according to claim 12, wherein the rare earth element is selected from Y, La, and Ce. (16) Elements belonging to Group 5 of the periodic table are Nb, Sb,
The capacitor according to claim 12, wherein the capacitor is selected from Ta.