JPS61239681A - Superconducting element - Google Patents

Superconducting element

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Publication number
JPS61239681A
JPS61239681A JP60080164A JP8016485A JPS61239681A JP S61239681 A JPS61239681 A JP S61239681A JP 60080164 A JP60080164 A JP 60080164A JP 8016485 A JP8016485 A JP 8016485A JP S61239681 A JPS61239681 A JP S61239681A
Authority
JP
Japan
Prior art keywords
electrode
layer
substrate
semiconductor layer
onto
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60080164A
Other languages
Japanese (ja)
Inventor
Juichi Nishino
西野 壽一
Ushio Kawabe
川辺 潮
Yutaka Harada
豊 原田
Mutsuko Miyake
三宅 睦子
Masaaki Aoki
正明 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60080164A priority Critical patent/JPS61239681A/en
Publication of JPS61239681A publication Critical patent/JPS61239681A/en
Pending legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To increase the switching rate of an element by forming an electrode consisting of a superconductor onto a substrate through an insulating film, shaping a semiconductor layer onto the electrode and forming a control electrode onto the semiconductor layer through an insulator layer. CONSTITUTION:An insulating film 2 is shaped onto an Si substrate 1, and an electrode 3 composed of a superconductor is formed onto the insulating film 2. A semiconductor layer 4 is shaped onto the electrode 3. The shape of the layer 4 is determined so that the layer 4 extends over the upper sections of both the film 2 and the electrode 3 including regions except a region 5 to which the electrode 3 faces. An insulator layer 6 is formed onto the surface of the layer 4, and a control electrode 7 consisting of a metal or a semiconductor is shaped onto the layer 6. Consequently, when shaping a superconducting element, substrate capacitance is not formed because the semiconductor layer through which superconductive currents or normal conductive currents flow is insulated electrically from the substrate. Accordingly, a switching rate in circuit operation can be increased.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、極低温で動作する超電導素子に係り、特に超
電導体と半導体とを組合わせて成る超電導素子に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a superconducting device that operates at extremely low temperatures, and particularly to a superconducting device that is formed by combining a superconductor and a semiconductor.

〔発明の背景〕[Background of the invention]

従来、超電導体と半導体とを組合わせた超電導素子とし
て特開昭57−106186号に記載されたものがある
。この超電導素子は、半導体基板上に一対の超電導体層
を該超電導体層の端面を対向させて被着し、その対向部
に絶縁層を介して制御導体を配設することにより成る。
Conventionally, there is a superconducting element that combines a superconductor and a semiconductor described in Japanese Patent Laid-Open No. 106186/1986. This superconducting element is constructed by depositing a pair of superconducting layers on a semiconductor substrate with their end surfaces facing each other, and disposing a control conductor on the opposing portions with an insulating layer interposed therebetween.

すなわち、制御導体により超電導体層・半導体基板・超
電導体層間を流れる電流を制御するものであるが、半導
体の基板容量により回路動作におけるスイッチ速度を高
速にすることができない。
That is, although the control conductor controls the current flowing between the superconductor layer, the semiconductor substrate, and the superconductor layer, it is not possible to increase the switching speed in circuit operation due to the substrate capacitance of the semiconductor.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、素子のスイッチング速度の高速化を図
ることができる超電導素子を提供することにある。
An object of the present invention is to provide a superconducting element that can increase the switching speed of the element.

〔発明の概要〕[Summary of the invention]

本発明は前記目的を達成するため、少なくとも極低温に
おいて絶縁体となる基板若しくは基板上に形成した絶縁
膜上に超電導体より成る電極を形成し、該電極上に半導
体層を形成する。さらにこの半導体層上に絶縁物層を形
成し、該絶縁物層上に制御電極を形成することにより超
電導素子を構成する。
In order to achieve the above object, the present invention forms an electrode made of a superconductor on a substrate that becomes an insulator at least at extremely low temperatures or an insulating film formed on the substrate, and forms a semiconductor layer on the electrode. Furthermore, a superconducting element is constructed by forming an insulating layer on this semiconductor layer and forming a control electrode on the insulating layer.

このように、超電導電流又は常電導電流が流れる半導体
層は、基板と電気的に絶縁されているのでいわゆる基板
容量を持たない。従って、回路動作におけるスイッチ速
度を高速化することが可能となる。また基板の材料とし
て高抵抗の材料を用j      いることができるの
で、基板上に多数の超電導素子を形成する場合、基板内
に特別の素子間分離を施すことなく使用することができ
る。
In this way, the semiconductor layer through which superconducting current or normal conducting current flows is electrically insulated from the substrate and therefore does not have so-called substrate capacitance. Therefore, it is possible to increase the switching speed in circuit operation. Furthermore, since a high-resistance material can be used as the substrate material, when a large number of superconducting elements are formed on the substrate, it can be used without providing special isolation between elements within the substrate.

また、半導体層を結晶的・電気的に向−ヒさせるため熱
処理を行うことが有効である。この場合、半導体層下の
超電導体の超電導特性が劣化するおそれがある。本発明
者らの検討によると超電導体の材料としてNbN、Nb
3Si、Nb、Ge。
Furthermore, it is effective to perform heat treatment to improve the crystallization and electrical properties of the semiconductor layer. In this case, the superconducting properties of the superconductor under the semiconductor layer may deteriorate. According to the studies conducted by the present inventors, NbN, Nb
3Si, Nb, Ge.

M o N、 V3S i  を用いれば、半導体層の
熱処理を行っても半導体層下の超電導体の特性が劣化し
ないことが判明した。これにより、半導体層を熱処理す
ることができ、例えば半導体の結晶粒径を増大させるか
又は再結晶化させて主に(100)面の単結晶化が可能
となり、超電導素子の特性を向上させることができる。
It has been found that when M o N, V3S i is used, the characteristics of the superconductor under the semiconductor layer do not deteriorate even if the semiconductor layer is subjected to heat treatment. This makes it possible to heat-treat the semiconductor layer, for example to increase the crystal grain size of the semiconductor or to recrystallize it, making it possible to form a single crystal mainly in the (100) plane, thereby improving the characteristics of the superconducting element. I can do it.

尚、(100)面の単結晶化をするためには、半導体層
を超電導体と絶縁膜の両方にまたがるように形成すれば
良い。
Note that in order to achieve single crystallization in the (100) plane, the semiconductor layer may be formed so as to span both the superconductor and the insulating film.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面を用いて詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は、本発明の実施例による超電導素子の一部を示
す断面図である。(100)方位のSi基板1を熱酸化
して厚さ約700nmのS i O,より成る絶縁膜2
を形成する。続いてArとN2の混合ガスを用いた反応
性スパッタリング法により厚さ約20nmのNbN薄膜
を形成し、ホトレジストのパターンをマスクとしたCF
4ガスによる反応性イオンエツチング法により加工し超
電導体より成る電極3を形成した。対向する電極の距離
は0.5〜0.1  μmに選ばれることが良い。次に
気相成長法により多結晶状若しくはアモルファス状のS
iを厚さ約20nm堆積させ、ホトレジストのパターン
をマスクとしたCF、ガスによってエツチングする。続
いてスパッタ法によって図には示されていないSin、
膜を約30nmの厚さに堆積させたのち、レーザビーム
あるいはヒータによって500℃〜1500℃に加熱し
て、半導体の結晶粒径の増大あるいは単結晶化を行って
半導体層4とした。5in2膜はこの加熱処理のあとで
エツチングにより除去する。半導体層4、の形状は第2
図に示したごとく、電@Sが対向する領域5以外の領域
を含めて絶縁膜2及び電極3の両方の上にまたがる様に
決める。こうすることによって再結晶後の半導体層4の
結晶方位は(100)面とすることができる。結晶方位
を(100)面にそろえることができるということは、
素子特性のばらつきを小さくするために有効である。
FIG. 1 is a sectional view showing a part of a superconducting element according to an embodiment of the present invention. An insulating film 2 made of SiO with a thickness of approximately 700 nm is formed by thermally oxidizing a (100) oriented Si substrate 1.
form. Next, a NbN thin film with a thickness of about 20 nm was formed by reactive sputtering using a mixed gas of Ar and N2, and a CF film was formed using the photoresist pattern as a mask.
An electrode 3 made of a superconductor was formed by processing using a reactive ion etching method using four gases. The distance between opposing electrodes is preferably selected to be 0.5 to 0.1 μm. Next, polycrystalline or amorphous S is grown by vapor phase growth.
I is deposited to a thickness of about 20 nm and etched using CF and gas using the photoresist pattern as a mask. Subsequently, using a sputtering method, Sin, which is not shown in the figure, is
After the film was deposited to a thickness of about 30 nm, it was heated to 500° C. to 1500° C. using a laser beam or a heater to increase the crystal grain size of the semiconductor or to form a single crystal, thereby forming the semiconductor layer 4. After this heat treatment, the 5in2 film is removed by etching. The shape of the semiconductor layer 4 is the second
As shown in the figure, the electrode @S is determined so as to extend over both the insulating film 2 and the electrode 3, including the area other than the opposing area 5. By doing so, the crystal orientation of the semiconductor layer 4 after recrystallization can be set to the (100) plane. The fact that the crystal orientation can be aligned to the (100) plane means that
This is effective for reducing variations in device characteristics.

次に半導体層4の表面にSin、を堆積させるか、又は
半導体層4の自己酸化によって厚さ約1100nの絶縁
物層6を形成し、最後に厚さ約400nmのNbN薄膜
による制御電極を形成した。この絶縁物層6は自己酸化
の他に、低絶縁材料を堆積させて形成しても良い。以上
によって本発明の超電導素子を実現することができた。
Next, an insulator layer 6 with a thickness of about 1100 nm is formed by depositing Sin on the surface of the semiconductor layer 4 or by self-oxidation of the semiconductor layer 4, and finally a control electrode made of an NbN thin film with a thickness of about 400 nm is formed. did. In addition to self-oxidation, this insulating layer 6 may be formed by depositing a low insulating material. Through the above steps, the superconducting element of the present invention could be realized.

以上の実施例においては、電極3の材料にNbNを用い
た。第3図は、加熱処理によるNbN薄膜および従来の
Nb薄膜との超電導特性の重要な目安である超電導転移
温度Tcの変化を示したものである。Nb薄膜でTcが
低下し、超電導特性が劣化しているの比対し、NbN#
Illではこの様な問題は生じない。NbNに代えて、
Nb、、Si。
In the above embodiments, NbN was used as the material for the electrode 3. FIG. 3 shows changes in superconducting transition temperature Tc, which is an important indicator of superconducting properties, between an NbN thin film and a conventional Nb thin film due to heat treatment. In contrast to the Nb thin film, where Tc decreases and the superconducting properties deteriorate, NbN#
Ill does not have this problem. Instead of NbN,
Nb,,Si.

N b s G e 、 M o N 、 V a S
 iを用いた場合にも同様の効果を得ることができた。
N b s G e , M o N , V a S
A similar effect could be obtained when i was used.

また半導体材料にはSiの他に、G a A s 、 
 I n A s 、 I n P +InSb、Ga
P、Ge、CdS等の材料を用いても良いことは言うま
でも無い。また、上記実施例では制御電極として超電導
体を用いたが、AQ等の常電導金属や、不純物を含有す
る半導体を用いても良い。また基板上に絶縁膜を形成し
たが基板材料を石英や極低温において導電性を示さない
ような不純物の少ないSi等の基板であれば絶縁膜を省
略することができる。また、第1図では2つの電極3が
対向し制御電極を有する超電導トランジスタを示したが
、この他に、電極3はそのままで、制御電極の無い平面
型ジョセフソン素子。
In addition to Si, semiconductor materials include Ga As,
I n A s , I n P +InSb, Ga
It goes without saying that materials such as P, Ge, and CdS may also be used. Further, although a superconductor is used as the control electrode in the above embodiment, a normal conducting metal such as AQ or a semiconductor containing impurities may also be used. Further, although an insulating film is formed on the substrate, the insulating film can be omitted if the substrate material is quartz or Si with few impurities that does not show conductivity at extremely low temperatures. Although FIG. 1 shows a superconducting transistor in which two electrodes 3 face each other and has a control electrode, there is also a planar Josephson element with the electrodes 3 as they are but without a control electrode.

あるいは、電極3が1つだけのスーパ・ショットキダイ
オードを形成しこれを用いて回路を形成しても良い。
Alternatively, a super Schottky diode having only one electrode 3 may be formed and a circuit may be formed using this.

この様に製造した超電導素子を液体ヘリウムで1   
  冷却して動作させたと3ろ・素子力゛基板力゛ら電
気的に分離されているために、基板容量が小さく従って
スイッチングが高速となる。また半導体層の結晶性を向
上させ、単結晶化した場合には結晶方位をそろえること
ができるので、素子特性のばらつきを小さく、従って集
積度の高い回路を高い歩留りで製造できる。
The superconducting element manufactured in this way was heated with liquid helium.
When operated with cooling, the circuit is electrically isolated from the element power (substrate force), so the substrate capacitance is small and switching is fast. Furthermore, since the crystallinity of the semiconductor layer can be improved and the crystal orientation can be aligned when it is made into a single crystal, variations in device characteristics can be reduced and highly integrated circuits can be manufactured at a high yield.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、超電導体が接する半導体層が基板とは
絶縁され基板容量を持たないため、超電導素子のスイッ
チ速度の高速化を図ることができる。
According to the present invention, since the semiconductor layer in contact with the superconductor is insulated from the substrate and has no substrate capacitance, the switching speed of the superconducting element can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例による超電導素子の一部を示す
断面図、第2図は本発明の実施例による超電導素子の製
造工程の一部を示す上面図、第3図は加熱処理による超
電導電極の特性変化を示す説明図である。 1・・・基板、2・・・絶縁膜、3・・・電極、4・・
・半導体層、6・・・絶縁物膜、7・・・制御電極。
FIG. 1 is a cross-sectional view showing a part of a superconducting device according to an embodiment of the present invention, FIG. 2 is a top view showing a part of the manufacturing process of a superconducting device according to an embodiment of the present invention, and FIG. FIG. 3 is an explanatory diagram showing changes in characteristics of a superconducting electrode. 1... Substrate, 2... Insulating film, 3... Electrode, 4...
- Semiconductor layer, 6... Insulator film, 7... Control electrode.

Claims (1)

【特許請求の範囲】 1、基板上に設けた超電導体より成る電極と、該電極上
に形成された半導体層と、該半導体層上に形成された絶
縁物層と、該絶縁物層上に設けた金属又は半導体より成
る制御電極とを少なくとも有することを特徴とする超電
導素子。 2、特許請求の範囲第1項において、前記基板と超電導
体より成る電極との間に絶縁膜を有することを特徴とす
る超電導素子。 3、特許請求の範囲第1項又は第2項において、前記電
極を形成する超電導体は、NbN、 Nb_3Si、Nb_3Ge、MoN、V_3Siより
選ばれた材料より成ることを特徴とする超電導素子。 4、特許請求の範囲第1項乃至第3項に記載のいずれか
において、前記半導体層はアモルファス状又は多結晶状
の半導体薄膜を熱処理したものであることを特徴とする
超電導素子。 5、特許請求の範囲第1項乃至第4項に記載のいずれか
において、前記半導体層は前記電極と前記絶縁膜の両方
にまたがりその上面を覆うように形成されたることを特
徴とする超電導素子。
[Claims] 1. An electrode made of a superconductor provided on a substrate, a semiconductor layer formed on the electrode, an insulating layer formed on the semiconductor layer, and an insulating layer formed on the insulating layer. 1. A superconducting element comprising at least a control electrode made of metal or semiconductor. 2. A superconducting element according to claim 1, further comprising an insulating film between the substrate and the electrode made of a superconductor. 3. A superconducting element according to claim 1 or 2, wherein the superconductor forming the electrode is made of a material selected from NbN, Nb_3Si, Nb_3Ge, MoN, and V_3Si. 4. A superconducting element according to any one of claims 1 to 3, wherein the semiconductor layer is a heat-treated amorphous or polycrystalline semiconductor thin film. 5. A superconducting element according to any one of claims 1 to 4, wherein the semiconductor layer is formed to span both the electrode and the insulating film and cover the upper surface thereof. .
JP60080164A 1985-04-17 1985-04-17 Superconducting element Pending JPS61239681A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60080164A JPS61239681A (en) 1985-04-17 1985-04-17 Superconducting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60080164A JPS61239681A (en) 1985-04-17 1985-04-17 Superconducting element

Publications (1)

Publication Number Publication Date
JPS61239681A true JPS61239681A (en) 1986-10-24

Family

ID=13710675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60080164A Pending JPS61239681A (en) 1985-04-17 1985-04-17 Superconducting element

Country Status (1)

Country Link
JP (1) JPS61239681A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272358A (en) * 1986-08-13 1993-12-21 Hitachi, Ltd. Superconducting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272358A (en) * 1986-08-13 1993-12-21 Hitachi, Ltd. Superconducting device

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