JP2950958B2 - Superconducting element manufacturing method - Google Patents
Superconducting element manufacturing methodInfo
- Publication number
- JP2950958B2 JP2950958B2 JP2252218A JP25221890A JP2950958B2 JP 2950958 B2 JP2950958 B2 JP 2950958B2 JP 2252218 A JP2252218 A JP 2252218A JP 25221890 A JP25221890 A JP 25221890A JP 2950958 B2 JP2950958 B2 JP 2950958B2
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- Japan
- Prior art keywords
- superconducting
- single crystal
- superconductor
- thin film
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000013078 crystal Substances 0.000 claims description 53
- 239000010409 thin film Substances 0.000 claims description 30
- 229910002480 Cu-O Inorganic materials 0.000 claims description 22
- 239000010408 film Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 3
- 239000002887 superconductor Substances 0.000 description 32
- 239000004065 semiconductor Substances 0.000 description 16
- 229910015901 Bi-Sr-Ca-Cu-O Inorganic materials 0.000 description 14
- 238000010438 heat treatment Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910000978 Pb alloy Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 229910014454 Ca-Cu Inorganic materials 0.000 description 2
- 229910004261 CaF 2 Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 238000001552 radio frequency sputter deposition Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910015902 Bi 2 O 3 Inorganic materials 0.000 description 1
- 229910004247 CaCu Inorganic materials 0.000 description 1
- -1 SrCO 3 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】 （イ） 産業上の利用分野 本発明は近年注目を浴びている酸化物超電導材料を用
いた超電導素子に関し、超電導トランジスタ及び超電導
FET等に用いることができるものである。The present invention relates to a superconducting device using an oxide superconducting material, which has been receiving attention in recent years, and relates to a superconducting transistor and a superconducting device.
It can be used for FETs and the like.
（ロ） 従来の技術 超電導トランジスタとして、近接効果型トランジスタ
が提案されている（西野他「超電導トランジスタ」応用
物理第56巻第６号（1987）P752〜756参照）。(B) Conventional technology A proximity effect transistor has been proposed as a superconducting transistor (see Nishino et al., “Superconducting Transistor” Applied Physics Vol. 56, No. 6, (1987), pp. 752-756).
これは、超電導体と常電導体を密着させると超電導体
側から常電導体側へクーパー対がしみ出して、常電導体
側への染みだし距離程度の薄い層に超電導を誘発する近
接効果を利用したものである。即ち、常電導膜Ｎを超電
導膜Ｓで挟んだSNS接合で、Ｎの膜厚がしみ出し距離程
度であると、近接効果のためにクーパー対がＳ膜間を行
き来できるようになる。しみ出し距離は常電導体内のコ
ヒーレンス長さに相当する量で、温度の低下と共に大き
くなり、また自由電子の温度と共に増大する。This is due to the proximity effect that induces superconductivity in a thin layer about the distance from the superconductor when the superconductor and normal conductor are brought into close contact and the superconductor side exudes from the superconductor side to the normal conductor side. It is. That is, in the SNS junction in which the normal-conducting film N is sandwiched between the superconducting films S, if the thickness of N is about the exudation distance, the Cooper pair can move between the S films due to the proximity effect. The exudation distance is an amount corresponding to the coherence length in the normal conductor, and increases with decreasing temperature and increases with the temperature of free electrons.
金属の自由電子濃度を変えるのは難しいが、半導体を
用いると半導体の電流を運ぶキャリアを電場によって接
合部に引き寄せて接合部でのキャリア濃度を電界効果ト
ランジスタのように変えることができる。Although it is difficult to change the free electron concentration of a metal, when a semiconductor is used, carriers carrying the current of the semiconductor can be attracted to the junction by an electric field to change the carrier concentration at the junction like a field effect transistor.
近接効果型トランジスタは、この半導体を用いたもの
であり、第７図に示すように、シリコン単結晶板21上
に、ソース電極22とドレイン電極23を形成すると共にシ
リコン単結晶板21の下面にゲート電極24を形成するもの
であり、各電極を鉛合金の超電導体にて構成するもので
ある。図中、25、26、27は絶縁膜である。The proximity effect transistor uses this semiconductor. As shown in FIG. 7, a source electrode 22 and a drain electrode 23 are formed on a silicon single crystal plate 21 and a lower surface of the silicon single crystal plate 21 is formed on the silicon single crystal plate 21. The gate electrode 24 is formed, and each electrode is formed of a lead alloy superconductor. In the figure, reference numerals 25, 26 and 27 are insulating films.
他の従来例としてトンネル注入型電導トランジスタが
提案されている。このトンネル注入型超電導トランジス
タの概念構造は、例えば、IEEE TRANSACTIONS ON MAGNE
TICS,VOL.MAG−21,NO.2,MAR.1985「A NEW SUPERCONDUCT
ING BASE TRANSISTOR」P.721〜724、あるいは同誌VOL.M
AG−19,NO.3,MAY 1983「QUITERON」P.1203〜1295に示さ
れている。即ち、第８図に示すように、半導体からなる
コレクタ領域31と、コレクタ領域31に接した超電導体か
らなるベース領域32と、このベース領域32にトンネル現
象が起こり得る極めて薄い絶縁層33を介して設けられた
超電導体からなるエミッタ領域34とから構成されてい
る。As another conventional example, a tunnel injection type conductive transistor has been proposed. The conceptual structure of this tunnel injection type superconducting transistor is, for example, IEEE TRANSACTIONS ON MAGNE.
TICS, VOL.MAG-21, NO.2, MAR.1985 `` A NEW SUPERCONDUCT
ING BASE TRANSISTOR ”P.721-724, or VOL.M
AG-19, NO. 3, MAY 1983, "QUITERON", pp. 1203-1295. That is, as shown in FIG. 8, a collector region 31 made of a semiconductor, a base region 32 made of a superconductor in contact with the collector region 31, and an extremely thin insulating layer 33 in which a tunnel phenomenon can occur in the base region 32 are formed. And an emitter region 34 made of a superconductor.
（ハ） 発明が解決しようとする課題 近接効果型トランジスタを製造するには、半導体と超
電導体の積層化が必要であり、前述の従来例において
は、半導体としてシリコン単結晶板を用いるとともに、
超電導体として鉛合金を用いており、鉛合金超電導体の
臨界温度が低いことから使用温度を低くする必要があ
る。このため、超電導体として、相対的に臨界温度が高
い高温酸化物超電導体を用いることが望まれる。この高
温酸化物超電導体を超電導素子として用いる場合には、
基板上に超電導薄膜を形成して使用され、基板としては
通常SrTiO3単結晶、MgO単結晶が用いられる。そこでこ
の単結晶基板をして、従来例に用いたシリコン単結晶板
を用いることが考えられる。(C) Problems to be Solved by the Invention To manufacture a proximity effect transistor, it is necessary to laminate a semiconductor and a superconductor. In the above-described conventional example, a silicon single crystal plate is used as a semiconductor,
Since a lead alloy is used as the superconductor, the operating temperature needs to be lowered because the critical temperature of the lead alloy superconductor is low. Therefore, it is desired to use a high-temperature oxide superconductor having a relatively high critical temperature as the superconductor. When using this high-temperature oxide superconductor as a superconducting element,
A superconducting thin film is formed on a substrate and used. The substrate is usually a single crystal of SrTiO 3 or a single crystal of MgO. Therefore, it is conceivable to use the silicon single crystal plate used in the conventional example as this single crystal substrate.
ところがシリコン単結晶板上に酸化物超電導薄膜を形
成する場合には、両結晶体の格子定数の不一致等から良
質の超電導薄膜が得られていない。However, when an oxide superconducting thin film is formed on a silicon single crystal plate, a high-quality superconducting thin film has not been obtained due to a mismatch between lattice constants of both crystals.
また、トンネル注入型超電導トランジスタにあって
は、その概念構造が提案されているものの、トランジス
タ動作をする具体的構造の提案は未だなされていない。Although a conceptual structure of a tunnel injection superconducting transistor has been proposed, a specific structure for operating the transistor has not yet been proposed.
本発明はかかる点に鑑み発明されたものにして、半導
体上に良質な酸化物超電導薄膜を形成するとともにその
半導体と酸化物超電導薄膜との界面が良好である超電導
素子の製造方法を提供せんとするものである。The present invention has been made in view of the above points, and it is necessary to provide a method of manufacturing a superconducting element in which a good oxide superconducting thin film is formed on a semiconductor and an interface between the semiconductor and the oxide superconducting thin film is good. Is what you do.
（ニ） 課題を解決するための手段 本発明による超電導素子の製造方法は、Bi−Sr−Cu−
Ｏ単結晶体と、この単結晶体の一部にCaからなる薄膜を
形成した後、第２図に示す、第１ポイント（0.1μｍ、8
70℃）、第２ポイント（0.4μｍ、820℃）、第３ポイン
ト（1.6μｍ、820℃）、及び第４ポイント（1.5μｍ、8
70℃）（横軸:Ca−Ｆ膜厚、縦軸：アニール温度）で囲
まれる領域内で該単結晶体、及び薄膜をアニールするこ
とによってBi−Sr−Ca−Cu−Ｏの超電導領域を得ること
を特徴とする。(D) Means for Solving the Problems The method for manufacturing a superconducting element according to the present invention is characterized in that the
After forming an O single crystal and a thin film made of Ca on a part of the single crystal, a first point (0.1 μm, 8 μm) shown in FIG.
70 ° C.), 2nd point (0.4 μm, 820 ° C.), 3rd point (1.6 μm, 820 ° C.), and 4th point (1.5 μm, 8
(70 ° C.) (horizontal axis: Ca—F film thickness, vertical axis: annealing temperature), the single crystal and the thin film are annealed in a region surrounded by a Bi-Sr—Ca—Cu—O superconducting region. It is characterized by obtaining.
（ホ） 作用 本発明による超電導素子の製造方法は、半導体として
Bi−Sr−Cu−Ｏ単結晶体を用い、超電導領域としてこの
単結晶体の一部にCaを導入して得られるBi−Sr−Ca−Cu
−Ｏ超電導体を用いるものであるから、半導体上に、酸
化物超電導の構成組成元素以外の元素（不純物）を含ま
ず、且つその半導体の結晶系と同じ結晶系の酸化物超電
導領域を形成することができる。また、その酸化物超電
導領域の形成は熱平衡プロセスによるものであるから、
半導体と酸化物超電導領域の界面がダメージを受けず、
その界面を大きなポテンシャルバリアがない（ショット
キーバリアなどができない）ものとすることができ、超
電導素子に必要な界面が得られる。(E) Function The method for manufacturing a superconducting element according to the present invention is a
Bi-Sr-Ca-Cu obtained by using a Bi-Sr-Cu-O single crystal and introducing Ca into a part of this single crystal as a superconducting region
Since an -O superconductor is used, an oxide superconducting region which does not contain an element (impurity) other than a constituent element of oxide superconductivity and has the same crystal system as that of the semiconductor is formed on the semiconductor. be able to. Also, since the formation of the oxide superconducting region is due to the thermal equilibrium process,
The interface between the semiconductor and the oxide superconducting region is not damaged,
The interface can be made without a large potential barrier (a Schottky barrier or the like cannot be formed), and an interface necessary for a superconducting element can be obtained.
（ヘ） 実施例 〔第１実施例〕 第１図（ａ）及び（ｂ）は、本発明の基本構成を示す
超電導素子の製造工程を示す断面図である。この図面に
おいて、Bi−Sr−Cu−Ｏ単結晶体１の一部の上にCa−Ｆ
薄膜２を形成する。この状態で熱処理によりCa−Ｆ薄膜
２からの元素Caを単結晶体１に導入して単結晶体１の一
部を超電導領域３にするものである。(F) Example [First Example] FIGS. 1 (a) and 1 (b) are cross-sectional views showing steps of manufacturing a superconducting element showing a basic configuration of the present invention. In this drawing, Ca-F is added on a part of the Bi-Sr-Cu-O single crystal 1.
A thin film 2 is formed. In this state, the element Ca from the Ca—F thin film 2 is introduced into the single crystal body 1 by heat treatment to make a part of the single crystal body 1 into the superconducting region 3.
Bi−Sr−Cu−Ｏ単結晶体１を次のように作成した。 Bi-Sr-Cu-O single crystal 1 was prepared as follows.
即ち、Bi2O3、SrCO3、CuO粉末を、Bi:Sr:Cu＝2:2:1の
割合で混合してアルミナボートに入れ、950℃以上の温
度で溶融し、徐冷速度３℃／時で徐冷する。That is, Bi 2 O 3 , SrCO 3 , and CuO powder were mixed at a ratio of Bi: Sr: Cu = 2: 2: 1, put into an alumina boat, melted at a temperature of 950 ° C. or more, and gradually cooled at a rate of 3 ° C. Cool slowly at / hour.
得られた塊体をヘキ開し、縦4mm、横3mm、厚み0.2mm
の大きさにした。この塊体をＸ線回析によって調べたと
ころ、Bi2Sr2CuOX（2201相または秋光相）の単結晶であ
ることが確認された。Open the obtained lump, 4mm long, 3mm wide, 0.2mm thick
The size of. When this mass was examined by X-ray diffraction, it was confirmed that the mass was a single crystal of Bi 2 Sr 2 CuO X (2201 phase or autumn light phase).
このようにして得られた単結晶体１の一部の上にCa−
Ｆ薄膜２を形成する。この実施例ではCa−Ｆ薄膜２を電
子ビーム蒸着法により形成した。その条件は、基板とし
ての単結晶体１を100〜300℃とし、ソース源としてCaF2
を用い、電子ビーム加速電圧を4kV、電子ビーム電流を1
mAとし、その成膜速度は10Å／秒であり、Ca−Ｆ薄膜２
を厚み50〜500nmにした。この場合のCa−Ｆ薄膜のパタ
ーニングは、メタルマスクによるマスク蒸着あるいはリ
フトオフ法により行った。このようにして得られたCa−
Ｆ薄膜２はICP分析によってCaF2であることを確認し
た。On a part of the single crystal body 1 thus obtained, Ca-
An F thin film 2 is formed. In this embodiment, the Ca-F thin film 2 was formed by an electron beam evaporation method. The conditions are as follows: the single crystal body 1 as a substrate is 100 to 300 ° C., and CaF 2
With an electron beam acceleration voltage of 4 kV and an electron beam current of 1
mA, the deposition rate was 10 ° / sec, and the Ca-F thin film 2
Has a thickness of 50 to 500 nm. In this case, patterning of the Ca—F thin film was performed by mask evaporation using a metal mask or a lift-off method. The thus obtained Ca-
The F thin film 2 was confirmed to be CaF 2 by ICP analysis.
第１図（ａ）に示すように、単結晶体１の一部の上に
Ca−Ｆ薄膜２を形成したものを、熱処理することによ
り、第１図（ｂ）に示す超電導領域３を形成した。この
超電導領域３はCa−Ｆ薄膜２から元素CaをBi−Sr−Cu−
Ｏ単結晶体１に取り込んだものである。従って超電導領
域３はBi−Sr−Ca−Cu−Ｏの組成であり、単結晶体１の
半導体と酸化物超電導領域３の界面がダメージを受け
ず、その界面を大きなポテンシャルバリアがないものと
することができ、超電導素子に必要な界面が得られる。As shown in FIG. 1 (a), on a part of the single crystal body 1,
The Ca-F thin film 2 was formed and heat-treated to form a superconducting region 3 shown in FIG. 1 (b). The superconducting region 3 converts the element Ca from the Ca—F thin film 2 into Bi—Sr—Cu—.
It is taken into the O single crystal body 1. Therefore, the superconducting region 3 has a composition of Bi-Sr-Ca-Cu-O, and the interface between the semiconductor of the single crystal body 1 and the oxide superconducting region 3 is not damaged and the interface has no large potential barrier. And an interface necessary for the superconducting element can be obtained.
このような良好なBi−Sr−Ca−Cu−Ｏ超電導体が得ら
れるCa−Ｆ薄膜２の膜厚と熱処理温度の関係を第２図に
示す。この図面は熱処理時間を30時間とした場合を示
す。この図面から例えば870℃の熱処理温度では、Ca−
Ｆ薄膜２の厚みが0.1〜1.5μｍとすれば、良好なBi−Sr
−Ca−Cu−Ｏ超電導体が得られることがわかる。超電導
領域３はＸ線回析によりBi2Sr2CaCu2OX（2212相）構造
であることを確認した。また、超電導領域３は母体であ
るBi−Sr−Cu−Ｏ単結晶体１のＣ軸面に沿って配向して
いることがわかった。FIG. 2 shows the relationship between the film thickness of the Ca—F thin film 2 and the heat treatment temperature at which such a good Bi—Sr—Ca—Cu—O superconductor is obtained. This drawing shows a case where the heat treatment time is 30 hours. From this drawing, for example, at a heat treatment temperature of 870 ° C., Ca-
If the thickness of the F thin film 2 is 0.1 to 1.5 μm, good Bi-Sr
It can be seen that a -Ca-Cu-O superconductor is obtained. X-ray diffraction confirmed that the superconducting region 3 had a Bi 2 Sr 2 CaCu 2 O X (2212 phase) structure. In addition, it was found that superconducting region 3 was oriented along the C-axis plane of Bi-Sr-Cu-O single crystal body 1 as a base.
Bi−Sr−Cu−Ｏ単結晶体１及びBi−Sr−Ca−Cu−Ｏ超
電導領域３の電気特性の一例として抵抗温度特性を測定
した。その結果をそれぞれ第３図及び第４図に示す。第
３図から単結晶体１は8Kぐらいまでほぼフラットな特性
を示すことがわかる。一方、第４図から超電導領域３は
ほぼ90Kまで金属的な温度特性を示し、84Kでゼロ抵抗に
なることを確認した。Resistance temperature characteristics were measured as an example of the electrical characteristics of the Bi-Sr-Cu-O single crystal 1 and the Bi-Sr-Ca-Cu-O superconducting region 3. The results are shown in FIGS. 3 and 4, respectively. From FIG. 3, it can be seen that the single crystal body 1 shows a substantially flat characteristic up to about 8K. On the other hand, it was confirmed from FIG. 4 that the superconducting region 3 exhibited metallic temperature characteristics up to approximately 90K, and became zero resistance at 84K.
Bi−Sr−Ca−Cu−Ｏ超電導体は、母体のBi−Sr−Cu−
Ｏ単結晶体のab軸面の格子定数が変わらず、Cu−Ｏ面の
数が１面から２面になることで得られている。このよう
にして半導体の性質を有するBi−Sr−Cu−Ｏ単結晶体の
表面に、Bi−Sr−Ca−Cu−Ｏ超電導体が得られた。この
両者は同一組成系で構成されているため超電導体と半導
体の界面が良好であり、且つ安定となる。Bi-Sr-Ca-Cu-O superconductor is based on the base material Bi-Sr-Cu-
It is obtained by changing the lattice constant of the ab-axis plane of the O single crystal body and changing the number of Cu—O planes from one plane to two planes. Thus, a Bi-Sr-Ca-Cu-O superconductor was obtained on the surface of the Bi-Sr-Cu-O single crystal having semiconductor properties. Since both are composed of the same composition system, the interface between the superconductor and the semiconductor is good and stable.
〔第２実施例〕 この実施例は第１実施例で得られる超電導体と半導体
の接合を利用して、超電導ベーストランジスタを形成す
るものである。[Second Embodiment] In this embodiment, a superconducting base transistor is formed by using the junction between the superconductor and the semiconductor obtained in the first embodiment.
第５図（ａ）〜（ｃ）は超電導ベーストランジスタの
製造工程を示す断面図である。同図（ａ）は第１実施例
で得られたもの、即ち超電導領域３を一部に有する単結
晶体１を示す。この単結晶体１の表面をArイオンエッチ
ングで軽くエッチングした後、同図（ｂ）に示すように
絶縁膜４としてMgO膜をリフトオフ法により40〜80Å形
成する。Arイオンエッチングはアルゴンガスを10sccm、
酸素ガスを17sccm供給して圧力3.4×10-4Torrの下で、
加速電圧を200V、供給電流1.2mAとして行う。5 (a) to 5 (c) are cross-sectional views showing the steps of manufacturing a superconducting base transistor. FIG. 1A shows a single crystal 1 obtained in the first embodiment, that is, a single crystal 1 having a superconducting region 3 in part. After the surface of the single crystal 1 is lightly etched by Ar ion etching, an MgO film is formed as an insulating film 4 by a lift-off method at 40 to 80 ° as shown in FIG. Ar ion etching is 10 sccm argon gas,
At a pressure of 3.4 × 10 -4 Torr by supplying oxygen gas at 17 sccm,
The acceleration voltage is 200 V and the supply current is 1.2 mA.
この絶縁膜４の上に、エミッタ電極となるBi−Sr−Ca
−Cu−Ｏ超電導体５とベース電極となるBi−Sr−Ca−Cu
−Ｏ超電導体６をrfスパッタリング法により形成する。
このrfスパッタリングは、Bi2.3Sr2Ca2Cu3.5OXの焼結タ
ーゲットを用い、ベルジャ内に純度99.9995％のアルゴ
ンガスと純度99.999％の酸素ガスを比1:1の割合で８×1
0-3Torrの圧力で供給すると共に単結晶体１及び絶縁膜
４を600℃として、スパッタ成膜速度１Å／秒とした。On this insulating film 4, Bi-Sr-Ca serving as an emitter electrode is formed.
-Cu-O superconductor 5 and Bi-Sr-Ca-Cu to be a base electrode
-O superconductor 6 is formed by rf sputtering.
This rf sputtering is performed using a sintered target of Bi 2.3 Sr 2 Ca 2 Cu 3.5 O X , and 8 × 1 argon gas having a purity of 99.9995% and oxygen gas having a purity of 99.999% at a ratio of 1: 1 in a bell jar.
The single crystal body 1 and the insulating film 4 were supplied at a pressure of 0 -3 Torr, the temperature was set at 600 ° C., and the sputter deposition rate was 1 ° / sec.
また、母体となる単結晶体１の裏面にコレクタ電極と
なる金属膜７を設ける。この金属膜としてはAu、Ag、P
t、Al、Cr等を用いることができ、この実施例ではAu膜
を抵抗加熱法により１μｍの厚みに形成する。Further, a metal film 7 serving as a collector electrode is provided on the back surface of the single crystal body 1 serving as a base. Au, Ag, P
t, Al, Cr, etc. can be used. In this embodiment, an Au film is formed to a thickness of 1 μm by a resistance heating method.
このようにして、超電導ベーストランジスタが構成さ
れ、エミッタ電極であるBi−Sr−Ca−Cu−Ｏ超電導体５
とベース電極であるBi−Sr−Ca−Cu−Ｏ超電導体６は、
超電導体・絶縁体・超電導体を構成し、コレクタである
Bi−Sr−Cu−Ｏ単結晶体１がベース電極であるBi−Sr−
Ca−Cu−Ｏ超電導体６に接合されている。従って、エミ
ッタから準粒子がベースに注入され、コレクタから引き
出されることになり、トランジスタ動作を行うことにな
る。In this manner, a superconducting base transistor is formed, and the Bi—Sr—Ca—Cu—O superconductor 5 serving as an emitter electrode is formed.
And the Bi-Sr-Ca-Cu-O superconductor 6, which is a base electrode,
Constructs superconductor, insulator, and superconductor, and is a collector
Bi-Sr- in which the Bi-Sr-Cu-O single crystal 1 is a base electrode
It is joined to the Ca—Cu—O superconductor 6. Therefore, quasiparticles are injected into the base from the emitter and are extracted from the collector, thereby performing a transistor operation.
〔第３実施例〕 この実施例は第１実施例で得られる超電導体と半導体
の接合を利用して、超電導FETを形成するものである。[Third Embodiment] In this embodiment, a superconducting FET is formed by using the junction between the superconductor and the semiconductor obtained in the first embodiment.
第６図（ａ）〜（ｂ）は超電導FETの製造工程を示す
断面図である。同図（ａ）は第１実施例と同様にBi−Sr
−Cu−Ｏ単結晶体１上に２箇所分離してCa−Ｆ薄膜８、
９を形成した状態を示す。Bi−Sr−Cu−Ｏ単結晶体１は
第１実施例で得たものと同じである。Ca−Ｆ薄膜８、９
の形成方法は第１実施例と同じであるが、膜厚は0.1〜
0.2μｍとし、両薄膜８、９をその微小間隙が0.1〜2.0
μｍになるように微細にパターニングする。また熱処理
条件は、一方のCa−Ｆ薄膜８からの元素Caが取り込まれ
て形成されるBi−Sr−Ca−Cu−Ｏ超電導領域10と、他方
のCa−Ｆ薄膜９からの元素Caが取り込まれて形成される
Bi−Sr−Ca−Cu−Ｏ超電導領域11とが単結晶体１内でつ
ながる条件の一歩手前の条件を求める必要がある。この
実施例では、Ca−Ｆ薄膜８、９の膜厚が0.2μｍ、両薄
膜８、９の微小間隙が２μｍとしたとき、熱処理条件を
860℃で10時間として、同図（ｂ）に示すBi−Sr−Ca−C
u−Ｏ超電導領域10と11を形成した。この超電導領域10
と11の構造及び電気特性は第１実施例の超電導領域３と
同じであった。6 (a) and 6 (b) are cross-sectional views showing the steps of manufacturing the superconducting FET. FIG. 9A shows a Bi-Sr similar to the first embodiment.
A Ca—F thin film 8 separated into two portions on a Cu—O single crystal body 1,
9 shows a state in which 9 is formed. The Bi-Sr-Cu-O single crystal 1 is the same as that obtained in the first embodiment. Ca-F thin films 8, 9
Is the same as that of the first embodiment except that the film thickness is 0.1 to
The thickness of both thin films 8 and 9 is set to 0.1 to 2.0 μm.
Finely pattern to a thickness of μm. The heat treatment conditions are such that Bi-Sr-Ca-Cu-O superconducting region 10 formed by taking in elemental Ca from one Ca-F thin film 8 and elemental Ca from the other Ca-F thin film 9 Formed
It is necessary to find a condition one step before the condition in which the Bi-Sr-Ca-Cu-O superconducting region 11 is connected in the single crystal body 1. In this embodiment, when the thickness of the Ca—F thin films 8 and 9 is 0.2 μm and the minute gap between the two thin films 8 and 9 is 2 μm,
Bi-Sr-Ca-C shown in FIG.
The u-O superconducting regions 10 and 11 were formed. This superconducting region 10
The structures and electrical characteristics of the superconducting regions 3 and 11 were the same as those of the superconducting region 3 of the first embodiment.
この超電導領域10と11を有する単結晶体１の表面をAr
イオンエッチングで前述と同様に軽くエッチングした
後、同図（ｃ）に示すように絶縁膜12としてのMgO膜を
リフトオフ法により2000〜8000Å形成する。また、ゲー
ト絶縁膜となる絶縁膜13としてのMgO膜を新たにリフト
オフ法により30〜150Å形成する。The surface of the single crystal body 1 having the superconducting regions 10 and 11 is Ar
After light etching by ion etching in the same manner as described above, an MgO film as the insulating film 12 is formed at 2000 to 8000 ° by a lift-off method as shown in FIG. Further, an MgO film as an insulating film 13 serving as a gate insulating film is newly formed by a lift-off method at 30 to 150 °.
次に、同図（ｃ）に示すように、ソース、ドレイン、
及びゲートとなる各電極を同図（ｄ）に示すようにAu、
Pt、TiあるいはAg等で形成する。実施例ではAuを蒸着に
よりソース電極14、ドレイン電極15及びゲート電極16を
形成した。両超電導領域10と11の間のチャンネル部17は
Bi−Sr−Cu−Ｏの単結晶であり、ソース電極14及びドレ
イン電極15はBi−Sr−Ca−Cu−Ｏ超電導領域に設けられ
ているので、全体としてFETの動作をする。Bi系超電導
体のコヒーレンス長は比較的短いが、ｃ軸方向よりab軸
方向のコヒーレンス長が長いため、このFETはab軸方向
のキャリアの移動を利用することができる。また、同一
組成系で形成されるため、Bi−Sr−Cu−Ｏ単結晶体１及
びBi−Sr−Ca−Cu−Ｏ超電導領域10、11との界面が良好
である。さらに、Ca−Ｆ薄膜８、９からの元素CaのBi−
Sr−Cu−Ｏ単結晶体１内の横方向の拡散を利用すること
ができるので、ソースとドレインの間隔をパターニング
するよりも微細に制御することができる （ト） 発明の効果 本発明による超電導素子は、Bi−Sr−Cu−Ｏ単結晶体
とこの単結晶体の一部にCaを導入して得られるBi−Sr−
Ca−Cu−Ｏの超電導領域とで構成されるものであるか
ら、単結晶体と超電導体が同一組成系で形成されること
になり、単結晶体と超電導体の界面を良好にすることが
できる。Next, as shown in FIG.
And each electrode serving as a gate is Au, as shown in FIG.
It is formed of Pt, Ti, Ag or the like. In the embodiment, the source electrode 14, the drain electrode 15, and the gate electrode 16 are formed by depositing Au. The channel portion 17 between the two superconducting regions 10 and 11 is
Since it is a single crystal of Bi-Sr-Cu-O and the source electrode 14 and the drain electrode 15 are provided in the Bi-Sr-Ca-Cu-O superconducting region, the FET operates as a whole. Although the coherence length of the Bi-based superconductor is relatively short, since the coherence length in the ab-axis direction is longer than that in the c-axis direction, this FET can use carrier movement in the ab-axis direction. Further, since they are formed with the same composition system, the interface with the Bi—Sr—Cu—O single crystal 1 and the Bi—Sr—Ca—Cu—O superconducting regions 10 and 11 is good. Furthermore, Bi- of elemental Ca from the Ca—F thin films 8 and 9
Since the lateral diffusion in the Sr—Cu—O single crystal body 1 can be used, the distance between the source and the drain can be more finely controlled than by patterning. (G) Effect of the present invention Superconductivity according to the present invention The element is a Bi-Sr-Cu-O single crystal and a Bi-Sr- obtained by introducing Ca into a part of the single crystal.
Since it is composed of the superconducting region of Ca-Cu-O, the single crystal and the superconductor are formed in the same composition system, and it is possible to improve the interface between the single crystal and the superconductor. it can.
第１図乃至第４図は第１の実施例を示し、第１図は本発
明の基本構成を示す超電導素子の製造工程を示す断面
図、第２図はCa−Ｆ薄膜の膜厚と熱処理温度の関係説明
図、第３図はBi−Sr−Cu−Ｏ単結晶体の抵抗温度特性
図、第４図は、Bi−Sr−Ca−Cu−Ｏ超電導領域の抵抗温
度特性図、第５図は第２の実施例を示し、超電導ベース
トランジスタの製造工程を示す断面図、第６図は第２の
実施例を示し、超電導FETの製造工程を示す断面図、第
７図及び第８図は従来の超電導トランジスタの断面図で
ある。 １……Bi−Sr−Cu−Ｏ単結晶体、２、８、９……Ca−Ｆ
薄膜、３、10、11……Bi−Sr−Ca−Cu−Ｏ超電導領域、
４、12、13……絶縁膜、５、６……超電導体、７……金
属膜、14……ソース電極、15……ドレイン電極、16……
ゲート電極、17……チャンネル部。1 to 4 show a first embodiment, FIG. 1 is a sectional view showing a manufacturing process of a superconducting element showing a basic structure of the present invention, and FIG. 2 is a diagram showing the thickness and heat treatment of a Ca-F thin film. FIG. 3 is a diagram showing the relationship between temperature, FIG. 3 is a diagram showing a resistance temperature characteristic of a Bi—Sr—Cu—O single crystal, FIG. 4 is a diagram showing a resistance temperature characteristic of a Bi—Sr—Ca—Cu—O superconducting region, and FIG. FIG. 6 shows a second embodiment, and is a cross-sectional view showing a manufacturing process of a superconducting base transistor. FIG. 6 shows a second embodiment and is a cross-sectional view showing a manufacturing process of a superconducting FET. FIG. 2 is a sectional view of a conventional superconducting transistor. 1. Bi-Sr-Cu-O single crystal, 2, 8, 9 ... Ca-F
Thin film, 3, 10, 11 ... Bi-Sr-Ca-Cu-O superconducting region,
4, 12, 13 ... insulating film, 5, 6 ... superconductor, 7 ... metal film, 14 ... source electrode, 15 ... drain electrode, 16 ...
Gate electrode, 17 ... channel part.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−194569（ＪＰ，Ａ) 特開 平２−194668（ＪＰ，Ａ) 特開 平１−282187（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 39/00 H01L 39/22 H01L 39/24 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-194569 (JP, A) JP-A-2-194668 (JP, A) JP-A 1-282187 (JP, A) (58) Field (Int.Cl. 6 , DB name) H01L 39/00 H01L 39/22 H01L 39/24
Claims (1)
の一部にCaからなる薄膜を形成した後、第２図に示す、
第１ポイント（0.1μｍ、870℃）、第２ポイント（0.4
μｍ、820℃）、第３ポイント（1.6μｍ、820℃）、及
び第４ポイント（1.5μｍ、870℃）（横軸:Ca−Ｆ膜
厚、縦軸：アニール温度）で囲まれる領域内で該単結晶
体、及び薄膜をアニールすることによってBi−Sr−Ca−
Cu−Ｏの超電導領域を得ることを特徴とする超電導素子
の製造方法。1. After forming a Bi-Sr-Cu-O single crystal and a thin film made of Ca on a part of the single crystal, as shown in FIG.
1st point (0.1μm, 870 ℃), 2nd point (0.4
μm, 820 ° C.), the third point (1.6 μm, 820 ° C.), and the fourth point (1.5 μm, 870 ° C.) (horizontal axis: Ca—F film thickness, vertical axis: annealing temperature) By annealing the single crystal and the thin film, Bi-Sr-Ca-
A method for manufacturing a superconducting element, comprising obtaining a superconducting region of Cu-O.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252218A JP2950958B2 (en) | 1990-09-21 | 1990-09-21 | Superconducting element manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252218A JP2950958B2 (en) | 1990-09-21 | 1990-09-21 | Superconducting element manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04130782A JPH04130782A (en) | 1992-05-01 |
| JP2950958B2 true JP2950958B2 (en) | 1999-09-20 |
Family
ID=17234155
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|---|---|---|---|
| JP2252218A Expired - Fee Related JP2950958B2 (en) | 1990-09-21 | 1990-09-21 | Superconducting element manufacturing method |
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| Country | Link |
|---|---|
| JP (1) | JP2950958B2 (en) |
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1990
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|---|---|
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