JPS61237434A - Mounting of semiconductor chip - Google Patents

Mounting of semiconductor chip

Info

Publication number
JPS61237434A
JPS61237434A JP7835085A JP7835085A JPS61237434A JP S61237434 A JPS61237434 A JP S61237434A JP 7835085 A JP7835085 A JP 7835085A JP 7835085 A JP7835085 A JP 7835085A JP S61237434 A JPS61237434 A JP S61237434A
Authority
JP
Japan
Prior art keywords
chip
chips
lsi
bus
ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7835085A
Other languages
Japanese (ja)
Inventor
Kazuhiko Iwasaki
一彦 岩崎
Mitsunori Ketsusako
光紀 蕨迫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7835085A priority Critical patent/JPS61237434A/en
Publication of JPS61237434A publication Critical patent/JPS61237434A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce signal delays between semiconductor chips and at the same time improve heat radiation efficiency by connecting one side ends of the chips in a ring shape. CONSTITUTION:LSI chips 1, 2...18 are connected in a central connection part 19. The central connection part 19 is constituted by a cylinder 60 made of insulation material, ring wirings 40-44 provided on the cylinder 60 and thru- holes 45-47 connecting the ring wirings to the inside of the cylinder 60. A bus 40 consists of a plurality of the ring wirings and is connected to all the chips 1, 2...18. A bus 41 also consists of a plurality of the ring wirings and is connected to all the LSI chips 1, 2...18. The ring wirings 42-44 provide a source, a ground and a clock. Every chip is individually air-cooled. If the number of the connected LSI chips is not more than 100, the load capacity of the bus is not more than 10pF.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体チップの実装方式に係り、特にチップ
間の信号遅延を小さくシ、かつ放熱効果にもすぐれた半
導体チップの実装方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor chip mounting method, and more particularly to a semiconductor chip mounting method that reduces signal delay between chips and has excellent heat dissipation effects.

〔発明の背景〕[Background of the invention]

半導体チップの３次元実装方式として、従来はア・イー
・イー・イー、コンピュータ、Ｐ６９〜８１、”ア・セ
ルラー・ヴイ・エル・ニス・アイ・アーキテクチャ−、
”　１９８４年１月刊（Ｉｔ！ＩＩ！Ｅ。Conventionally, as a three-dimensional mounting method for semiconductor chips, A.E.I.
” January 1984 (It!II!E.

Ｃｏｍｐｕｔｅｒ、　　ｐ　　６　９〜８　１　　”　
Ａ　　Ｃｅ１ｌｕｌａｒ　　ＶＬＳＩＡｒｃｈｉｔｅｃ
ｔｕｒｅ’　Ｊａｎｕａｒｙ　１９８４）に示されるよ
うに、各チップを重ね合わせる方式が提案されていた。Computer, p69~81”
A Ce1lular VLSIA Architecture
ture' January 1984), a method of overlapping each chip was proposed.

しかし、各チップが発生する熱の放熱に関する配慮がな
されていなかった。However, no consideration was given to dissipating the heat generated by each chip.

〔発明の目的〕[Purpose of the invention]

本発明は、チップ間の信号遅延を小さくするとともに、
放熱効果も高い半導体チップ実装方式を提供することに
ある。The present invention reduces signal delay between chips, and
The object of the present invention is to provide a semiconductor chip mounting method that also has a high heat dissipation effect.

〔発明の概要と実施例〕[Summary of the invention and examples]

以下、本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図は１本発明の一実施例を表す図である。FIG. 1 is a diagram showing an embodiment of the present invention.

第１図において、ＬＳＩチップ１，２・・・、１８は、
それぞれ中心接続部１９で接続されている。In FIG. 1, LSI chips 1, 2..., 18 are as follows:
They are connected through a central connection part 19, respectively.

ＬＳＩチップ５はディスク制御用のＬＳＩとする。The LSI chip 5 is assumed to be an LSI for disk control.

ディスク制御用の信号線はボンディング線２０゜２１．
２２を通して、別の基板２３へ接続される。The signal line for disk control is the bonding line 20°21.
22, it is connected to another board 23.

基板２３からは通常のシールド線２４，２５．２６を通
して、ディスク２７を制御する。A disk 27 is controlled from the substrate 23 through ordinary shielded wires 24, 25, and 26.

ＬＳＩチップ１４はＣＲＴ　（Ｃａｔｈｏｄｅ　Ｒａｙ
　Ｔｕｂｅ）制御用のＬＳＩとする。ＣＲＴ制御用の信
号線はボンディング線２８，２９．３０を通して、別の
基板３６１へ接続される。基板３１からは通常のシール
ド線３２，３３．３４を通してＣＲＴ３５を制御する。The LSI chip 14 is a CRT (Cathode Ray).
(Tube) is an LSI for control. CRT control signal lines are connected to another board 361 through bonding lines 28, 29, and 30. A CRT 35 is controlled from the board 31 through ordinary shielded wires 32, 33, and 34.

第２図は、第１図における中心結合部１９の構造を示す
図であり、ＬＳＩチップ１，１０のみが接続されている
。中心結合部１９は、絶縁物質から成る円筒６０と、同
筒上のリング配線４０，４１．４２，４３．４４と、リ
ング配線と円筒の内側を接続するスルーホール４５，４
６．４７から成る。FIG. 2 is a diagram showing the structure of the central coupling portion 19 in FIG. 1, in which only the LSI chips 1 and 10 are connected. The central joint part 19 includes a cylinder 60 made of an insulating material, ring wirings 40, 41, 42, 43, 44 on the cylinder, and through holes 45, 4 that connect the ring wirings to the inside of the cylinder.
Consists of 6.47.

バス４０は、複数のリング配線から成っており、第２図
ではＬＳＩチップ１，１０に接続されている。第１図で
は、すべてのＬＳＩチップ１，２・・・１９へ接続され
ている。バス４１も同様に、複数のリング配線から成っ
ており、第２図ではＬＳＩチップ１，１０に、第１図で
はすべてのＬＳＩチップ１，２．’　１９．に接続され
ている。バス４０はアドレスバスおよびメモリアクセス
制御信号として使用される。バス４０はＭＰＵ　（にｉ
ｃｒ。The bus 40 is made up of a plurality of ring wiring lines, and is connected to the LSI chips 1 and 10 in FIG. In FIG. 1, it is connected to all LSI chips 1, 2, . . . , 19. Similarly, the bus 41 is made up of a plurality of ring wirings, and is connected to LSI chips 1 and 10 in FIG. 2, and all LSI chips 1, 2 . '19. It is connected to the. Bus 40 is used as an address bus and memory access control signals. Bus 40 is MPU
cr.

Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）　Ｌ　Ｓ　Ｉチップ
と、メモリＬＳＩチップあるいは周辺ＬＳＩチップとの
間の読み出し／書き込みの制御のためのバスである。バ
ス４１は双方向のデータバスである。第２図においてＬ
ＳＩチップ１はＭＰＵＬＳＩチップとし、ＬＳＩチップ
１ｏがルモリＬＳＩチップとする。このとき、ＬＳＩチ
ップ１はバス４０の信号線（アドレス線。Processing Unit) A bus for controlling read/write between the LSI chip and the memory LSI chip or peripheral LSI chip. Bus 41 is a bidirectional data bus. In Figure 2, L
The SI chip 1 is an MPULSI chip, and the LSI chip 1o is a Lumory LSI chip. At this time, the LSI chip 1 is connected to the signal line (address line) of the bus 40.

アドレスストローブ線、データストローブ線など）を駆
動してＬＳＩチップ１０をアクセスする。読み出し／書
き込みデータはバス４１を通して、ＬＳＩチップ１，１
０の間で転送される。(address strobe line, data strobe line, etc.) to access the LSI chip 10. Read/write data is sent to the LSI chips 1, 1 through the bus 41.
Transferred between 0 and 0.

リング配線４２．４３．４４は、それぞれ電源、接地、
クロックを供給するための配線である。リング配線４２
，４３，４４はそれぞれ、スルーホール４５，４６，４
７および配線４８，４９゜５０を通して、外部の電源、
接地、クロックへ接続される。Ring wires 42, 43, and 44 are for power, ground, and
This is the wiring for supplying the clock. Ring wiring 42
, 43 and 44 are through holes 45, 46 and 4, respectively.
7 and wiring 48, 49° 50, an external power supply,
Ground, connected to clock.

第３図は、第１図の中心結合部１９とＬＳＩチップ１の
接続法について示す図である。特に。FIG. 3 is a diagram showing a method of connecting the center coupling portion 19 of FIG. 1 and the LSI chip 1. especially.

ＬＳＩチップ１のクロック入力線７０と中心結合部１９
のクロック用リング配線４４の接続を示すものである。Clock input line 70 and center coupling part 19 of LSI chip 1
3 shows the connection of the clock ring wiring 44 in FIG.

ＬＳＩチップ１のクロック入力線７０に対し、チップの
ダイシング端にハンダバンブ７１を乗せる。これをリン
グ配線４４に圧着させる。圧着させた後は、外部からの
クロックは、配線５０．スルーホール４７．リング配線
４４゜ハンダバンプ７１．配線７０を通してＬＳＩチッ
プ１内のＣＰ　Ｇ　（Ｃ１ｏｃｋ　Ｐｕ１ｓｅ　Ｇｅｎ
ｅｒａｔｏｒ）　７２　ヘ到着する。A solder bump 71 is placed on the clock input line 70 of the LSI chip 1 at the dicing end of the chip. This is crimped onto the ring wiring 44. After crimping, the external clock is connected to the wiring 50. Through hole 47. Ring wiring 44° solder bump 71. The CPG (C1ock Pulse Gen) inside the LSI chip 1 is connected through the wiring 70.
Arrive at 72.

次に本発明の他の実施例を説明する。Next, another embodiment of the present invention will be described.

ここでは、半導体チップを３次元的に接続する実装方式
において、特に、各チップの大きさが異なる半導体チッ
プを実装する場合に好適な半導体チップ接続方式を提供
する。Here, in a mounting method for three-dimensionally connecting semiconductor chips, a semiconductor chip connecting method is provided that is particularly suitable for mounting semiconductor chips having different sizes.

ＬＳＩチップを積層化し実装する場合、各チップの大き
さが異なるという問題がある０例えば、多数枚のＬＳＩ
チップを積層して立方形状に形成されるワン・キューブ
・パソコンを積層化する場合、Ｍ　Ｐ　Ｕ　（Ｍｉｃｒ
ｏ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）　＃メモリ。When stacking and mounting LSI chips, there is a problem that the size of each chip is different. For example, if a large number of LSI
When stacking a one-cube computer, which is formed by stacking chips to form a cubic shape, MPU (Micr
o Processing Unit) #Memory.

周辺ＬＳＩなどを、ワン・キューブ化する必要がある。It is necessary to make peripheral LSIs into one cube.

この場合、ＭＰＵチップ、メモリチップ。In this case, MPU chip, memory chip.

周辺ＬＳＩチップは各々独立に最適化設計がなされるた
め、個々のチップサイズが異なる。このため、上下のチ
ップ間の配線の整合を取ることが問題となる。Since each peripheral LSI chip is independently optimized and designed, each chip size is different. Therefore, it becomes a problem to match the wiring between the upper and lower chips.

とくに一部の及チップを改良した場合に、チップサイズ
が変更されることがあり、従来の積層接続方式ではこの
種の要求に対応することができなかった０本発明は、各
チップの配線位置を工夫することにより、設計変更に対
する柔軟性をもたせたことが特徴である。In particular, when some chips are improved, the chip size may change, and the conventional stacked connection method could not meet this type of demand.The present invention improves the wiring position of each chip. It is characterized by being flexible to design changes by devising the following.

第４図は本発明の実施例を示す図である。第４図におい
て、メモリチップ１はＭＰＵチップ２の上に実装される
。すなわち、ＭＰＵチップ２の斜線部にメモリチップ１
が乗せられる。このとき、メモリチップの頂点ａとＭＰ
Ｕチップの頂点ａ′を重ねるようにする。すなわち、積
層化の基準点として別々のチップの１つの頂点を利用す
るところに特徴がある。FIG. 4 is a diagram showing an embodiment of the present invention. In FIG. 4, memory chip 1 is mounted on MPU chip 2. In FIG. That is, the memory chip 1 is placed in the shaded area of the MPU chip 2.
is carried. At this time, the vertex a of the memory chip and MP
Make sure that the apexes a' of the U chips overlap. That is, the feature is that one vertex of separate chips is used as a reference point for stacking.

メモリチップｌには頂点ａを基準点として、スルーホー
ル１０，１１，１２，１３，１４．１５゜１６．１７，
１８，１９，２０，２１，２２゜２３．２４，２５，２
６，２７，２８，２９゜３０．３１，３２，３３，３４
，３５が配置されている、一方、ＭＰＵチップ２上には
、頂点ａ′を基準点として、スルーホール４０，４１，
４２゜４３．４４，４５，４６，４７，４８，４９゜５
０．５１，５２，５３，６４，５５，５６゜５７．５８
，５９，６０，６１，６２，６３゜６４．６５が配置さ
れている。The memory chip l has through holes 10, 11, 12, 13, 14.15°16.17, with apex a as a reference point.
18,19,20,21,22゜23.24,25,2
6, 27, 28, 29° 30. 31, 32, 33, 34
, 35 are arranged on the MPU chip 2. On the other hand, on the MPU chip 2, with the apex a' as a reference point, through holes 40, 41,
42゜43.44, 45, 46, 47, 48, 49゜5
0.51, 52, 53, 64, 55, 56°57.58
, 59, 60, 61, 62, 63°64.65 are arranged.

スルーホール１０〜３５はメモリチップ１の頂点ａを基
準点とし、スルーホール１０〜６５はＭＰＵチップ２の
頂点ａ′基準点としているため。The through holes 10 to 35 have the apex a of the memory chip 1 as a reference point, and the through holes 10 to 65 have the apex a' of the MPU chip 2 as a reference point.

メモリチップ１とＭＰＵチップ２を重ね合わせる場合、
頂点ａと頂点ａ′を重ね合わせれば、スルーホール１０
と４０．１１と４１・・・、３５と６５はそれぞれ接合
することができる。When stacking memory chip 1 and MPU chip 2,
If apex a and apex a' are overlapped, through hole 10
, 40, 11 and 41..., 35 and 65 can be joined, respectively.

又、スルーホールをチップの周辺部に配置すれば次のよ
うな効果がある。一部のチップのマスクをシュリンクさ
せる場合、チップ全体をシュリンクした後、スルーホー
ルに至る配線のみを変更すればよい、シュリンク後のチ
ップに対しても、１つの頂点を基準としてスルーホール
の位置を決め得る。Further, if the through holes are arranged at the periphery of the chip, the following effects can be obtained. If you want to shrink the mask of some chips, you only need to change the wiring leading to the through holes after shrinking the entire chip. I can decide.

またこの様な構造はチップ実装工程上の位置合わせに有
効であり、チップの２辺を強制することによって複数の
チップのスルーホールを自動的に整列させることができ
る。Further, such a structure is effective for alignment during the chip mounting process, and by forcing two sides of the chip, the through holes of a plurality of chips can be automatically aligned.

【発明の効果〕【Effect of the invention〕

以上のような実装方式を用いた場合には次のような効果
がある。When the above-mentioned mounting method is used, the following effects are obtained.

（１）放熱 各ＬＳＩチップ毎の空冷方式となっている。空冷が可能
なＬＳＩチップならば、第１図の実装方式を用いても問
題はない。(1) Heat dissipation Each LSI chip is air-cooled. If the LSI chip can be air cooled, there is no problem even if the mounting method shown in FIG. 1 is used.

（２）バスの負荷容量 各ＬＳＩチップをパッケージに収納し、基板上に実装す
る場合のバスの負荷容量は９０ＰＦ以上となる。一方、
第１図の実装方式によれば、接続するＬＳＩチップが１
００個以下ならば、バスの負荷容量は１０ｐＦ以下とな
る。これにより、各ＬＳＩチップ内の出力バッファの能
力が小さくて済み、消費電力が小さくなり、チップ面積
も減少する。(2) Bus load capacity When each LSI chip is housed in a package and mounted on a board, the bus load capacity is 90PF or more. on the other hand,
According to the mounting method shown in Figure 1, the number of LSI chips to be connected is one.
If the number is less than 00, the load capacitance of the bus is less than 10 pF. As a result, the capacity of the output buffer in each LSI chip is reduced, power consumption is reduced, and chip area is also reduced.

バスの負荷容量が減少した場合、ＭＰＵＬＳＩチップは
、メモリＬＳＩチップを高速にアクセスでき、システム
全体の高速動作が可能となる。When the load capacity of the bus is reduced, the MPULSI chip can access the memory LSI chip at high speed, and the entire system can operate at high speed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例を示す図、第２図は第１
の実施例の中心部の構成を示す図、第３図は中心部とチ
ップの接続法を示す図、第４図は本発明の第２の実施例
を示す図である。 冨　１　　図 ￥Ｊ３図FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a first embodiment of the present invention.
FIG. 3 is a diagram showing a method of connecting the center part and a chip, and FIG. 4 is a diagram showing a second embodiment of the present invention. Tomi 1 Figure ￥J3 figure

Claims (1)

【特許請求の範囲】[Claims] １、半導体チップの一端をリング状に接続することを特
徴とする半導体チップ実装方式。1. A semiconductor chip mounting method characterized by connecting one end of a semiconductor chip in a ring shape.
JP7835085A 1985-04-15 1985-04-15 Mounting of semiconductor chip Pending JPS61237434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7835085A JPS61237434A (en) 1985-04-15 1985-04-15 Mounting of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7835085A JPS61237434A (en) 1985-04-15 1985-04-15 Mounting of semiconductor chip

Publications (1)

Publication Number Publication Date
JPS61237434A true JPS61237434A (en) 1986-10-22

Family

ID=13659540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7835085A Pending JPS61237434A (en) 1985-04-15 1985-04-15 Mounting of semiconductor chip

Country Status (1)

Country Link
JP (1) JPS61237434A (en)

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