JPS61237138A - Data processor - Google Patents

Abstract

PURPOSE:To inform an uncorrectable error of a main storage device to a software by a simple constitution, by detecting with an execution processor even the uncorrectable error of the main storage device, which generates when an input/output processor is being operated. CONSTITUTION:In case an uncorrectable error is generated in the course of an access to a main storage device 1 from an input/output processor 3, the error is reported to an execution processor 2 through a signal line 101 from the device 1. As a result, in a state that an output to a signal line 107 from an AND gate 9 is '1', and an FF 7 is '1', an instruction end signal is sent to a signal line 103 from a main controlling circuit 4, an output of an AND gate 10 becomes '1', an interruption request for generating an exception is sent out to the circuit 4. This circuit 4 reads out detailed information from the inside of the device 1, when an insterruption is received, generates an exceptional message from its information, and informs it to a software.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a data processing device.

(Prior Art) When an uncorrectable error (read error of 2 or more bits) is detected in access from the execution processing unit to the main memory, the execution processing unit interrupts execution and retries the currently executed instruction. It is checked whether the command is in a retryable state, and if the command can be retried, the command is retried.

Also, if the instruction cannot be retried, stop executing the instruction,
Report this to the software.

In either case, it is necessary to notify the software that there is an uncorrectable error in the main memory. In addition to the software being notified in the form of an exception message that there was an uncorrectable error in the main memory,
The address information where this error occurred is also notified. This address information is typically held in a status holding register inside the main memory and read by a special command to the main memory (eg, a main memory status read command).

The software that receives the notification designates the area near the above address as a software-inhibited area, inhibits future use, and prevents the main memory uncorrectable error from occurring again.

On the other hand, if an uncorrectable error occurs while the input/output processing device is accessing the main storage device, the input/output processing device interrupts the channel program being executed and notifies the software of this fact as a channel exception. It is also necessary to notify the software that there is an uncorrectable error in the main memory. Reporting of uncorrectable errors in main memory during operation of an I/O processor is different from reporting during operation of an execution processor; the I/O processor itself directly reports software. Depending on timing issues, it is common for the input/output processing device to notify the software via the execution processing device rather than directly to the software.

If an uncorrectable error in the main memory is detected during the operation of the input/output processing unit, the input/output processing unit will transfer data to the execution processing unit's communication area (a defined area in the main memory). It records that there was an uncorrectable error and notifies the execution processor of the presence of the message. When the execution processing unit reads the contents of the communication area and recognizes that an uncorrectable error has occurred, it reads the contents of the status register inside the main memory, creates an exception message from this information, and notifies the software. .

(Problems to be Solved by the Invention) As explained above, when an uncorrectable error occurs in the main memory during the operation of the execution processing unit, the input/output processing unit does not independently notify the software; A means for notification via the execution processing unit is required, and furthermore, reliability is reduced if a communication area in the main memory is used where failures are inherent in communication with the execution processing unit. was there.

An object of the present invention is to constantly monitor the presence or absence of an uncorrectable error in the main memory by an execution processing unit, even if an uncorrectable error in the main memory occurs during operation of the input/output processing unit. To provide a data processing device configured to eliminate the above-mentioned drawbacks by detecting it by an execution processing unit and reporting it to software, and to notify software of an uncorrectable error in a main storage device using a simple table structure. It is in.

(Means for Solving the Problems) A data processing device according to the present invention is composed of a main storage device, at least one execution processing device, and at least one input/output processing device, and includes the above-mentioned at least 1
Each of the execution processing devices includes a monitoring means, a detection means, and a main control means.

The monitoring means is for constantly monitoring uncorrectable errors from the main memory, and the detecting means is for identifying whether or not the uncorrectable error is related to access to the main memory. It is.

If the uncorrectable error is not related to access to its own main memory, the main control means executes processing related to the uncorrectable error after completing execution of the instruction being executed when the uncorrectable error was detected. This is to notify you that.

(Example> Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. In FIG. 1, 1 is a main storage device, 2 is an execution processing device, and 3 is an input/output processing device.

In FIG. 1 showing a first embodiment of the present invention, a main storage device 1, an execution processing device 2, and an input/output processing device 3 are interconnected by a bus 100.

The bus 100 includes bus request signals, response signals, addresses, data, and the like.

FIG. 2 is a block diagram showing an uncorrectable error processing circuit included in the execution processing device 2. As shown in FIG.

In FIG. 2, 4 is the main control circuit, 5 to 7 are the first to third flip-flops, and 8 to 10 are the first flip-flops, respectively.
-This is the third AND gate.

The first 7-lip flop 5 receives as input a signal output from the main control circuit 4 onto the signal line 102 indicating that the right to use the bus 100 has been obtained, and outputs the signal on the signal line 104 as @"l#.
This indicates that the execution processing device 2 is using the bus 100 at the time of . The output signal on signal line 105 is of opposite polarity to the output signal on signal line 104. 1st A
The ND gate 8 connects one input to the first flip-flop 5.
The other input is an uncorrectable error signal sent from the bus 100 onto the signal line 101. The second AND gate 9 is
One input is connected from the first 7-lip flop 5 to the signal line 10.
5, and the other input is the signal line 1.
This is an uncorrectable error signal on 01. Second
The 7 lip-flop 6 receives the output from the first AND gate 8 onto the signal line 106 and outputs the error signal of the main memory onto the signal line 108.

The third 7-lip flop 7 inputs the output from the second AND gate 9 to the signal line 107, and receives the output from the input/output processing device [3].
A signal indicating that an uncorrectable error has occurred during access to the main memory device l is output onto the signal line 109.

The third AND game) 10 is connected to the signal line 1 from the main control circuit 4.
One input is the instruction completion signal on the 03, and the other input is output to the signal line 109 of the third 7-lip-flop 7, and an interrupt for the occurrence of an exception is sent to the main controller 4 via the signal line 110. It generates a signal. Execution processing device 2
When accessing the main memory l, the signal i! ! 11
The main storage device request signal on bus 10 is set to “1#.The main storage device 1 determines the priority, and the execution processing device 2
When the right to use 0 is granted, the accept signal on signal line 112 is set to 11#.

When the main control circuit 4 receives the accept signal on the signal line 112, it sets the signal on the signal line 102 to "1" and sets the first seven lip-flop 5 indicating that the bus is in use. When an uncorrectable error is detected during access to the main memory 1, the signal on the signal line 101 becomes @1'' and the first AN
The output signal line 106 of the D gate 8 is also set to "1", and the second flip-flop 6 is set to "1".

When the second flip-flop 6 is @1#, it indicates that an uncorrectable error has occurred during access in the main memory 1 of the execution processing unit 2, and the signal on the signal line 108 is @1''. A hardware error processing interrupt is requested to the main control circuit 4.The main control circuit 4 interrupts the process currently being executed.
Perform hardware error handling. In hardware error processing, it is determined whether the instruction being executed can be retried, and an exception is generated to the software. Regarding retry, detailed explanation will be omitted since it is not directly related to the present invention.

Next, if an uncorrectable error occurs while the input/output processing device 3 is accessing the main storage device 1, the execution processing device 2 is not accessing the main storage device 1, so the first flip-flop 5 is "O", and the output signal on the signal line 105 is "11". When an uncorrectable error is reported from the main memory device 1 on the signal line 101 in this state, the second AND gate The output from 9 to the signal line 107 is not "1", and the third 7-lip-flop 7 is set to @1#. With the third 7-lip-flop 7 set to @1", the main control circuit 4 to the end of the instruction (two signals indicating the end of one software instruction and indicating the break between instructions are sent onto the signal line 103, and when the state of this signal is set to 11#, the third AND game ) 10 to the signal line 110 becomes "1", and an interrupt request for generating an exception is sent to the main control circuit 4.

When the main control circuit 4 receives an interrupt, it reads detailed information from inside the main storage device 1, creates an exception message based on the read information, and notifies the software. Since the execution processing device 2 notifies the software between different instructions that an uncorrectable error has occurred in the main storage device 1, the instruction being executed is completed and retry processing is no longer necessary.

When the execution of one instruction is completed, control is transferred to the software (control program), and the control program reconfigures the main storage device l, and then resumes execution of the interrupted program. The input/output processing device 3 also recognizes the uncorrectable error from the main storage device 1, and reports as a channel exception that execution of the channel program cannot be continued.

In the above embodiments of the present invention, the case of one execution processing device and one input/output processing device has been explained, but in the case of a data processing device consisting of a plurality of execution processing devices and a plurality of input/output processing devices, There are two methods: one in which a single execution processing unit is responsible for monitoring uncorrectable errors, and another in which the execution processing units and input/output processing units are grouped together to report uncorrectable errors. Needless to say, these are also included within the scope of the invention.

(Effects of the Invention) As explained above, the present invention detects an uncorrectable error by the execution processing unit during access to the main memory from a single output processing unit, and notifies the software so that the input/output processing Compared to a data processing device in which the device detects an uncorrectable error and notifies the execution processing device, there is no need for a means to notify the execution processing device from the input/output processing device, and the control of the input/output processing device is simpler. This has the effect of increasing reliability by notifying the software of an exception without using the failed main memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. FIG. 2 is a circuit diagram showing an embodiment of the uncorrectable error processing circuit of the execution processing device shown in FIG. 1. 1... Main storage device 2... Execution processing device 3...
・I/O processing device 4...Main control circuit 5.6.7・
...Flip-flop 8, 9, 1 O-AND gate Patent applicant NEC Corporation Representative Patent attorney Jusai Inoro Figure 1 Figure 22

Claims (1)

[Claims] In a data processing device comprising a main storage device, at least one execution processing device, and at least one input/output processing device, each of the at least one execution processing device receives corrections from the main storage device. monitoring means for constantly monitoring uncorrectable errors; detecting means for identifying whether the uncorrectable error relates to access to the own main memory; If it is not related to memory access, a main control means for notifying to execute processing related to the uncorrectable error after the execution of the instruction being executed when the uncorrectable error is detected is completed. What is claimed is: 1. A data processing device comprising: