JPH03276245A - Cpu fault processing system - Google Patents

Cpu fault processing system

Info

Publication number
JPH03276245A
JPH03276245A JP2073302A JP7330290A JPH03276245A JP H03276245 A JPH03276245 A JP H03276245A JP 2073302 A JP2073302 A JP 2073302A JP 7330290 A JP7330290 A JP 7330290A JP H03276245 A JPH03276245 A JP H03276245A
Authority
JP
Japan
Prior art keywords
input
output device
address
fault
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2073302A
Other languages
Japanese (ja)
Inventor
Shuichi Yamano
修一 山野
Hideki Iwao
岩尾　秀樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2073302A priority Critical patent/JPH03276245A/en
Publication of JPH03276245A publication Critical patent/JPH03276245A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To carry on the information processing even with the faults occurred in an input/output device and at the interface part between the input/output device and a channel by providing a working-alternate address table for the input/output device and a fault flag corresponding to each input/output device. CONSTITUTION:The fault flags are simultaneously set to the working and alternate addresses. These flags are set at 1 by a report received from an input/ output device and the fault occurred at an interface part between the input/ output device and a channel. Then the fault flags are reset at 0 by a hardware reset instruction. meanwhile the working and alternate addresses are set on the address tables 3 and 4 in a preparation end state of a CPU. Then a working address is exchanged with an anternate address at execution of the hardware reset instruction and with the fault flag set at 1. Thus the system down is automatically recovered despite a fault occurred in an input/output device or at an interface part between the input/output device and a channel.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数のチャネルを持つ中央処理装置及び入出力
装置の制御に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to control of a central processing unit and input/output device having a plurality of channels.

〔従来の技術〕[Conventional technology]

従来、マシンチエツク割込みが発生すると、チャネルの
入出力命令実行状態を調べ、チャネルの入出力命令実行
中ならば、該当チャネルを切離し、チャネル状態語に異
常を示すビットをセソ１−するとともにコンデイション
コードをセットして該当チャネルの入出力命令を終了し
、マシンチエツク割込みを回避する方式になっている。Conventionally, when a machine check interrupt occurs, the input/output instruction execution status of the channel is checked, and if the channel is executing an input/output instruction, the corresponding channel is disconnected, a bit indicating an error is set to 1 in the channel status word, and the condition is set. This method sets a code to terminate the input/output command for the corresponding channel and avoids machine check interrupts.

これに関連するものとして、特公昭６４−８３７９号公
報等があげられる。Related to this is Japanese Patent Publication No. 8379/1983.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記公知例は、中央処理装置のマシンチエツク割込みに
ついての回避例であり、入出力装置及び、入出力装置と
チャネルとのインタフェース上の障害については考慮さ
れていない。The above-mentioned known example is an example of avoiding a machine check interrupt of a central processing unit, and does not take into account failures in input/output devices or interfaces between input/output devices and channels.

本発明は、入出力装置及び入出力装置とチャネルとのイ
ンタフェース部の障害が発生した時にも、情報処理を継
続できるようにすることを目的とする。An object of the present invention is to enable information processing to continue even when a failure occurs in an input/output device or an interface between the input/output device and a channel.

〔発明が解決するための手段〕[Means for the invention to solve the problem]

上記目的を達成するために、中央処理装置に、入出力装
置の現用、交替アドレスのテーブル及びそれぞれの入出
力装置に対応する障害フラグを設けたものである。In order to achieve the above object, the central processing unit is provided with a table of current and alternate addresses of input/output devices and a failure flag corresponding to each input/output device.

〔作用〕[Effect]

障害フラグは、入出力装置からの報告及び入出力装置と
チャネルとのインタフェース部分での障害により、１に
セントされ、ハードウェアリセット命令によりＯにリセ
ットされる。The fault flag is set to 1 in response to a report from the input/output device or a fault at the interface between the input/output device and the channel, and is reset to O by a hardware reset command.

また、アドレスのテーブルは、現用アドレスと交替アド
レスが、中央処理装置の準備完了状態の時にセットされ
、ハードウェアリセット命令実行時に障害フラグが１の
時、現用アドレスと交換アドレスが交換される。Further, in the address table, the current address and the replacement address are set when the central processing unit is ready, and when the failure flag is 1 when the hardware reset instruction is executed, the current address and the replacement address are exchanged.

〔実施例〕〔Example〕

以下、本発明の一実施例を第１図により説明する。中央
処理装置の記録装置に入出力装置の現用アドレスと予備
の入出力装置を示す交替アドレスとをテーブルとして記
憶しておく。また、現用、交替アドレスに障害フラグも
同時に設定しておく。An embodiment of the present invention will be described below with reference to FIG. The working address of the input/output device and the alternate address indicating the backup input/output device are stored as a table in the recording device of the central processing unit. Also, set failure flags for the current and alternate addresses at the same time.

システム動作中に、入出力装置あるいは入出力装置とチ
ャネルとのインタフェース部分に障害が発生した場合、
チャネルが障害フラグを１にセットし、対応する入出力
命令に対するチャネル状態語に異常を示すビットをセッ
トする。上位ソフトウェアは、チャネル状態語の異常を
示すビットを判定し、ハードウェアリセット命令を発行
する。このハードウェアリセット命令により、障害フラ
グが１の対応するアドレステーブルの現用アドレスと交
替アドレスを交換し、障害フラグを０にリセットする。If a failure occurs in the input/output device or the interface between the input/output device and the channel during system operation,
The channel sets a failure flag to 1 and sets a bit indicating an abnormality in the channel status word for the corresponding input/output instruction. The higher-level software determines the bit indicating an abnormality in the channel status word and issues a hardware reset instruction. This hardware reset instruction exchanges the current address and alternate address in the address table corresponding to the failure flag of 1, and resets the failure flag to 0.

本実施例によれば、入出力装置あるいは入出力装置とチ
ャネルとのインタフェース部分に障害が発生した場合に
上位ソフトウェアのハードウェアリセット命令により、
障害装置と予備の入出力装置との交換を行なうことがで
き、システムダウンの回復を自動的にできる。According to this embodiment, when a failure occurs in the input/output device or the interface between the input/output device and the channel, the hardware reset instruction of the higher-level software causes the
Failed devices can be replaced with spare input/output devices, and system down recovery can be automatically performed.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、入出力装置あるいは入出力装置とチャ
ネルとのインタフェース部分に障害が発生した場合に、
上位ソフトウェアのハードウェアリセット命令により、
予備の入出力装置と現用の入出力装置とのアドレスを中
央処理装置の記憶装置上で交換し、システムダウンの回
復を自動的に行なうことができる。According to the present invention, when a failure occurs in the input/output device or the interface between the input/output device and the channel,
Due to the hardware reset instruction of the upper software,
By exchanging the addresses of the spare input/output device and the current input/output device on the storage device of the central processing unit, it is possible to automatically recover from a system down.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の中央処理装置回路図である
。 １・・・命令語レジスタ ２・・・記憶装置 ３・・現用入出力アドレステーブル ４・・・交替入出力アドレステーブル ５・・・選択回路 ６・・・選択信号制御回路 ７・・・フラグレジスタ ８−１〜８−ｎ・・・入出力制御部 α・・・オペランドアドレスデータ ｂ・・・現用入出力アドレスデータ Ｃ・・・交替入出力アドレスデータ ｄ・・・入出力アドレスバス ｅ・・・ハードウェアリセット信号 ｆ・・・フラグセット信号FIG. 1 is a circuit diagram of a central processing unit according to an embodiment of the present invention. 1... Instruction word register 2... Storage device 3... Current input/output address table 4... Alternate input/output address table 5... Selection circuit 6... Selection signal control circuit 7... Flag register 8-1 to 8-n... Input/output control unit α... Operand address data b... Current input/output address data C... Alternate input/output address data d... Input/output address bus e...・Hardware reset signal f...flag set signal

Claims (1)

【特許請求の範囲】[Claims] １、複数のチャネルを持つ情報処理装置において、チャ
ネルの制御下にある入出力装置の現用アドレス，交替ア
ドレス及びそれぞれの入出力装置毎に障害が発生すると
１にセットされる障害フラグを記憶する記憶手段を設け
、入出力装置及び入出力装置とチャネルとのインタフェ
ース部分に障害が発生すると、障害フラグを１にセット
し、その後のソフトウェアのハードウェアリセット命令
により、障害フラグが１の場合のみ、現用アドレスと交
替アドレスとを交換することにより、障害時のシステム
ダウンを回避することを特徴とする中央処理装置の障害
処理方式。1. In an information processing device having multiple channels, a memory that stores the working addresses and alternate addresses of input/output devices under the control of the channels, and a failure flag that is set to 1 when a failure occurs for each input/output device. If a failure occurs in the input/output device or the interface between the input/output device and the channel, the failure flag is set to 1, and a subsequent software hardware reset instruction causes the current use to be reset only when the failure flag is 1. A fault handling method for a central processing unit, characterized in that a system failure in the event of a fault is avoided by exchanging an address with a replacement address.
JP2073302A 1990-03-26 1990-03-26 Cpu fault processing system Pending JPH03276245A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2073302A JPH03276245A (en) 1990-03-26 1990-03-26 Cpu fault processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2073302A JPH03276245A (en) 1990-03-26 1990-03-26 Cpu fault processing system

Publications (1)

Publication Number Publication Date
JPH03276245A true JPH03276245A (en) 1991-12-06

Family

ID=13514232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2073302A Pending JPH03276245A (en) 1990-03-26 1990-03-26 Cpu fault processing system

Country Status (1)

Country Link
JP (1) JPH03276245A (en)

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