JPH04180130A - Protection circuit for interruption vector table - Google Patents

Abstract

PURPOSE:To facilitate the analysis of a fault by permitting the write to an interruption vector table when a flip-flop is reset and inhibiting the write to the table when the flip-flop is set respectively. CONSTITUTION:In an initialization state of an interruption vector table 2, an FF 3 is reset and the write is permitted to the table 2. In this case, no interruption is produced to a CPU 1 from a protection circuit 4 even though the write is carried out to the table 2 for a setting operation. Then the FF 3 is set so that the write is inhibited to the table 2 when the data are set to the table 2. If the write is carried out to the table 2 thereafter, the circuit 4 suppresses the write to the table 2 and orders the CPU 1 to produce an interruption. Then the CPU 1 recognizes a fact that an abnormal write instruction is carried out to the table 2 and then processes the abnormality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt vector table protection circuit, and more particularly to an interrupt vector table protection circuit for an information processing device that stores processing for each interrupt vector in a memory as an interrupt vector table.

[Conventional technology]

Conventionally, there was no way to detect when an abnormal write was performed to the interrupt vector table due to a fault, and furthermore, if an interrupt occurred using a vector table that was rewritten due to an abnormal write, a program runaway would occur, making it difficult to analyze the fault. I was making it difficult.

[Problem to be solved by the invention]

With the conventional technology described above, the cause of the failure cannot be detected.
Another drawback is that failure analysis is difficult.

[Means to solve the problem]

The interrupt vector table protection circuit of the present invention allows writing to the interrupt vector table when the flip-flop is reset, and inhibits writing even if writing to the interrupt vector table is performed when the flip-flop is set. It has a protection circuit that reports abnormalities.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a central processing unit; 2 is an interrupt vector table in which addresses of processes corresponding to each separate vector referenced by the central processing unit 1 are stored; read from the central processing unit 1;
Can write.

3 is a flip-flop, and 4 is a flip-flop that inhibits writing even if the central processing unit 1 writes to the interrupt vector table 2 when the flip-flop is set;
When the flip-flop 3 is reset, the protection circuit 4 allows writing from the central processing unit 1 to the interrupt vector table 2;
Gase.

If a write is performed to the interrupt vector table 2 while the data is being written, an interrupt is generated to the central processing unit 1 and an abnormality report is made.

Next, the operation of one embodiment of the present invention will be explained in detail.

In the initial settings for interrupt vector table 2, flip-flop 3 is reset and interrupt vector table 2 is initialized.
Allow writing to.

At this time, even if writing is performed to the interrupt vector table 2 for setting, no interrupt is generated from the protection circuit 4 in the central processing unit 1.

When data setting for the interrupt vector table 2 is completed, a free-tub flop 3 is set to inhibit and monitor writing to the interrupt vector table 2.

After setting the flip-flop 3, when a write to the interrupt vector table 2 occurs, the protection circuit 4 inhibits the write to the interrupt vector table 2, and causes the central processing unit 1 to generate an interrupt.

The central processing unit 1 detecting the interrupt from the protection circuit 4 recognizes that an abnormal write command to the interrupt vector table 2 has been executed, and moves to abnormal processing.

At this time, since writing to the interrupt vector table 2 is inhibited, the stored values do not change, so that the interrupt processing corresponding to the interrupt from the protection circuit 4 can be normally performed.

〔Effect of the invention〕

As described above, the present invention has the effect of suppressing writing to the interrupt vector table, detecting writing to the interrupt vector table due to a failure, and facilitating failure analysis.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Central processing unit, 2... Interrupt vector table, 3... Flip-flop, 4... Protection circuit.

Claims (1)

[Claims] An information processing device using vectored interrupts includes a central processing unit, an interrupt vector table storing interrupt processing addresses corresponding to each interrupt vector referenced by the central processing unit, a flip-flop, and the flip-flop. is set, inhibits writing even if the central processing unit writes to the interrupt vector table, and when the flip-flop is reset, prevents the central processing unit from writing to the interrupt vector table. and a protection circuit that enables the interruption, and when the flip-flop is set, the protection circuit reports to the central processing unit when a write instruction to the interrupt vector table is executed. Interrupt vector table protection circuit.