JPS61232640A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61232640A
JPS61232640A JP60074737A JP7473785A JPS61232640A JP S61232640 A JPS61232640 A JP S61232640A JP 60074737 A JP60074737 A JP 60074737A JP 7473785 A JP7473785 A JP 7473785A JP S61232640 A JPS61232640 A JP S61232640A
Authority
JP
Japan
Prior art keywords
package
substrate
sealing
chip
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60074737A
Other languages
Japanese (ja)
Inventor
Keigo Nakatani
圭吾 中谷
Susumu Endo
進 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60074737A priority Critical patent/JPS61232640A/en
Publication of JPS61232640A publication Critical patent/JPS61232640A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To increase the adhesive strength of a semiconductor chip while also improving heat-dissipating properties during the operation of a semiconductor element, and to enhance the reliability of a frit sealing package by previously heating and treating a package substrate at a sealing temperature or higher prior to die bonding treatment to the package substrate of the chip. CONSTITUTION:Since a clearance is formed sufficiently between a chip 4 and an Au plating layer 3 at the step of formation of an adhesive layer 5, an adsorption gas generated from the Au plating layer 3 completely scatters until an Au.Si pellet melts, and voids are hardly made to be contained in the adhesive layer. Since the sealing temperature of a frit sealing package is higher than the temperature of die bonding as 400-430 deg.C, on the other hand, the Au plating layer 3 is degassed, and a gas intrudes into the adhesive layer 5 because the adhesive layer 5 consisting of an eutectic of Au.Si is brought to a melted state at that time, and the gas is changed into a void by the completion of package treatment. Accordingly, a substrate is heated at the sealing temperature or higher of the frit sealing package before die bonding treatment to the substrate 1, thus degassing the substrate, then removing degassing during sealing treatment.

Description

【発明の詳細な説明】 〔概要〕 フリットシールパッケージの封止処理は４００〜４３０
℃と比較的高温で行われ、この処理温度は半導体チップ
をパッケージ基板にグイボンディングする処理温度より
も高く、そのためにパッケージ基板からのガス出しの問
題がある。[Detailed Description of the Invention] [Summary] The sealing process of the frit seal package is 400 to 430
This process is carried out at a relatively high temperature of .degree. C., which is higher than the temperature at which semiconductor chips are bonded to the package substrate, and therefore there is a problem of outgassing from the package substrate.

本発明はこの問題を解決する封止方法に関するものであ
る。The present invention relates to a sealing method that solves this problem.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体デツプの接着強度と放熱性とを向上した
フリットシールパッケージの封止方法に関する。The present invention relates to a method for sealing a frit seal package that improves the adhesive strength and heat dissipation of a semiconductor dip.

ＩＣ，ＬＳＩなどの半導体素子のパッケージ形態として
はメタルシールパッケージ、セラミックシールパッケー
ジ（通称サーデツプパッケージ）。Package forms for semiconductor devices such as ICs and LSIs include metal seal packages and ceramic seal packages (commonly known as surdeep packages).

フリットシールパッケージなどがある。There are also frit seal packages.

ここでメタルシールパッケージの封止は予め金属化処理
が施されているパッケージ基板の接合部と金属製の蓋部
とを共晶半田などの低融点金属からなる枠体を用いて封
止する方法である。Here, the metal seal package is sealed by using a frame made of a low melting point metal such as eutectic solder to seal the joint of the package substrate, which has been previously metallized, and the metal lid. It is.

またサーデツプパッケージはセラミックからなるパッケ
ージ基板と蓋部に低融点ガラスを部分的に被覆処理して
おり、パッケージ基板と蓋部とを位置決めして加熱する
ことにより相互に融着させる方法である。In addition, in a sur-deep package, the ceramic package substrate and lid are partially coated with low-melting glass, and the package substrate and lid are positioned and heated to fuse them together. .

一方、フリットシールパッケージは予めセラミック製の
蓋部に低融点ガラスが部分的に被覆処理されており、こ
れをセラミックからなるパッケージ基板に位置決めし、
荷重を加えて加熱することにより相互に融着させる方法
である。On the other hand, in a frit seal package, the ceramic lid is partially coated with low-melting glass, and this is positioned on the ceramic package substrate.
This is a method of welding them together by applying a load and heating them.

これらのパッケージ形態を比較するとそれぞれ特徴があ
るが材料がメタルシールパッケージより安く、サーディ
ソプパソケージより封止の気密性が高いことからフリッ
トシールパッケージが使用されている。Comparing these package types, each type has its own characteristics, but the frit seal package is used because the material is cheaper than the metal seal package and the sealing is more airtight than the Sardi soap package.

〔従来の技術〕[Conventional technology]

図はフリットシールパッケージ法を説明するパッケージ
の断面図で、アルミナなどからなるパッケージ基板（以
下略して基板）１の中央に設けられている凹部はタング
ステン（Ｗ＞がメタライズされており、この上にニッケ
ル（Ｎ＋）からなるメッキ層２と金（Ａ　ｕ　）からな
るメッキ層３とが形成されており、この位置に金シリコ
ン（Ａｕ−３ｉ）共晶合金からなるベレットを介して半
導体チップ（以下略してチップ）４を置き、加熱すると
篩・Ｓｉベレットが溶融すると共にチップ４との界面で
Ａｕ・Ｓｔの共晶からなる接着層５を生じてダイボンデ
ィングが行われている。The figure is a cross-sectional view of a package to explain the frit seal packaging method.The recess provided in the center of the package substrate (hereinafter referred to as the substrate) 1 made of alumina etc. is metalized with tungsten (W>). A plating layer 2 made of nickel (N+) and a plating layer 3 made of gold (A u ) are formed, and a semiconductor chip (hereinafter referred to as "semiconductor chip") is formed at this position via a pellet made of a gold-silicon (Au-3i) eutectic alloy. When a chip (abbreviated as a chip) 4 is placed and heated, the sieve/Si pellet melts and an adhesive layer 5 made of eutectic Au/St is formed at the interface with the chip 4, thereby performing die bonding.

次にチップ４の周辺部に形成されているポンディングパ
ッドと基板１の凹部の周辺にパターン形成されているリ
ード部とを金（Ａｕ）線６を用いてワイヤボンディング
して回路接続が行われる。Next, bonding pads formed around the periphery of the chip 4 and lead parts patterned around the concave portion of the substrate 1 are wire-bonded using a gold (Au) wire 6 to establish a circuit connection. .

次にパッケージ蓋部（以下略して蓋部）７を基板１に位
置決めし、荷重を加えながら加熱すると蓋部７の基板と
の接触面に被覆しているシールガラス層（以下略してガ
ラス層）８が基板１と融着してハーメチックシールが行
われる。Next, the package lid part (hereinafter abbreviated as the lid part) 7 is positioned on the substrate 1 and heated while applying a load, and the sealing glass layer (hereinafter abbreviated as the glass layer) covering the contact surface of the lid part 7 with the substrate is heated. 8 is fused to the substrate 1 to form a hermetic seal.

ここでＡｕ−３ｉの共晶温度は３７０°Ｃであり、一方
基板１と蓋部７とを融着させる封止温度は４００〜４３
０℃と高く、メタルシールパッケージの封止温度が３５
０°Ｃと低いのと較べて特徴がある。Here, the eutectic temperature of Au-3i is 370°C, while the sealing temperature for fusing the substrate 1 and the lid 7 is 400-43°C.
The sealing temperature of the metal seal package is as high as 0℃, and the sealing temperature is 35℃.
It has a unique feature compared to the low temperature of 0°C.

また、フリットシールパッケージで封止処理を行ったも
のはチップ４の基板１との接着強度が低下すると共に熱
抵抗が増加する傾向があり、この対策が必要であった。Furthermore, in the case of a frit-sealed package that is sealed, the adhesive strength between the chip 4 and the substrate 1 tends to decrease and the thermal resistance tends to increase, so countermeasures have been required.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上記したようにフリットシールパッケージは比較的簡
単にハーメチックシールが行われるために広く使用され
ているが、他のパッケージ法と較べて接着強度が低下し
、また熱抵抗が増加することが問題である。As mentioned above, frit seal packages are widely used because their hermetic sealing is relatively easy, but compared to other packaging methods, they have problems such as lower adhesive strength and increased thermal resistance. be.

〔問題点を解決するための手段〕[Means for solving problems]

上記の問題は半導体チップを装着したパッケージ基板に
フリットシールガラスを部分的に被覆したパッケージ蓋
部を融着して封止を行うハーメチックシール工程におい
て、半導体チップのパッケージ基板へのダイボンディン
グ処理に先立ち、パッケージ基板を予め封止温度以上に
加熱処理しておくことを特徴とするフリットシールパッ
ケージの封止方法により解決することができる。The above problem occurs during the hermetic sealing process in which a package lid partially covered with frit seal glass is fused and sealed to a package substrate on which a semiconductor chip is attached, prior to die bonding of the semiconductor chip to the package substrate. This problem can be solved by a method for sealing a frit-seal package, which is characterized in that the package substrate is previously heat-treated to a temperature higher than the sealing temperature.

〔作用〕[Effect]

本発明はフリットシールパッケージにおいてチップの接
着強度が低下する原因を究明した結果、チップ４が基板
１と接着している接着層５にボイドが存在することが接
着強度の低い原因であり、これはＡｕメッキ層２より生
ずることを確かめた。As a result of investigating the cause of the decrease in adhesive strength of chips in frit seal packages, the present invention found that the presence of voids in the adhesive layer 5 where the chip 4 adheres to the substrate 1 is the cause of the low adhesive strength. It was confirmed that this occurs from the Au plating layer 2.

すなわちＸ線撮影とガス分析によってチップ４の接着状
態を調査すると、ボイドは基板１を約４００℃以上に加
熱することにより生じており、このガスは水素（Ｎ２）
とヘリウム（Ｈｅ）を主成分とするものであって、メッ
キ層２を形成するＡｕに多く含まれていることが判った
。In other words, when the adhesion state of the chip 4 was investigated by X-ray photography and gas analysis, it was found that the voids were caused by heating the substrate 1 to about 400°C or higher, and this gas was hydrogen (N2).
It was found that Au containing helium (He) as a main component was contained in large amounts in the Au forming the plating layer 2.

ところで、チップ４の基板ｌへの接着はＷからなるメタ
ライズ層の上に形成したＡｕメッキ層３の上に４ｕ−５
ｉ共晶合金片からなるベレットを置き、この上にチップ
４を置いて約３７０℃に加熱することにより行われてい
るが、この接着層５の形成段階においてはチップ４とＡ
ｕメッキＮ３との間には隙間が充分に存在するので、Ａ
ｕメッキ層３から発生する吸着ガスはＡｕ−３ｔペレツ
トが溶融するまでに飛散してしまい、そのため接着層に
は殆どボイドが含まれていない。By the way, in order to bond the chip 4 to the substrate l, 4u-5 is applied on the Au plating layer 3 formed on the metallized layer made of W.
This is done by placing a pellet made of a eutectic alloy piece, placing the chip 4 on top of it, and heating it to about 370°C.
There is a sufficient gap between u plating N3, so A
The adsorbed gas generated from the U plating layer 3 is scattered before the Au-3t pellet melts, and therefore the adhesive layer contains almost no voids.

一方、フリットシールパッケージの封止温度は４００〜
４３０℃とグイポンディグ温度よりも高いためにＡｕメ
ッキ層３よりガス出しがあり、またこの際にＡｕ−３ｉ
の共晶からなる接着層５は溶融状態であるためにガスが
接着層５の中に入り、パッケージ処理の終了によってボ
イドとなる。On the other hand, the sealing temperature of the frit seal package is 400~
Since the temperature is 430°C, which is higher than the Guipondig temperature, gas is released from the Au plating layer 3, and at this time, the Au-3i
Since the adhesive layer 5 made of eutectic material is in a molten state, gas enters the adhesive layer 5 and becomes a void upon completion of the packaging process.

そこで本発明は基板１へのダイポンディグ処理前に基板
をフリットシールパッケージの封止温度以上に加熱する
ことによりガス出しを行い、これにより封止処理中のガ
ス出しを無くするものである。Therefore, in the present invention, gas is released by heating the substrate 1 to a temperature higher than the sealing temperature of the frit seal package before the die-ponging process to the substrate 1, thereby eliminating gas release during the sealing process.

〔実施例〕〔Example〕

表は基板に本発明を適用し、窒素（Ｎ２）中に微量の水
素（Ｈ２）を加えた雰囲気中で４５０°Ｃ１６０分の熱
処理を施した場合の効果を示すものである。The table shows the effect when the present invention is applied to a substrate and heat treatment is performed at 450° C. for 160 minutes in an atmosphere containing a trace amount of hydrogen (H2) in nitrogen (N2).

ここでボイドの面積はチップの接着面積に対する占有率
をＸ線写真より求めたもので、ボイドは何れも多数の粒
状ボイドよりなっている。Here, the area of the void is determined from an X-ray photograph as the occupancy of the bonded area of the chip, and each void is composed of a large number of granular voids.

このように本発明を適用するとデツプの接着強度が改良
される以外に接着層５の熱抵抗が低下して放熱性が改良
される。When the present invention is applied in this way, not only the adhesive strength of the depth is improved, but also the thermal resistance of the adhesive layer 5 is reduced, and the heat dissipation performance is improved.

〔発明の効果〕〔Effect of the invention〕

以上記したように本発明の実施により接合層にボイドが
無くなり、それによってチップの接着強度が増大すると
共に半導体素子が動作中の放熱性も改善することができ
、フリットシールパッケージの信頼性を向上することが
可能となる。As described above, implementation of the present invention eliminates voids in the bonding layer, thereby increasing the bonding strength of the chip and improving heat dissipation while the semiconductor element is in operation, improving the reliability of the frit seal package. It becomes possible to do so.

【図面の簡単な説明】[Brief explanation of drawings]

図はフリットシールパッケージの断面構成図で同図（Ａ
）は蓋部、同図（Ｂ）は基板である。 図において １は基板、　　　　　　　２ば寸、メッキ層、３は△Ｕ
メッキ層、　　　　４はチップ、５は接着層、　　　　
　　７は蓋部、 ８はガラス層、 である。 狂 ＣＢ） ノ］へンＦシールバソケコ〉゛。 手続補正書く旅）The figure is a cross-sectional diagram of the frit seal package.
) is the lid, and (B) is the substrate. In the figure, 1 is the board, 2 is the plating layer, and 3 is △U
Plating layer, 4 is chip, 5 is adhesive layer,
7 is a lid portion; 8 is a glass layer; Mad CB) ノ]hen F seal basokeko〉゛. Procedural amendment writing journey)

Claims (1)

【特許請求の範囲】[Claims] 半導体チップ（３）を装着したパッケージ基板（１）に
フリットシールガラスを部分的に被覆したパッケージ蓋
部（６）を融着して封止を行うハーメチックシール工程
において、半導体チップ（３）の前記パッケージ基板（
１）へのダイボンディング処理に先立ち、パッケージ基
板（１）を予め封止温度以上に加熱処理しておくことを
特徴とする半導体装置の製造方法。In a hermetic sealing process in which the package substrate (1) on which the semiconductor chip (3) is attached is fused and sealed with a package lid (6) partially covered with frit seal glass, the semiconductor chip (3) is sealed. Package board (
1) A method for manufacturing a semiconductor device, characterized in that, prior to the die bonding process, the package substrate (1) is previously heat-treated to a temperature higher than the sealing temperature.
JP60074737A 1985-04-09 1985-04-09 Manufacture of semiconductor device Pending JPS61232640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60074737A JPS61232640A (en) 1985-04-09 1985-04-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60074737A JPS61232640A (en) 1985-04-09 1985-04-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61232640A true JPS61232640A (en) 1986-10-16

Family

ID=13555846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60074737A Pending JPS61232640A (en) 1985-04-09 1985-04-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61232640A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10289962A (en) * 1997-02-17 1998-10-27 Denso Corp Manufacture of electronic circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10289962A (en) * 1997-02-17 1998-10-27 Denso Corp Manufacture of electronic circuit device

Similar Documents

Publication Publication Date Title
US4784974A (en) Method of making a hermetically sealed semiconductor casing
US4656499A (en) Hermetically sealed semiconductor casing
TW201737362A (en) Transient liquid phase material bonding and sealing structures and methods of forming same
JP2001176999A (en) Method of sealing electronic component
EP0090566B1 (en) Semiconductor device package
EP0361283A2 (en) Resin-sealed type semiconductor device and method for manufacturing the same
EP0098176A2 (en) The packaging of semiconductor chips
US3585711A (en) Gold-silicon bonding process
JPH01278959A (en) Joining method for structure
CA1201211A (en) Hermetically sealed semiconductor casing
JPS61232640A (en) Manufacture of semiconductor device
JPH07122670A (en) Fabrication of glass sealed semiconductor device
JPH0228351A (en) Semiconductor device
JPH03187247A (en) Semiconductor integrated circuit device and fabrication thereof
JPH03108361A (en) Semiconductor integrated circuit device
JP2002334943A (en) Electronic component
JPH03181153A (en) Semiconductor integrated circuit device
JPH03276665A (en) Electron device
JPS58103198A (en) Method of mounting electronic part
JPH06291239A (en) Manufacture of semiconductor device
JPS5889847A (en) Sealing type integrated circuit package
JP2002198485A (en) Semiconductor mounting body, semiconductor device using the same and manufacturing method therefor
JPS637459B2 (en)
JPH0432253A (en) Mounting structure of semiconductor integrated circuit and mounting board used therefor
JPH04348055A (en) Semiconductor device and its manufacture