JPS61230369A - Triac - Google Patents
TriacInfo
- Publication number
- JPS61230369A JPS61230369A JP7213185A JP7213185A JPS61230369A JP S61230369 A JPS61230369 A JP S61230369A JP 7213185 A JP7213185 A JP 7213185A JP 7213185 A JP7213185 A JP 7213185A JP S61230369 A JPS61230369 A JP S61230369A
- Authority
- JP
- Japan
- Prior art keywords
- opposite
- thyristor
- insulating films
- triac
- mutually
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 239000008188 pellet Substances 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はトライブックの転流時臨界オフ電圧上昇率を改
良したトライブックに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a try book that improves the critical off-voltage rise rate during commutation of the try book.
第4図は従来のトライブックの一例を示す断面図である
。N型シリコン基板を使用して、通常の拡散技術により
容易に製作出来るものである。基T1電極9及びT、電
極7に接続する部分はP型エミッタ層として働く。FIG. 4 is a sectional view showing an example of a conventional trybook. It can be easily manufactured using a normal diffusion technique using an N-type silicon substrate. The portion connected to the base T1 electrode 9 and T, electrode 7 functions as a P-type emitter layer.
このトライブックの駆動モードには4つある。There are four drive modes for this trybook.
すなわちT1電極9に○、T雪電極電極7を印加し、ゲ
ート電極8に■又はeを印加し逆阻止サイリスタと同じ
方向に導通させ為2つのモードと、TI電極9に■、T
3電極7にeを印加し前記と逆の方向に導通させる2つ
のモードである。That is, ○, T snow electrode electrode 7 is applied to the T1 electrode 9, and ■ or e is applied to the gate electrode 8 to conduct in the same direction as the reverse blocking thyristor.
These are two modes in which e is applied to the three electrodes 7 and conduction occurs in the opposite direction to the above.
さてトライブックを導通、非導通の状態に制御する方法
としては、導通している方向と逆方向にバイアスをかけ
、導通時の電流を保持電流以下にして強制的にオフさせ
る方法である。Now, as a method of controlling the trybook to be in a conducting or non-conducting state, there is a method of applying a bias in the direction opposite to the direction in which it is conducting, and forcing the current at the time of conducting to be lower than the holding current to force it to turn off.
さて、従来の逆バイアスを印加する方法は、近年の機器
の高速化に対して、逆バイアスの立ち上がり時間を短か
くして対応を計るという方向で対処して来た。しかしト
ライアックの機能が追いつかず、逆バイアスにより導通
時の方向と逆方向の方を導通させてしまう誤動作が起こ
った■この誤動作を防ぐために、臨界オフ電圧上昇率を
改良することが必要であり、従来方法としては、第4図
に示す、対向するN型エミツタ層4及び6に、互いが重
なり合わない対向部L(対向部の幅をLとする)を設け
て、導通時の電荷を非導通のサイリスタ部に影響させな
い方策を取って来た。The conventional method of applying a reverse bias has been to cope with the recent increase in speed of devices by shortening the rise time of the reverse bias. However, the function of the triac could not keep up, and a malfunction occurred in which the reverse bias caused conduction in the direction opposite to the conduction direction. ■To prevent this malfunction, it was necessary to improve the critical off-voltage rise rate. In the conventional method, opposing N-type emitter layers 4 and 6 shown in FIG. We have taken measures to avoid affecting the conduction thyristor section.
しかるに本方法では、対向部りを十分に取らなければな
らず、チップ小型化の面で問題となる。又P型エミッタ
層2及び3とT8電極7及びT、電極9の接する部分は
等電位であるから、ある程度までしか電荷の残留をおさ
えることが出来ず、この為、臨界オフ電圧上昇率の改良
に対して制限が加わるという欠1点があった。However, in this method, a sufficient opposing portion must be provided, which poses a problem in chip miniaturization. In addition, since the contact areas of the P-type emitter layers 2 and 3 and the T8 electrodes 7 and T, and the electrode 9 are at the same potential, the residual charge can only be suppressed to a certain extent, and for this reason, the rate of increase in critical off-voltage can be improved. One drawback was that it added restrictions to the
本発明の目的は、上記欠点を除去することKよシ、臨界
オフ電圧上昇率が改善され、かつチップの小型化が可能
なトライアックを提供することにある。SUMMARY OF THE INVENTION In addition to eliminating the above-mentioned drawbacks, an object of the present invention is to provide a triac in which the critical off-voltage rise rate is improved and the chip size can be reduced.
〔問題点を解決するための手段〕
本発明のトライアックは、互いに隣接する層が第2のエ
ミツタ層の互に嵐なり合わない対向部に絶縁膜を設けた
ことからなっている。[Means for Solving the Problems] The triac of the present invention includes an insulating film provided in the opposing portions of the second emitter layer in which adjacent layers do not overlap with each other.
第1図は本発明の第1の実施例を示す模式的断面図であ
る。本実施例は第4図に示す従来例に本発明を適用した
ものであり、同じ参照番号は同じ要素を表わす。本実施
例は、対向する2つのN型エミツタ層4及び6の互いに
電なり合わない対向部りに、それぞれ絶縁層10を設け
たことを特徴としている。本実施例による絶縁層10は
、各拡散層を設けた後にイオン注入法によりNt又はO
8をP型領域2及び3の所定の位置に選択的に注入し1
000℃程度の不活性ガス中にてアニールすることによ
り形成したものである。FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention. This embodiment is an application of the present invention to the conventional example shown in FIG. 4, and the same reference numerals represent the same elements. This embodiment is characterized in that an insulating layer 10 is provided on each of the opposing portions of the two opposing N-type emitter layers 4 and 6 that are not electrically connected to each other. The insulating layer 10 according to this embodiment is made of Nt or O by ion implantation after providing each diffusion layer.
8 was selectively implanted into predetermined positions of P-type regions 2 and 3.
It is formed by annealing in an inert gas at about 000°C.
第2図及び第3図は、本発明の第2及び第3の実施例を
示す平面図で、それぞれ本発明を実際に適用したトライ
アックの一例であり、第2図はサイドゲート型トライア
ック、第3図はセンターゲート型トライブックである。2 and 3 are plan views showing second and third embodiments of the present invention, each of which is an example of a triac to which the present invention is actually applied. Figure 3 shows a center gate type try book.
両図中の参照番号は第1図の場合と同じでありどのトラ
イブックにも適用出来ることがわかる。It can be seen that the reference numbers in both figures are the same as in Figure 1 and can be applied to any trybook.
本発明では、上記のように互いに対向するサイリスタ部
が、絶縁膜によって完全に分離されている為に、片方の
導通時におけるもう一つへのサイリスタ接合への影響を
最小限におさえることが出来る。そのため転流時の臨界
オフ電圧上昇率を改善することが可能となシ、高速な電
気機器へ使用出来るサイリスタが得られる。さらに対向
部りの幅りは、絶縁膜の幅の制御によシ、十分に小さく
することが可能となり、半導体ベレットそのものを小さ
く出来る効果がある。In the present invention, since the thyristor parts facing each other are completely separated by the insulating film as described above, when one conducts, the effect on the thyristor junction to the other can be minimized. . Therefore, it is possible to improve the critical off-voltage rise rate during commutation, and a thyristor that can be used in high-speed electrical equipment can be obtained. Furthermore, the width of the opposing portion can be made sufficiently small by controlling the width of the insulating film, which has the effect of making the semiconductor pellet itself smaller.
第1図は本発明の第1の実施例を示す模式的断面図、第
2図、第3図はそれぞれ本発明の第2゜第3の実施例を
示す平面図、第4図は一従来例を示す模式的断面図であ
る。
1・・・・・・Nilペース層、2,3・・・・・・P
型領域、4゜5.6・・・・・・N型エミツタ層、7・
・・・・・T、電極、8・・・・・・ゲート電極、9・
・・・・・T11ic極、10・・・・・・絶縁層、L
・・・・・・対向部(対向部幅)。
I=N型ヘーズ層 7:T2噛り干封 Aり;秀と末
飽■(第 1 回
茅3 回FIG. 1 is a schematic cross-sectional view showing the first embodiment of the present invention, FIGS. 2 and 3 are plan views showing the second and third embodiments of the present invention, respectively, and FIG. 4 is a conventional one. FIG. 3 is a schematic cross-sectional view showing an example. 1...Nil pace layer, 2,3...P
Type region, 4°5.6...N type emitter layer, 7.
...T, electrode, 8...gate electrode, 9.
...T11ic pole, 10...Insulating layer, L
...Opposing part (opposing part width). I = N-type haze layer 7: T2 Kamihanfu A; Hide and Suaku■ (1st Kaya 3rd
Claims (2)
造のトライアックにおいて、一主面側の第1のエミッタ
層と他主面側の第2のエミッタ層の互いが重なり合わな
い対向部に絶縁層を設けたことを特徴とするトライアッ
ク。(1) In a triac with a five-layer structure in which adjacent layers are of different conductivity types, the first emitter layer on one main surface side and the second emitter layer on the other main surface side are opposed to each other and do not overlap. A triac characterized by having an insulating layer.
することに形成されてなる特許請求の範囲第(1)項記
載のトライアック。(2) The triac according to claim (1), wherein the insulating layer is formed by ion implantation of N_2 or O_2 and heat treatment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7213185A JPS61230369A (en) | 1985-04-05 | 1985-04-05 | Triac |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7213185A JPS61230369A (en) | 1985-04-05 | 1985-04-05 | Triac |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61230369A true JPS61230369A (en) | 1986-10-14 |
Family
ID=13480435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7213185A Pending JPS61230369A (en) | 1985-04-05 | 1985-04-05 | Triac |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61230369A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4994885A (en) * | 1988-07-01 | 1991-02-19 | Sanken Electric Co., Ltd. | Bidirectional triode thyristor |
EP1324394A1 (en) * | 2001-12-28 | 2003-07-02 | STMicroelectronics S.A. | Static bidirectional switch sensitive in the quadrants Q4 and Q1 |
WO2017046944A1 (en) * | 2015-09-18 | 2017-03-23 | 新電元工業株式会社 | Semiconductor device and semiconductor device manufacturing method |
-
1985
- 1985-04-05 JP JP7213185A patent/JPS61230369A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4994885A (en) * | 1988-07-01 | 1991-02-19 | Sanken Electric Co., Ltd. | Bidirectional triode thyristor |
EP1324394A1 (en) * | 2001-12-28 | 2003-07-02 | STMicroelectronics S.A. | Static bidirectional switch sensitive in the quadrants Q4 and Q1 |
FR2834385A1 (en) * | 2001-12-28 | 2003-07-04 | St Microelectronics Sa | SENSITIVE BIDIRECTIONAL STATIC SWITCH IN Q4 AND Q1 QUADRANTS |
WO2017046944A1 (en) * | 2015-09-18 | 2017-03-23 | 新電元工業株式会社 | Semiconductor device and semiconductor device manufacturing method |
CN106716643A (en) * | 2015-09-18 | 2017-05-24 | 新电元工业株式会社 | Semiconductor device and semiconductor device manufacturing method |
JP6157043B1 (en) * | 2015-09-18 | 2017-07-05 | 新電元工業株式会社 | Semiconductor device and manufacturing method of semiconductor device |
TWI594424B (en) * | 2015-09-18 | 2017-08-01 | 新電元工業股份有限公司 | Semiconductor device and method of manufacturing the semiconductor device |
US10326010B2 (en) | 2015-09-18 | 2019-06-18 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing the semiconductor device |
CN106716643B (en) * | 2015-09-18 | 2020-12-22 | 新电元工业株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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