JPH045274B2 - - Google Patents

Description

[Detailed Description of the Invention] (Background of the Invention) This invention relates to a thyristor, and more specifically, to a thyristor.
This invention relates to a thyristor that can be turned off and turned off.

A thyristor is a well-known semiconductor device typically used as a current switch to allow current to flow through a circuit and to interrupt this current. A thyristor "turns off" when it creates a high conductance path between its two terminals (ie, anode and cathode), and "turns off" when it creates a high resistance path between those two terminals. A typical conventional thyristor 10 is shown in FIG. The thyristor 10 has four regions 12, 14, 16, 18 of alternating conductivity type, an anode 20 and a cathode 22, and a metal-oxide-semiconductor (MOS) turn-off structure 24, or more broadly, a conductor. an insulator-semiconductor turn-off structure 24 .

The MOS turn-off structure 24 has a gate 26 and
and an insulating layer 28 separating the gate 26 from the semiconductor body of the thyristor 10. When gate 26 is biased with a positive voltage above the threshold (relative to cathode 22), the portion of P-type region 16 adjacent to insulating layer 28 "inverts" creating an inversion channel 30;
This allows electrons to pass through. For this reason, cathode 2
Electrons from N-type region 18 can flow through electron current path 32 from N-type region 18 to N-type region 14 via inversion channel 30 .

As is well known, the thyristor 10 has an N-type region 1
4, an NPN transistor structure formed by a P-type region 16 and an N-type region 18, and a P-type region 12;
It can be modeled as two transistor structures, a PNP transistor structure formed by an N-type region 14 and a P-type region 16. These transistor structures are recombined with each other. That is, the collector (region 14) of the NPN transistor structure is coupled to the base (region 14) of the PNP transistor structure, so that this base can be driven. The collector of the PNP transistor structure (region 16) is coupled to the base of the NPN transistor structure (region 16), so that this base can be driven. Therefore, supplying electrons to the N-type region 14 (the base of the PNP transistor structure) regeneratively turns on both the NPN and PNP transistor structures, thus turning on the thyristor 10.

It is desirable to provide a semiconductor device that can operate as a thyristor, has a MOS turn-on structure on its upper surface, and has a turn-off structure on its lower surface. Although such devices have turn-off capability, each side of the device has two electrodes, viz.
It is easy to manufacture because it has only two electrodes, a gate and an anode or cathode for the MOS turn-on or turn-off structure.

(Object of the invention) Therefore, the object of this invention is to
It is an object of the present invention to provide a semiconductor device having a MOS turn-on structure and a MOS turn-off structure on the other side.

Another object of the invention is to provide a semiconductor device that can act as either a thyristor or a field effect transistor (FET), thereby providing important advantages as described below.

SUMMARY OF THE INVENTION In realizing the objects of the invention, there is provided a semiconductor device having a body of semiconductor material, first and second electrodes, and first and second plurality of cells.

A semiconductor body or wafer includes a first and a second semiconductor body or wafer.
a first having a major surface of and joined together in sequence;
a second, a third and a fourth region;
is of one conductivity type, the second and fourth regions are of opposite conductivity type, and the wafer further includes a fifth region of opposite conductivity type disposed within the first region and spaced from the second region. including the area of The second region extends to both the first and second major surfaces, the first and fifth regions extend to the first major surface, and the third and fourth regions extend to the second major surface. It extends to the surface. the first electrode is the first
and a fifth region, and a second electrode is electrically connected to the fourth region.

Each of the first plurality of cells is comprised of a conductor-insulator-semiconductor type means for transporting majority carriers between the second region and the first electrode. Each of the second plurality of cells is comprised of conductor-insulator-semiconductor type means for transporting majority carriers between the fourth region and the second region.

In certain embodiments of the invention, the cell repeat distance of the first and second plurality of cells is less than about the minimum thickness of the second region of the semiconductor body.

Although the novel features of this invention are specifically described in the claims, the structure, operation, and other objects and advantages of this invention will be better understood from the following description of the drawings. Good morning.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION FIG. 2 schematically shows a semiconductor device 40 embodying the invention. Device 40 turns on cell 4
Contains 2,44. It is appropriate to do these in the same way. Additionally, device 40 includes turn-off cells 46, 48, which are also suitably similar. Therefore, only the left-hand cells 42, 46 will be described in detail below.

A first region 50, a second region 52, a third region 54, and a fourth region to which semiconductor devices 40 are connected one after another.
area 56. The first region 50 is separated from the third and fourth regions 54, 56 by a second region 52, and the fourth region 56 is separated from the third region 5.
4 from the first and second regions 50,52. Additionally, the device 40 may include another first region, such as the first region 53 of the turn-off cell 48 , another third region, such as the third region 55 of the turn-on cell 44 , and a third region of the turn-on cell 44 . 4 includes another fourth region, such as region 57 of 4. 50 and 5
It is possible to interconnect the first regions as shown at 3 and similarly it is possible to interconnect the third regions such as 54 and 55.

N-type second region 52, P-type third region 54
and an N-type fourth region 56 form an NPN transistor structure. P-type first region 5
A PNP transistor structure is formed by the second region 52 of 0, N type and the third region 54 of P type.

Typical doping concentrations (ie, number of dopant atoms per cubic centimeter) for various regions of semiconductor device 40 are of the following order:

First region 50 (P ₁ + portion): 10 ¹⁸ or more Second region 52: 10 ¹⁶ or less Third region 54: 10 ¹⁷ or less Fourth region 56: 10 ¹⁵ or more Therefore, for example, the third region 54 is
It can be said that the doping concentration is substantially higher than that of No.2. "Substantially higher" or "substantially lower" refers to at least an order of magnitude higher or lower.

A cathode 58, suitably in the form of a comb-tooth on the top surface of the device 40, abuts the fourth region 56. The anode 60 is suitably comb-shaped on the underside of the device 40 and is located in the first region 5.
It is close to 0.

Turn-on cell 42 includes a gate 60 and an insulating layer 61 separating gate 60 from the semiconductor body of device 40 . The gate 60 has a junction 63 (between the second and third regions 52, 54) connected to the insulating layer 6.
From near position 62 terminating near 1, (3rd
and the fourth region 54 , 56 ) to a point 64 where the junction 65 terminates near the insulating layer 61 .
It overlaps above the third region 54. Similar to the operation of the conventional turn-on structure 24 shown in FIG. region 54 is inverted to create an inversion channel 66, which allows electrons to pass through. The inversion channel 66 thus creates an electron current path 67 between the fourth region 56 and the second region 52. Therefore, electrons from the cathode 58 enter the path 6
7 to the second region 52 of N type, which constitutes the base of the PNP transistor structure, and can regeneratively turn on both the PNP and NPN transistor structures, thus turning on the device 40.

Gate 60, insulating layer 61, and third region 54
The portion of the inversion channel 66 that includes the inversion channel 66 constitutes what one skilled in the art would consider to be a MOS-type means for transporting majority carriers between the fourth region 56 and the second region 52. This means is normally off.

The turn-on cell 42 can be made in various shapes when viewed from above, such as elongated, square or rounded.

The turn-off cell 46 includes a gate 68, an insulating layer 70, and an N-type fifth transistor disposed within the first region 50.
It is composed of a region 72. Region 72 is in contact with first region 50 and anode 60 . A gate 68 is separated from the semiconductor body of device 40 by an insulating layer 70. The gate 68 extends from the location 73 (between the first and second regions 50, 52) where the junction 74 (between the first and second regions 50, 52) terminates near the insulating layer 70;
and the fifth region 72 ) between the insulating layer 7 and the fifth region 72 ).
It overlaps the first region 50 up to a position 75 terminating near zero.

Biasing gate 68 (with respect to cathode 58) with a positive voltage above the threshold inverts the portion of first region 50 immediately adjacent to insulating layer 70;
An inverted channel 78 is created, which allows electrons to pass through. Electrons from the second region 52 thus pass along the distributed electron current path 80 through the inversion channel 78 and the fifth region 72 to the anode 6.
It can flow to 0.

For turn-off cell 46 to function properly, the electrical resistance of electron current path 80 must be
The forward bias of junction 63 due to electron flow at zero must be less than a value that limits it to approximately half the energy bandgap voltage of the semiconductor material forming junction 63. This removes base drive from the PNP transistor structure, thereby turning off the NPN transistor structure, thereby allowing device 40 to be turned off. Generally, the lower the resistance of current path 80, the lower the resistance of turn-off cell 46.
The current that can turn off becomes larger. For this reason,
The appropriate value for the resistance of current path 80 is related, in part, to how much current the turn-off cell 46 needs to turn off.

The resistance of electron current path 80 is related in part to the resistance of inversion channel 78. channel 7
The resistance value of 8 can be reduced by doping the P ₂ portion of the first region 50 containing the inversion channel to a concentration of less than about 10 ¹⁷ dopant atoms per cubic centimeter. Furthermore, the following design points contribute to the purpose of reducing the resistance of current path 80.

(1) As seen in FIG. 2, by shortening the horizontal dimension of the first region 50, the total length of the current path 80 can be shortened.

(2) As seen in FIG. 2, the overall length of current path 80 can also be shortened by reducing the horizontal dimension of inversion channel 78.

(3) By reducing the size of the cell 46 by reducing the size 82 and by making the shape of the cell 46 not elongated but round or square when viewed from below in FIG. , the resistance of the inversion channel 78 can be reduced by increasing the dimension of the channel 78, as viewed normal to FIG. 2, compared to the area of the cell 46.

(4) By doping the first region 50 and the fifth region 72 with a high concentration, the resistance value of these regions can be reduced. However, area 50
The doping concentration of should not be too large so that the forward drop of device 40 is not excessive.

From the above description, those skilled in the art will be able to realize a semiconductor device having an electron current path 80 with an appropriate resistance so that the turn-off cell 46 can function properly.

Those skilled in the art will appreciate that the gate 98, the insulating layer 70, and the portion of the first region 50 that includes the inversion channel 78 are connected between the second region 52 and the anode 60 via the fifth region 72. ) It will be understood that it constitutes a MOS type structure that transports electrons. This structure is normally off.

Turn-off cell 46 and turn-on cell 4
If the cell repeat distances (or cell widths) 82, 84 of 2 are approximately equal to or less than the minimum thickness 86 of the N-type region 52, the semiconductor device 40 can operate in two modes: as a thyristor and as a FET. can have. Accordingly, the electron current path of device 40 between cathode 58 and anode 60 through the inverted channels 66, 78 and N-type second region 52 (not shown in the figure but hereinafter referred to as the FET current path) is , has a conductivity of sufficient magnitude to allow a significant electron current to flow between the cathode 58 and the anode 60. Further, the turn-on cell 42 is aligned with the turn-off cell 46 to the second region 52, as shown, such that the FET in the second region 52 is aligned between the inversion channels 66, 78.
It is desirable to maximize the conductivity of the current path.
Furthermore, the cell repeat distance 84 of the cells 42 is about 10 to
Preferably, gate 60 overlies insulating layer 61 and insulating layer 61 contacts second region 52, as shown in region 88 between locations 62 and 90, over a distance of 50%. The most preferable value for the above distance is 20%. This minimizes the spreading resistance value in the second region 52 of the FET current path. It is not necessary that the aforementioned distance between locations 62 and 90 be along a straight path. As such, conventional MOS turn-on thyristor structures have been constructed with distances that fall within the aforementioned ranges.

As one skilled in the art will appreciate, when gates 60 and 68 are biased with positive voltages greater than their respective thresholds (thus creating inversion channels 66 and 68),
By varying the magnitude of one or both of the voltages applied to gates 60 and 68, the conductivity of the FET current path is
It varies from a minimum value determined primarily by the resistance of the second region 52 (except in the case of low voltage devices 40) to substantially infinity. When operated in FET mode, the semiconductor device 40 is connected to the cathode 58, as opposed to one orientation (i.e., the anode 60 is positively biased relative to the cathode 58) as when the device 40 operates as a thyristor. Current can be passed between the anode 60 and the anode 60 in either direction.

FIG. 3 shows a graph of the current of the device versus time. This is a thyristor and FET
2 illustrates various features of the bimodal semiconductor device 40 of FIG. 2 which have both modes of operation and are capable of being turned on and turned off. To simplify the explanation of Figure 3, the following definitions will be used.

(1) “FET style” means that both gates 60 and 6
8 are biased above their respective threshold voltages (ie both inversion channels 66, 78 are present).

(2) "Thyristor turn-off mode" means that only gate 60 is biased above its threshold voltage (inversion channel 66 is present).

(3) "Thyristor turn-off mode" means that only gate 60 is biased above its threshold voltage (inversion channel 78 is present).

Turn-on of the semiconductor device 40 proceeds in three stages.
In the first phase of period _t1 , device 40 is in FET mode and the current in device 40 rises to the maximum value of the FET current determined by the resistance of the FET current path. As mentioned earlier, this means that gates 60, 68
can be changed by changing the magnitude of one or both of the voltages. In FET mode, the device 40 acts as a majority carrier device so that the period t ₁
can be very short. In the second phase of period _t2 , the device 40 is still in FET mode, but
This step can be deleted if desired. In the third phase, period _t3 , the device 40 is in thyristor turn-on mode. In this manner, the current in device 40 is initially small during the delay time and then increases rapidly during the rise time. The current in device 40 reaches its maximum current value in the thyristor turn-on condition. This maximum value is highly dependent on the state of external circuitry (not shown) to which device 40 is connected.

Turn-off of device 40 proceeds in three stages. The first stage occurs during periods _t4 and _t5 . period t ₄
The length of can be adjusted by changing the magnitude of the voltage applied to gate 68. period
At the beginning of t ₅ , the NPN and PNP transistor structures of device 40 are no longer operating in a regenerative manner, and the current in device 40 drops rapidly during the fall time, causing device 40 to
The holes are recombined with electrons in the second region 52, etc., and disappear in a tail while the holes are substantially eliminated. During the second stage of turn-off during period _t6 , device 40 is kept in FET mode, but this stage can be omitted if desired. period
In the third phase at _t7 , the current in device 40 rapidly decreases to zero as device 40 operates in thyristor turn-off mode and the device acts as a majority carrier device when in FET mode.

One very important advantage in turning off a bimodal type (both FET and thyristor type operation) device 40 is that it relaxes the design constraints on the turn-off cell as shown at 46.
This design constraint is that each turn-off cell is substantially identical to each other, requiring each to turn off the same amount of current flow at the same time during the thyristor turn-off regime.
If one turn-off cell operates more slowly than the other turn-off cells, it will conduct more current at a higher voltage and may overheat and be destroyed.

During turn-off, when device 40 operates in FET mode, all FET current paths (not shown) are ensured to conduct electronic current and the aforementioned problems do not occur. When the device 40 is then operated in a thyristor mode, its turn-off cells only have to turn off a decreasing amount of current, thus significantly reducing the aforementioned problem. When device 40 is initially operated in FET mode (during turn-off) for a period sufficient to cause holes in device 40 to be substantially depleted, its turn-off cell substantially simultaneously
The electron current is turned off reliably, and the above-mentioned problem does not occur.

Furthermore, the bimodal form (just described) of turning on and turning off device 40 is particularly useful in current switching applications. This means that the turn-on and turn-off of a conventional thyristor is
In contrast to the abrupt change in device current whenever the NPN and PNP transistors of a thyristor begin (turn-on) or end (turn-off) their regeneration action, the device 40 has a more gradual change in current. Or it can be turned on or off in a controlled manner. Therefore, 2
The transient voltages generated across the device 40 when turning on or off in a controlled manner are significantly reduced. This reduces the need for expensive noise filters or snubbers.

When manufacturing the semiconductor device 40, the junctions 63 and 7
The first through third regions, eg, regions 50, 52, and 54, are suitably fabricated using conventional techniques for manufacturing thyristors, with 4 forming the main voltage blocking junction of device 40. Gates 60, 68 and their associated insulating layers and fifth region 72 are suitably fabricated using conventional techniques for making FETs. The fourth area,
For example, region 56 is suitably manufactured using either thyristor technology or FET technology.

In the best mode contemplated for carrying out the invention, semiconductor device 40 includes an electrical short (not shown) between cathode 58 and third region 54, which constitutes the base of the NPN transistor structure. .
This short circuit reduces the susceptibility of device 40 to being turned on by noise or thermal currents within the semiconductor body, and increases the turn-off speed of device 40. This is because the short redirects a portion of the hole current for driving the base of the NPN transistor structure and directs it to the cathode 58 where it recombines with electrons from the cathode 58. Electrical short-circuits of this type are known per se. Furthermore, in the best mode, the semiconductor body of device 40 is comprised of a silicon wafer.

Further details regarding turn-off cells such as cell 46 can be found in United States Patent Application No. 331,049, filed December 16, 1981, by the present inventor. This patent application also describes a turn-off cell located in the upper portion of the semiconductor device. This can be incorporated into device 40 to further increase the turn-off speed.

Although the invention has been described by way of example with respect to particular embodiments, many modifications will occur to those skilled in the art. For example, using P-type material instead of N-type material,
By changing the P-type material to N-type and using holes instead of electrons and electrons instead of holes,
Applying the previous description of the invention, complementary semiconductor devices can be made. Furthermore, the device 40
Although it can be fabricated by a Brenna diffusion process as illustrated here, other methods involving etching grooves into the semiconductor body of the device can be used as well. These grooves can have different shapes, depending on whether selective or isotropic etching is used, as well as depending on the crystallographic orientation of the semiconductor body. . Those skilled in the art will also appreciate the range of possible shapes for the grooves.
By way of example, suitable groove shapes can be found in the International Electronic Devices Meeting Reprint No. 12, 1979, pages 88-92.
VAK Temple and PV Gray's paper "DMOS
Theoretical comparison of voltage and on-resistance of VMOS structures and
It is a glyph. Additionally, the second region 52 is doped by doping the portion in contact with the first region 50 to a substantially higher concentration than the other portions of the second region 52 (as described above). , the device can become what is known by the name of an asymmetric device. It is, therefore, to be understood that the following claims are intended to cover all such modifications that are possible within the scope of this invention.

[Brief explanation of drawings]

FIG. 1 is a simplified cross-sectional view of a conventional thyristor, showing a MOS turn-on structure on its top surface. FIG. 2 is a simplified cross-sectional view of a semiconductor structure embodying the invention, and FIG. 3 shows device current versus time illustrating the controlled turn-on and turn-off of a semiconductor device according to an embodiment of the invention. FIG. Explanation of main symbols 42, 44...Turn-on
Cell, 46, 48...Turn-off cell, 50...
...first region, 52 ... second region, 54 ... third region, 56 ... fourth region, 58 ... cathode,
60...Anode, 60,68...Gate, 61,7
0...Insulating layer.

Claims (1)

[Claims] 1. A latch-type semiconductor device whose turn-on and turn-off can be controlled by an insulated gate, comprising a wafer of a semiconductor material having first and second main surfaces, the wafer comprising: including first, second, third and fourth regions joined together in sequence, the first and third regions being of one conductivity type and the second and fourth regions being of opposite conductivity type; , the first and third regions are separated by the second region, and the second and fourth regions are separated by the second region.
are separated by the third region,
The wafer further includes a fifth region of an opposite conductivity type disposed within the first region and spaced apart from the second region, the second region being the first and second regions. extending to both major surfaces, the first and fifth regions extending to the first major surface and separated from the second major surface by a second region; the third and fourth regions extend to the second major surface and are separated from the first major surface by the second region; and the second region
a first channel portion adjacent to the first main surface between regions, and the third region includes a first channel portion adjacent to the first main surface between the fourth region and the second main surface.
a second channel portion adjacent to the second main surface, and a first main electrode on the first main surface in ohmic contact with the first and fifth regions; is arranged, and a second main electrode is provided on the second main surface and is arranged in ohmic contact with the fourth region and electrically insulated from the third region. Further, on the first main surface, a first insulated gate electrode for controlling conduction between the fifth and second regions via the first channel portion is provided on the first main surface. is disposed overlapping the channel portion of the device, and on the second main surface, a device for controlling conduction between the second and fourth regions via the second channel portion. A second insulated gate electrode is disposed overlapping the second channel portion, and a bias is applied between the first and second main electrodes so that the semiconductor device is latched in a conductive state. In a semiconductor device, the first channel portion has a function of turning off the semiconductor device when the first channel portion is brought into a conductive state. 2. The first main surface is substantially flat, and the first main surface is arranged so that a straight line perpendicular to the plane of the first main surface and passing through the first channel section passes through the second channel section. 2. The semiconductor device according to claim 1, wherein the channel portion is aligned with the second channel portion so as to face each other with the wafer interposed therebetween. 3. The first channel portion has a lower doping concentration than the remaining portion of the first region, and the second channel portion has a lower doping concentration than the remaining portion of the third region. The semiconductor device according to item 1. 4. the first major surface is substantially planar, and the first channel portion includes first and second portions disposed adjacent to two opposing sides of the first region; A central portion of the first region extends to the first main surface and is in contact with the first main electrode between the first and second portions of the first channel portion. , whereby a reproduction current path is formed between the first main electrode and the second main electrode that passes directly through the wafer and is substantially perpendicular to the plane of the first main surface. A semiconductor device according to claim 1. 5. The semiconductor device according to claim 4, wherein the second channel portion surrounds the fourth region. 6. The semiconductor according to claim 5, wherein the fourth region is aligned with the central portion of the first region as part of the reproduction current path so as to face each other across the wafer. Device. 7. The semiconductor device according to claim 4, wherein the central portion of the first region faces the fourth region across the wafer as part of the reproduction current path. 8. The semiconductor device according to claim 1, wherein each of the fourth and fifth regions comprises a plurality of spaced apart segments. 9 each of the first and third regions comprises a plurality of spaced apart portions, each of the portions of the first region surrounding one of the segments of the fifth region; 9. The semiconductor device according to claim 8, wherein each of said portions surrounds one said segment of said fourth region. 10 A latch-type semiconductor device capable of being turned off by an insulated gate, comprising a wafer of semiconductor material having first and second major surfaces, the wafer having first and second major surfaces bonded together in sequence. 2, a third and a fourth region, the first and third regions being of one conductivity type and the second and fourth regions being of opposite conductivity type; separated by the second region, the second and fourth regions;
are separated by the third region,
Each of the first, third and fourth regions is comprised of a plurality of spaced apart segments, and the wafer is further disposed within each segment of the first region and each segment of the second region. a fifth segment of opposite conductivity type consisting of a plurality of segments separated from the region;
the second region extends to both the first and second major surfaces, and a segment of each of the first and fifth regions extends to the first major surface. and separated from the second major surface by the second region, and a segment of each of the third and fourth regions extends to the second major surface and is separated from the second major surface by the second region. The first main surface is separated from the first main surface by a region of An electrode is arranged, and a second main electrode is provided on the second main surface and is arranged in ohmic contact with the fourth region and electrically insulated from the third region. and further includes a plurality of first cells distributed along the first main surface, and a repeating distance of the first cells along the first main surface is equal to the minimum thickness of the second region. each of the first cells is shorter than the second cell.
, one segment of the first region and one segment of the fifth region, and of the opposite conductivity type between the segment of the fifth region and the second region. conductor-insulator-semiconductor type means for controlling transport of majority carriers, the means comprising: a bias applied between the first and second main electrodes so that the semiconductor device is in a conducting state; It has a function of controlling turn-off of the semiconductor device when latched, and further includes a plurality of second cells distributed along the second main surface, Said second
a repeating distance along a major surface of the cell is less than a minimum thickness of the second region, and each of the second cells includes a portion of the second region, a segment of the third region, and a segment of the third region. and conductor-insulator-semiconductor type means for controlling the transport of said majority carriers of opposite conductivity type between said second main electrode and said second region. A semiconductor device characterized by: 11 the first major surface is substantially planar, each of the first cells includes a first channel portion, each of the second cells includes a second channel portion, and the first major surface is substantially planar; Each of the channel portions is aligned with one of the second channel portions so as to face each other across the wafer, and passes through each of the first channel portions perpendicularly to the plane of the first principal surface. 11. The semiconductor device according to claim 10, wherein a straight line passes through the one second channel section. 12. The first channel portion has a lower doping concentration than the remaining portion of the first region, and the second channel portion has a lower doping concentration than the remaining portion of the third region. The semiconductor device according to item 11. 13 a first channel portion disposed adjacent to two opposing side surfaces of the first region;
and a second portion, with a central portion of the first region extending to the first major surface and a second portion of the first channel portion between the first and second portions of the first channel portion. a regeneration current substantially perpendicular to the plane of the first major surface, the regeneration current passing through the wafer directly between the first and second major electrodes; 12. The semiconductor device according to claim 11, wherein a path is formed. 14. The semiconductor according to claim 13, wherein the fourth region is aligned with the central portion of the first region as part of the reproduction current path so as to face the wafer. Device. 15. The semiconductor according to claim 13, wherein the central portion of the first region is aligned to face the fourth region across the wafer as part of the reproduction current path. Device.