JPS61230360A - Manufacture of prom element - Google Patents

Abstract

PURPOSE:To form a PROM element in size sufficiently smaller than a conventional method even in consideration of the extension of an impurity region in a thermal annealing process by shaping only one layer having one conduction type in the impurity region formed into a semiconductor substrate. CONSTITUTION:Ions are implanted to an N-type silicon substrate 3, a P<+> type impurity region 6 is shaped through annealing, and a PSG film 4 is grown on the whole surface and a contact hole 12 is formed. Since only one P<+> type impurity region 6 layer shaping a bit line may be formed in the substrate, impurity regions can be shaped at a sufficiently narrow mutual space. An N-type epitaxial layer 7 is grown selectively in the contact hole 12, polysilicon is grown in the vapor phase, and a grown polysilicon layer 8 is removed with the exception of the contact hole while the surface of a contacting section is finished smoothly. As ions are implanted, a dielectric thin-film 9 is grown through annealing and thermal oxidation, and lastly an aluminum layer 5 is grown and patterned, thus forming a word line 1.

Description

[Detailed Description of the Invention] [Summary] PR that performs writing using dielectric breakdown of a dielectric thin film
As a method of manufacturing an OM element, the degree of integration was improved by improving the method of forming a pn junction formed at the intersection of a word line and a bit line and an element region made of a dielectric thin film.

[Industrial application field]

The present invention provides PRO that is writable on the user side.
M relates to a manufacturing method that aims to improve the degree of integration.

Two methods are generally used to write FROM. That is, there are two types: a joint breaking type and a fuse blowing type.

The junction destruction type writes information by applying an overvoltage to pn junctions connected back to back to destroy the junction biased in the reverse direction and leaving only the junction in the forward direction.

The fuse blowing type has a structure in which writing is performed by blowing a fuse connected to a transistor or a diode.

- There is a strong demand for the development of FROM, which increases the memory capacity per chip, is easier to manufacture, and has higher reliability.
A structure has been proposed in which a dielectric thin film is formed and writing is performed using the dielectric breakdown of the dielectric thin film.

[Conventional technology]

FRO using dielectric breakdown of dielectric thin film mentioned above
The structure of M will be explained in more detail with reference to the drawings.

FIG. 2 is a partially enlarged plan view of the matrix array section of FROM, and FIG. 4 is an XX plane of the storage element section at the intersection of word line 1 and bit line 2 in FIG. An enlarged cross-sectional view is shown.

In the drawing, 3 is an n-type silicon substrate, 4 is an insulating film such as a PSG film or silicon dioxide film, 5 is a word line wiring layer made of aluminum or other conductor, and 6 is a p° type impurity forming a bit line. A region 7 is an n4 type impurity region formed at the intersection of a word line and a bit line, 8 is a doped polysilicon buried layer, and 9 is a dielectric thin film of silicon dioxide.

When the structures in FIGS. 2 and 4 are rewritten as a circuit diagram, they become as shown in FIG. 3. Diode lO is p+ type region 6
, n4 type region 7, and a capacitor 11 is formed of a wiring layer 5 with a dielectric thin film 9 sandwiched therebetween and doped polysilicon 8.

During writing, dielectric breakdown of capacitor 11 causes diode 10 to be directly connected to word line I.

The outline of the manufacturing process of the FROM having the above structure will be briefly explained.

Boron ions are implanted using a mask that opens bit line regions linearly on the n-type substrate 3, and annealing is performed to form p''
Region 6 is formed.

Next, the PSGS composite film is laminated over the entire surface, and a contact hole 12 is opened in the element formation region. As ion implantation and annealing are performed to form n' region 7.

Next, polysilicon is grown over the entire surface by CVD, followed by As ion implantation, annealing, and patterning to form a doped polysilicon layer 8.

Furthermore, by thermally oxidizing the polysilicon layer 8, 250 to 300 silicon dioxide dielectric films 9 are grown.

Next, a wiring layer 5 of aluminum is deposited and patterned to form word lines 2.

[Problem that the invention seeks to solve]

In the above-mentioned method for manufacturing a FROM using the insulation film breakdown method, a pn junction region is formed within a silicon substrate.

Considering the expansion of the lateral profile of the impurity region during the annealing process after ion implantation, the pn junction region cannot be made extremely narrow.

The spacing between the bit lines 2 must be determined taking this into consideration, and this becomes an obstacle to improving the degree of integration as a FROM.

[Means for solving problems]

The above problems are solved by the method of the present invention, which comprises the following manufacturing method.

A bit line is formed by linearly introducing impurities of an opposite conductivity type into a semiconductor substrate of one conductivity type.

Next, after laminating an insulating film on the substrate, a contact hole is opened, and a semiconductor layer of one conductivity type is filled in the contact hole in the form of a single crystal or polycrystal.

Furthermore, after forming and smoothing a polycrystalline semiconductor layer of one conductivity type on the surface of the buried layer, thermal oxidation is performed to form a dielectric thin film as an oxide film on the polycrystalline semiconductor layer.

forming a conductive layer such as aluminum on the dielectric thin film;
These conductors are interconnected to form word lines.

[Effect]

As explained above, the impurity region formed in the semiconductor substrate only needs to be formed in one layer of - conductivity type, and even considering the spread of the impurity region during the thermal annealing process, it is sufficient compared to the conventional method. Can be made small.

This allows the bit line spacing to be designed to be much smaller than in the past.

〔Example〕

An embodiment of the manufacturing method according to the present invention will be described in detail with reference to the drawings.

The circuit configuration previously explained in FIGS. 2 and 3 remains unchanged.

FIGS. 1(a) to 1(0) are cross-sectional views showing the manufacturing method in order of steps. FIG. 1(a) shows a diagram in which a p-type impurity region 6 is formed by ion implantation into an n-type silicon substrate 3 and annealing, and then a PSG film 4 is grown on the entire surface by the CVD method to form a contact hole 12. .

In the present invention, the p3 type impurity region 6 forming the bit line 2 is
Since only one layer needs to be formed in the substrate, it is possible to form them with sufficiently narrow mutual spacing.

Next, an n-type epitaxial layer 7 is selectively grown to a thickness of about 1 μm in the contact hole 12 . This growth is 5iHC1
+ 500cc/n+in, Ht 2 ffi/l
This is carried out by vapor phase growth in which the substrate is heated to 950° C. using 20 cc/ll1n of H3.

Next, polysilicon is grown in a vapor phase at 800° C. for about 100 minutes. This growth requires S i Ht C1* and H2
Gas is used.

Furthermore, the grown polysilicon layer 8 is removed by ion milling, except for the contact hole, and the surface of the contact portion is smoothed.

After As ion implantation, the temperature was approximately 1000°C.

Anneal for 10 minutes. This state is shown in FIG. 1(b).

Next, thermal oxidation is performed at 850° C. in a dry oxygen atmosphere to grow an oxide film of about 250 layers to form the dielectric thin film 9.

Finally, an aluminum layer 5 is grown and subjected to continuous turning to form word lines 1 and complete the device. This is shown in FIG. 1(C).

〔Effect of the invention〕

The manufacturing method described above makes it possible to limit the formation of the pn junction region of FROM to the contact hole opened in the insulating film layer, which greatly contributes to higher integration and increased storage capacity of PROM. be.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing the manufacturing method according to the present invention in the order of steps; Fig. 2 is a partially enlarged plan view of the matrix array of FROM; Fig. 3 is an equivalent circuit of the memory element section; Fig. 4 is A cross-sectional view of a memory element portion having a conventional structure is shown. In the drawing, 1 is a word line, 2 is a bit line, 3 is an n-type silicon substrate, 4 is an insulating film, 5 is a wiring layer, 6 is a p-type impurity region, 7 is an n-type impurity region, and 8 is polysilicon. 9 is a dielectric thin film, 10 is a diode, 11 is a capacitor, and 12 is a contact hole. Fig. 1 Fig. 2 Kichi l Atonement Vertical) 1 Todo calculation i convex mouth B 3rd floor! ! J

Claims (1)

[Claims] A step of forming a bit line (2) by linearly introducing an impurity of an opposite conductivity type into a semiconductor substrate (3) of one conductivity type, and forming an insulating film (4) on the substrate. ) is laminated, contact holes (
12); burying the contact hole with a semiconductor layer (7) of one conductivity type; and forming a polycrystalline semiconductor layer (7) of one conductivity type on the surface of the buried layer
8), a step of forming a dielectric thin film (9) on the polycrystalline semiconductor layer, and a step of forming a conductor layer (5) on the dielectric thin film to interconnect these conductors. A method for manufacturing a PROM element, comprising the step of connecting to form a word line (1).