JPS61228653A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61228653A JPS61228653A JP7151785A JP7151785A JPS61228653A JP S61228653 A JPS61228653 A JP S61228653A JP 7151785 A JP7151785 A JP 7151785A JP 7151785 A JP7151785 A JP 7151785A JP S61228653 A JPS61228653 A JP S61228653A
- Authority
- JP
- Japan
- Prior art keywords
- film
- active layer
- layer
- si3n4
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に係り、特にトラン
ジスタやダイオード等の素子分離に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to isolation of elements such as transistors and diodes.
集積回路装置の製造において1選択酸化、エピタキシャ
ル成長法は公知の技術として広く用いら4ている。82
図は従来の方法によりnチャネル屋MO8)ッンジスタ
(n−MO8Tと略記する。)を作製する場合の部分断
面図である。すなわち。Single-selective oxidation and epitaxial growth methods are widely used as well-known techniques in the manufacture of integrated circuit devices. 82
The figure is a partial sectional view when an n-channel transistor (abbreviated as n-MO8T) is manufactured by a conventional method. Namely.
まず、p証高比抵抗、例えば100〜300Ω・傷のシ
リコン基板1に周知の選択酸化法によって分離用絶縁膜
であるシリコン酸化膜2を形成する。First, a silicon oxide film 2, which is an isolation insulating film, is formed on a silicon substrate 1 having a p-type high specific resistance, for example, 100 to 300 Ω/scars, by a well-known selective oxidation method.
その後、エピタキシャル成長法により、例えば5〜15
Ω・αの活性層3を形成し、この部分にn−MO8T′
91:形成ス6゜n −M OS T f!、M エバ
次の方法で作製される。After that, by epitaxial growth method, for example, 5 to 15
An active layer 3 of Ω・α is formed, and n-MO8T' is formed in this part.
91: Formation S6゜n -M OS T f! , M Eva is produced by the following method.
活性層3の上にゲート酸化膜4を形成し、n −MO8
Tのしきい値電圧を制御するために、チャネル領域8に
ホルン(B)vイオン注入する。次いで、ゲートとなる
ポリシリコン層5vチャネル領域8の上に形成する。続
いて、nfiのソース領域6およびドレイン領域7Yリ
ン(P)またはヒ素(As)のイオン注入によって形成
する。A gate oxide film 4 is formed on the active layer 3, and n-MO8
In order to control the threshold voltage of T, horn (B)v ions are implanted into the channel region 8. Next, a polysilicon layer 5v which becomes a gate is formed on the channel region 8. Subsequently, the NFI source region 6 and drain region 7Y are formed by ion implantation of phosphorus (P) or arsenic (As).
しかし、このような従来の方法では次のような欠点があ
る。すなわち、集積回路の密度がKくなつてくると、シ
リコン基板1に形成される活性層3の密度も比例して多
くなり、活性層3間の分離幅9も必然的に狭くなり、そ
の制御が困難となる。However, such conventional methods have the following drawbacks. That is, as the density of integrated circuits decreases, the density of the active layers 3 formed on the silicon substrate 1 increases proportionally, and the separation width 9 between the active layers 3 inevitably becomes narrower. becomes difficult.
これにより素子間の分離耐圧不良な引き起こし。This causes poor isolation withstand voltage between elements.
集積回路の製造歩留りt極端に低下せしめていた。The manufacturing yield of integrated circuits has been extremely reduced.
この発明は、上記のような問題点を解消するためになさ
れたもので、エピタキシャル成長法による活性層間の分
離幅を高精度で、かつ再現性よく制御することを目的と
している。This invention was made to solve the above-mentioned problems, and aims to control the separation width between active layers by epitaxial growth with high precision and good reproducibility.
この発明の半導体装置の製造方法は、エピタキシャル成
長法による活性層間に1例えば811NJからなる横方
向成長防止層を設けて、エピタキシャル成長法による各
活性層間の間隔幅上制御し分離耐圧を安定化しよ5とす
るものである。The method for manufacturing a semiconductor device of the present invention is to provide a lateral growth prevention layer of 1, for example, 811NJ between active layers formed by epitaxial growth, and to control the distance width between each active layer formed by epitaxial growth to stabilize the isolation breakdown voltage5. It is something to do.
この発明においては、横方向成長防止層を配設すること
kより、エピタキシャル成長法による活性層の横方向成
長を確実に阻止することか可能となり、n−MO8T間
の耐圧が向上する。In this invention, by providing a lateral growth prevention layer, it is possible to reliably prevent lateral growth of the active layer by epitaxial growth, and the breakdown voltage between n-MO8T is improved.
第1図(a)〜(・)はこの発明の一実施例の主餐工程
段階における状態を示す断面図である−まず、第1図(
a)のようK、半導体基板、例えばpIJlのシリコン
基板1v準備し、その主面上に分離用絶縁膜1例えばシ
リコン酸化膜2を熱酸化法によって形成し、その上にさ
らに81.N、膜を減圧CVD法により形成した後、こ
の81.N、膜を写真製版法でパターンニングする。そ
の後、この81.N、膜tマスクにしてシリ;ン酸化膜
2tエツチングして不要なシリコン酸化膜2′lL−除
去し、シリコン酸化膜2のパターンを形成する0次に第
1図(b)のように、再度シリコン基板1の全面に横方
向成長防止膜、例えば81.N、膜111−形成し、写
真製版法とエツチング法とにより第1図(C)のように
、シリコン酸化膜2の上の必要な部分に81.N、膜1
0を残す、このとき、Si、N、膜10の成長厚みと残
し面積は、後の工程で行うエピタキシャル成長法の成長
厚みと寸法によって決定される。その後第1図(d)の
ように、シリコン基板1上にエピタキシャル成長法によ
って活性層3を形成する。FIGS. 1(a) to 1(・) are cross-sectional views showing the state of an embodiment of the present invention at the main meal process stage. First, FIG.
A K, semiconductor substrate, for example, a silicon substrate 1v of pIJl is prepared as in a), and an isolation insulating film 1, for example, a silicon oxide film 2 is formed on its main surface by thermal oxidation, and further 81. N, after forming the film by low pressure CVD method, this 81. N, pattern the film by photolithography. After that, this 81. The silicon oxide film 2t is etched using the N and film t masks to remove the unnecessary silicon oxide film 2'lL-, and a pattern of the silicon oxide film 2 is formed.As shown in FIG. 1(b), Again, a lateral growth prevention film, for example 81. A film 111 of 81.N is formed, and as shown in FIG. N, membrane 1
At this time, the growth thickness and remaining area of the Si, N, and film 10 are determined by the growth thickness and dimensions of the epitaxial growth method performed in a later step. Thereafter, as shown in FIG. 1(d), an active layer 3 is formed on the silicon substrate 1 by epitaxial growth.
次に第1図(・)のよ5に、シリコン酸化膜2を除去す
るが、このとき、シリコン酸化膜2上で5t3N。Next, the silicon oxide film 2 is removed as shown in FIG.
膜10で覆われていない部分にはポリシリコン層11が
形成されるが、必要に応じこの部分はエツチングにより
除去してもよい。A polysilicon layer 11 is formed in the portion not covered by the film 10, but this portion may be removed by etching if necessary.
上記のブーセスにより活性層3が個々に分離される。そ
して、最後にこの活性層30部分にn−MO8Tv形成
して行く。ここでは、特に比較的ディメンジョンの大き
な場合に付いてaqi4したが。The active layer 3 is separated into individual parts by the above-described process. Finally, n-MO8Tv is formed in this active layer 30 portion. Here, aqi4 is used especially in cases where the dimension is relatively large.
n −M O8Tが超LSIに進展してくると素子間の
分離耐圧が不安定となるが、プロセスの分離工程におい
て、この発明による横方向成長防止膜である81.N4
膜10’t−設けることによりこの問題は完全に解決す
る。As n-M O8T develops into VLSIs, the isolation breakdown voltage between elements becomes unstable, but in the isolation step of the process, the lateral growth prevention film 81. N4
By providing the membrane 10't- this problem is completely solved.
なお、上記実施例では、n−MO8Tの電気的な分離を
目的として説明したが、集積回路V製作する上で素子間
の寸法精度が必要な工程においても使用できることは明
らかである。Although the above embodiment has been described for the purpose of electrically isolating n-MO8T, it is clear that the present invention can also be used in a process that requires dimensional accuracy between elements when manufacturing an integrated circuit V.
この発明は以上説明したとおり、半導体基板上に所望の
パターンの分離用絶縁1[を形成し、この分離用絶最膜
上Ky!IF望のパターンで横方向成長防止膜を形成し
た後、エピタキシャル成長法により活性層を形成するよ
うにしたので、各活性層は確実に分離され、上記各活性
層に形成したトランジスタの分離耐圧が不安定となるこ
とがない利点が得られる。As explained above, this invention forms a desired pattern of isolation insulator 1 on a semiconductor substrate, and then forms Ky! After forming the lateral growth prevention film in the desired IF pattern, the active layer is formed by epitaxial growth, so each active layer is reliably separated, and the isolation breakdown voltage of the transistor formed in each active layer is ensured. The advantage is that it does not become stable.
第1図(a)〜(@)はこの発明の一実施例を説明する
ための工程断面図、第2図は従来のn −M 08Tの
構造を示す断面図である。
図において、1はシリコン基板、2はシリコン酸化膜、
3はエピタキシャル成長法による活性層。
10はSL、N、膜である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大岩 増雄 (外2名)
第1図
第1図
第2図FIGS. 1(a) to (@) are process cross-sectional views for explaining one embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the structure of a conventional n-M08T. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film,
3 is an active layer formed by epitaxial growth. 10 is SL, N, membrane. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 1 Figure 2
Claims (1)
した後、前記分離用絶縁膜の間の前記半導体基板上に電
気持性の異なる活性層を成長せしめる半導体装置の製造
方法において、前記分離用絶縁膜の上に前記活性層の横
方向の成長を防止する横方向成長防止層を形成した後、
前記活性層をエピタキシャル成長により形成せしめるこ
とを特徴とする半導体装置の製造方法。In the method for manufacturing a semiconductor device, in which an isolation insulating film having a desired pattern is formed on a semiconductor substrate, and then active layers having different electrical properties are grown on the semiconductor substrate between the isolation insulating films. After forming a lateral growth prevention layer on the insulating film for preventing lateral growth of the active layer,
A method of manufacturing a semiconductor device, characterized in that the active layer is formed by epitaxial growth.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7151785A JPS61228653A (en) | 1985-04-02 | 1985-04-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7151785A JPS61228653A (en) | 1985-04-02 | 1985-04-02 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61228653A true JPS61228653A (en) | 1986-10-11 |
Family
ID=13462983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7151785A Pending JPS61228653A (en) | 1985-04-02 | 1985-04-02 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61228653A (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4944787A (en) * | 1972-08-31 | 1974-04-27 | ||
JPS4946113A (en) * | 1972-09-14 | 1974-05-02 | ||
JPS49115672A (en) * | 1973-03-07 | 1974-11-05 | ||
JPS509598A (en) * | 1973-05-30 | 1975-01-31 | ||
JPS57207348A (en) * | 1981-06-16 | 1982-12-20 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1985
- 1985-04-02 JP JP7151785A patent/JPS61228653A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4944787A (en) * | 1972-08-31 | 1974-04-27 | ||
JPS4946113A (en) * | 1972-09-14 | 1974-05-02 | ||
JPS49115672A (en) * | 1973-03-07 | 1974-11-05 | ||
JPS509598A (en) * | 1973-05-30 | 1975-01-31 | ||
JPS57207348A (en) * | 1981-06-16 | 1982-12-20 | Fujitsu Ltd | Manufacture of semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS63304657A (en) | Manufacture of semiconductor device | |
US4577397A (en) | Method for manufacturing a semiconductor device having vertical and lateral transistors | |
JPS59121976A (en) | Semiconductor device | |
JP2617177B2 (en) | Integrated circuit isolation structure and method of forming the same | |
US4775644A (en) | Zero bird-beak oxide isolation scheme for integrated circuits | |
US4885261A (en) | Method for isolating a semiconductor element | |
KR910000020B1 (en) | Manufacture of semiconductor device | |
JPS59208851A (en) | Semiconductor device and manufacture thereof | |
JPS61228653A (en) | Manufacture of semiconductor device | |
JPS6040702B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
JP2793141B2 (en) | Method of manufacturing semiconductor device having trench element isolation film | |
JPS6050063B2 (en) | Complementary MOS semiconductor device and manufacturing method thereof | |
JPS60144950A (en) | Manufacture of semiconductor device | |
JPH0290569A (en) | Manufacture of semiconductor device | |
JPS5919349A (en) | Semiconductor device and manufacture thereof | |
JPH03177072A (en) | Semiconductor device and its manufacture | |
JPS6025247A (en) | Manufacture of semiconductor device | |
JPH08213407A (en) | Semiconductor device | |
JPS63144543A (en) | Formation of semiconductor interelement isolation region | |
JPH03240244A (en) | Semiconductor device and its manufacture | |
JPS60128633A (en) | Semiconductor device and manufacture thereof | |
JPS5810857A (en) | Complementary type mos semiconductor device | |
JPH0316777B2 (en) | ||
JPH0546988B2 (en) | ||
JPS5979564A (en) | Semiconductor integrated circuit device |