JPS5979564A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5979564A
JPS5979564A JP18901582A JP18901582A JPS5979564A JP S5979564 A JPS5979564 A JP S5979564A JP 18901582 A JP18901582 A JP 18901582A JP 18901582 A JP18901582 A JP 18901582A JP S5979564 A JPS5979564 A JP S5979564A
Authority
JP
Japan
Prior art keywords
type
layer
well
buried
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18901582A
Other languages
Japanese (ja)
Inventor
Akira Muramatsu
彰 村松
Hideki Yasuoka
秀記 安岡
Norio Anzai
安済　範夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18901582A priority Critical patent/JPS5979564A/en
Publication of JPS5979564A publication Critical patent/JPS5979564A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Abstract

PURPOSE:To form elements in a small size, and moreover to prevent a semiconductor integrated circuit device from a reduction of terminal voltage when a bi-polar transistor and a C-MOS FET are to be made to coexist in an n type epitaxial layer on a p type substrate buried with n<+> type layers by a method wherein formation of the buried layer directly under a p-well is avoided. CONSTITUTION:An n<-> type epitaxial layer 2 on a p<-> type Si substrate 1 buried with n<+> type layers 3a, 3b is isolated by a p type layer 4, and a p<-> well 5 is formed avoiding the layer 3a. Field oxide films 8 are formed selectively, and an n<+> type collector lead out layer 9 and a p type base 10 are provided by diffusion in order in the n<-> type layer 2 on the layer 3b at first, and poly-Si gates 12 are formed on the n<-> type layer 2 on the layer 3a in succession interposing gate oxide films 11 between them. After then, p<+> type layers 13, n<+> type layers 16 and an n<+> type emitter 17 are provided applying properly SiO2 masks 14, 15 to complete a C-MOS FET and a bi-polar transistor. According to this construction, even when the epitaxial layer 2 is formed thin, the reduction of withstand voltage according to arising to the p-well 5 from the buried layer 3a can be avoided, and the device can be formed in a fine size.

Description

【発明の詳細な説明】 本発明は半２．ｑ体年債回路装置（以下、ＩＣと称ずろ
）、特に絶縁ゲート電界効果トランジスタをイｊするＴ
Ｃに関ずイ）。DETAILED DESCRIPTION OF THE INVENTION The present invention is based on semi-2. q-type circuit devices (hereinafter referred to as ICs), especially insulated gate field effect transistors.
Regarding C).

例えば、一つの半導体基体にバイポーラトランジスタと
相補型絶縁ゲ−１・ｌ／）、’異物。弔トランジスタ（
以下、Ｃ−Ｍ　ＯＳ　Ｆ　Ｅ　Ｔと称−４−ｏ）を共存
させたバイポーラへＴＯ３ＩＣ（Ｊ以下Ｔ３ｉ−ＣＭＯ
８ＪＣと称す。）として、第１図に示すような構造が知
られている。すなわち、このＢｉ−６ＭＯ８ＩＣは、高
比抵抗のｐ型Ｓｉ（シリコン）基板１上に高１．ｌｓ　
＜Ｉ：！ｒ：抗のｎ型Ｓｉ層２をパ［ビクキシャル成長
させ、か−）、そのｌ）型基板１とｎ型層２０間に高渭
゛（度のｎ＋型埋込１ｊ’ｉ　３を部分的に設け、１１
型層２を酸化；１．（やｐｎ接合を利用したアイソレー
ジ９ン部４により曲数の島領域に分離するとともにｎ覗
層の一部にｐ型拡散ウェル領域５を形成し、一つの島領
域のｐ型ウェル５表面にｎチャネルＭＯ８ＦＥＴ＆、ウ
ェルの形成されないｎ　Ｎ層の表面の一部にｐチャネル
Ｍ　ＯＳ　Ｆ　Ｅ　Ｔをそれぞれ形成し、そして他の島
領域のｎ型層表面にｎｐｎ　　ｌ・ラン９２、りを形成
した構造を有している。For example, a bipolar transistor and a complementary insulating gate (1.l/) on a single semiconductor substrate, 'foreign matter. Funeral transistor (
TO3IC (hereinafter referred to as C-MOS FET and -4-o) coexisting with TO3IC (hereinafter referred to as T3i-CMO
It is called 8JC. ), a structure as shown in FIG. 1 is known. That is, this Bi-6MO8IC is mounted on a p-type Si (silicon) substrate 1 with a high resistivity of 1. ls
<I:! r: The anti-n-type Si layer 2 is grown paralytically (or -), and the n+-type embedding 1j'i 3 is partially grown between the n-type substrate 1 and the n-type layer 20. 11
Oxidize mold layer 2;1. (A p-type diffusion well region 5 is formed in a part of the n-hole layer, and a p-type diffusion well region 5 is formed on the surface of the p-type well 5 of one island region.) An n-channel MO8FET and a p-channel MOSFET were formed on a part of the surface of the nN layer where no well was formed, and an npn l-run 92 and ri were formed on the surface of the n-type layer in the other island region. It has a structure.

同図において、ｎ＋型埋込層３はｎｐｎ）・ランジスタ
のコレクタ抵抗を低減するためにパイボーラ隼子の直下
に形成されるものであるが、同時にＭ　ＯＳ　素子の下
にも埋め込んでＣＭ　ＯＳ　Ｆ　Ｅ　Ｔのラッチアップ
防止を１９４っていζン。才なわら、ｎ＋型埋込層３に
よりＰ　ＭＯＳ　Ｆ’Ｅ　Ｔの■げ型層、ｎ−型層およ
びｐウェルより構成された寄生トランジスタの動作を防
止１〜ている。In the same figure, the n+ type buried layer 3 is formed directly under the piebola Hayabusa in order to reduce the collector resistance of the npn) transistor, but it is also buried under the MOS element at the same time to reduce the collector resistance of the npn) transistor. ET latch-up prevention with 194mm. In addition, the n+ type buried layer 3 prevents the operation of the parasitic transistor constituted by the exposed layer of the PMOS F'ET, the n- type layer, and the p well.

とこ７）で、かかる４’ｆ！￥造のＢｉ−ＣＭＯ８ＩＣ
においで、エピタキシャルｎ型層２が十分に厚い場合は
特に間ｊ７Ｆ１はないが、バイポーラ素子を微細化して
高速化、高集積化するためにＩＡ型層２の厚さを２７１
　ｍ程度に薄くした場合にｎ＋型埋込層３のエピタキシ
ャル層、１ｒ１１−にｐ型ウェル５への「わき上り」拡
散が問題となる。すなわち、ｎチャネルＭＯ、’、；　
Ｆ　Ｅ　’！’の形成されるｐ型ウェル５はＭＯＳＦＥ
Ｔのしきい電圧■ｔｈを規定するために低濃度で充分に
時間をかげてｐ型拡散処理を行なう必要があり、このと
きｎ＋型埋込層３がｐ型ウェル直下に拡散してソース・
ドレインｎ＋型領域６とｎ＋型埋込層３との距離が短か
くなりその結果ドレイン耐圧が小さくなることになった
。At 7), it takes 4'f! Bi-CMO8IC for ¥
In the case where the epitaxial n-type layer 2 is sufficiently thick, there is no particular gap between j7F1, but in order to miniaturize the bipolar element and increase its speed and integration, the thickness of the IA-type layer 2 may be increased to 271 cm.
When the thickness is reduced to about m, "upward" diffusion of the epitaxial layer of the n+ type buried layer 3, 1r11-, into the p type well 5 becomes a problem. That is, n-channel MO,′,;
FE'! 'The p-type well 5 formed is a MOSFE
In order to define the threshold voltage (■th) of T, it is necessary to perform p-type diffusion treatment at a low concentration and with sufficient time.At this time, the n+ type buried layer 3 is diffused directly under the p-type well, and the source
The distance between the drain n+ type region 6 and the n+ type buried layer 3 is shortened, resulting in a decrease in drain breakdown voltage.

本発明は上記した問題を解決するためになされたもので
あり、その目的とするところは、エピタキシャル層を薄
くして素子を微細化できしかも耐圧低下を少なくした１
３ｉ−ＣＭＯ３ＩＣ乃至ＣＭＯ８ＩＣの提供にある。The present invention was made in order to solve the above-mentioned problems, and its purpose is to make the epitaxial layer thinner, to miniaturize the device, and to reduce the drop in breakdown voltage.
3i-CMO3IC to CMO8IC are provided.

以下実施例にそって本発明な詳述する。The present invention will be described in detail below with reference to Examples.

第２図は本発明の一実施例を示す１３ｉ−ＣＭＯ３ＩＣ
の断面図である。FIG. 2 shows a 13i-CMO3IC showing an embodiment of the present invention.
FIG.

このＩ’３ｉ−ＣＭＯ８ＩＣは、Ｉ〕−型Ｓ五基板１の
一主面にエピタキシャル成長さぜたｎ型Ｓｉ層２を有し
、ｐ−型基板１とｎ型層２との間に部分的にｎ＋型埋込
層３ａ、３ｂが設けられている１、１１型ＳＩ層２の一
部にはｐ型ウェル領域５が形成されている。そして、こ
のｎ　ｐ、９　Ｓ　ｒ層２はｐ型拡１１（層４及び厚い
フィールド酸化）摸８によるアイソレーション部により
いくつかの島領域に分離されている１、ｐ　ｉ４！ｊウ
ェル５衣而にはソース・ドレインｎ＋型領域１６と絶縁
ゲート１２とによるｎチャネルＭＯ８ＦＥＴが設けられ
、同じ島領域のｎ型１９１２表面にはソース・ドレイン
ｐ＋型憤域１３と絶縁ゲート１２とによるｐチャネルＭ
　ＯＳ　Ｆ　Ｅ　Ｔとがそれぞれ設けられている。そし
て、他の島領域の１〕型層表面にはベースｐ型層１０．
コレクタ！１型層９及びエミツタ１１＋型層１７からな
るｎｐｎ　トランジスタが設けられている。本発明のＢ
ｉ−ＣＭＯ８ＩＣは、第２図から明らかなように、ｐ−
型基板１とｎ型層２０間に設けられたｎ＋型埋込層３ａ
、：う１〕は■）チャネルＭＯ８ＦＥＴの直下とｎｐｎ
ｌ・シンジスタの直下に存在しているが、ｎチャネルＭ
　ＯＳ　Ｆ　Ｅ　Ｔのある［）型ウェル直下には存在し
ていない。This I'3i-CMO8 IC has an n-type Si layer 2 epitaxially grown on one main surface of an I]-type S5 substrate 1, and a portion is formed between the p-type substrate 1 and the n-type layer 2. A p-type well region 5 is formed in a part of the 1 and 11-type SI layer 2 in which the n+-type buried layers 3a and 3b are provided. This n p,9 S r layer 2 is separated into several island regions by an isolation section by a p-type expansion 11 (layer 4 and thick field oxidation) 8 1, p i4! An n-channel MO8FET with a source/drain n+ type region 16 and an insulated gate 12 is provided in the j-well 5, and a source/drain p+ type region 13 and an insulated gate 12 are provided on the surface of the n-type 1912 in the same island region. p-channel M by
OS FET are provided respectively. A base p-type layer 10.
collector! An npn transistor consisting of a type 1 layer 9 and an emitter 11+ type layer 17 is provided. B of the present invention
As is clear from FIG. 2, i-CMO8IC has p-
n+ type buried layer 3a provided between type substrate 1 and n type layer 20
, : U1] is ■) Directly below the channel MO8FET and npn
It exists directly under the l-synister, but the n-channel M
It does not exist directly under the [ ) type well with OS FET.

次に、本発明によるＩｌｉ　−ＣＭＯＳ　Ｉ　Ｃの製造
プロセスの１１コ施例は下記の工程（１）　−（８１に
従って行われ、第３図乃Ｌａｌ’ｙ　１０図が対応する
。Next, 11 embodiments of the manufacturing process of Ili-CMOS IC according to the present invention are carried out according to the following steps (1)-(81), and FIGS. 3 to 10 correspond.

（１）高山抵抗ｐ−型Ｓｉ基板１の表面に１１　　型埋
込ハ”ｉ　３　ａ　、　　３　ｂをマスクｓｂ拡散によ
り形成する（第３図）。このとぎウェル位置Ｋｎ＋型埋
込層がかからないパターンなＩ△ぷ。(1) Form 11-type buried layers I3a, 3b on the surface of the high-resistance p-type Si substrate 1 by mask sb diffusion (Fig. 3).At this well position, the Kn+-type buried layer is not covered. Pattern I△pu.

（２）イ９しト純物儂度ｎ−型Ｓｉ層２を２〜４１１ｒ
ｒＬ厚い一エピタキシャル成長させる。ｎ−型Ｓｉ層の
一部に接合アイソレーションｒｔ＋ｓ　４をＢ拡散によ
り形成す７−）（第４図）。(2) A pure n-type Si layer 2 of 2 to 411r
Grow a thick epitaxial layer. Junction isolation rt+s 4 is formed in a part of the n-type Si layer by B diffusion 7-) (FIG. 4).

（３）ｐ−型ウェル５ンつくろためのＢイオン打込み拡
散を行なう（第５図）。(3) Perform B ion implantation and diffusion to create 5 p-type wells (Fig. 5).

（４）　　ナイトライド（ＳＩ３Ｎ４）マスク７による
Ｌ　０ＣＯ８（低温選択酸化技術）により厚いフィール
ドｒＩ９化膜８を形成する（第６図）。(4) A thick field rI9 film 8 is formed by L0CO8 (low temperature selective oxidation technology) using a nitride (SI3N4) mask 7 (FIG. 6).

（５）バイポーラ部のコンタク・コンタクト１１＋型層
（ＣＮ）９形成のためのＰ　（’Ｊン）デボ拡散、つづ
いてベースｐ型層（Ｊ３　Ｒ，）　１．６形成のための
Ｂ（ボロン）デボ拡散を行なう（第７図）。(5) P ('Jn) debo diffusion for forming the contact contact 11+ type layer (CN) 9 of the bipolar part, followed by B (boron) diffusion for forming the base p type layer (J3 R,) 1.6. ) Perform debo diffusion (Figure 7).

（６）フィールド部以外の表面酸化膜な除去した後、熱
酸化により薄いゲート酸化ｊ１１、′！１１な形成し、
そ、の」二にＳｉをデポジットし、ホトエッチしてＭＯ
Ｓ側にポリＳｉゲート１２を形成すｌ）（第８図）。(6) After removing the surface oxide film other than the field area, a thin gate oxide j11,'! is formed by thermal oxidation. 11 formed,
Deposit Si on the second side, photo-etch it and MO
A poly-Si gate 12 is formed on the S side (FIG. 8).

（力　低温酸化＋ＩＩ′、＼１４等を形成し、ポリＳｉ
ゲートをマスクにＢ（ボロン）をイオン打込ろ・、拡散
してｐチャネルＭＯ８ＦＥＴのソース・ドレイン■〕＋
型層１３を形成する（第９図）。(Formation: Low temperature oxidation + II', \14, etc. are formed, and
Using the gate as a mask, implant B (boron) ions and diffuse into the source and drain of the p-channel MO8FET.
A mold layer 13 is formed (FIG. 9).

（８）第１０図に示すように新たな低Ｎ＋’！＋酸化Ｉ
Ｉ（’：によるマスク１５を形成し、他のポリＳｉゲー
トをマスクにＡｓ　（ヒ素）をイオン打込み拡ｆｆｋ　
１．、、ウェル表面に１１チャネルＭ　ＯＳ　Ｆ　Ｅ　
’ｒのソース・ドレイン１１＋型層１６を形成すると同
時にバ・ｒポーラ部にエミツタ１１°型層１７を形成す
る。(8) New low N+' as shown in Figure 10! +oxidation I
A mask 15 is formed by I(':), and As (arsenic) is ion-implanted and expanded using the other poly-Si gate as a mask.ffk
1. ,,11 channel MOS F E on the well surface
At the same time as the 'r source/drain 11+ type layer 16 is formed, the emitter 11° type layer 17 is formed in the bar/r polar portion.

この後、ＰＳＧ（リン・シリケートガラス）　＋１４）
。After this, PSG (phosphorus silicate glass) +14)
.

１８の形成、コンタクトホトエッチ、Ａ−ｅ（アルミニ
ウム）蒸着、そしてホトエッチによるＡ、０電（・鱈１
９の形式を経て第２図に示すごときＢｉ−ＣＭＯ８ＩＣ
を完成する。18 formation, contact photoetching, A-e (aluminum) vapor deposition, and photoetching A, 0electron (・cod 1
9 format and Bi-CMO8IC as shown in Figure 2.
complete.

第１１図はエピタキシャルｎ型層とｐ型ウェル領域にか
けて０ＭＯ８ＦＥＴのみ（バイポーラ素子を形成しない
場合）を有するＩＣにおいて本発明を適用した場合の実
施例を示す。この場合もｐウェル５の直下にはｎ＋型埋
込層は形成されない。FIG. 11 shows an embodiment in which the present invention is applied to an IC having only 0MO8FET (in the case where no bipolar element is formed) across the epitaxial n-type layer and the p-type well region. In this case as well, no n+ type buried layer is formed directly under the p-well 5.

以上、実施例で述べた本発明によれば、少なくともｎチ
ャネルＭＯ８ＦＥＴのあるｐ型ウェルの直下にｎ＋型埋
込層を存在させないことにより、ｎ＋型埋込層のエピタ
キシャル層への１わき上り」がないため、第２図に示し
たエピタキシャルｎ型／？！２の厚さくｄ）が例えばわ
ずかに２７４　ｍ又はそれ以下に薄い場合おいても、ｎ
　型トレイン層とｐ型ウェルとの間のＰＮ接合からｐ型
つェル内部に向かって空乏層は充分のびるため、ｎ＋１
ｆＨＩＪドレイン耐圧を低下させることがない。例えば
、従来のｎチャネルＭＯ８ＦＥＴの下に１げ型埋込層が
ある構造では耐圧を１５Ｖ出そうとする場合、ウェル深
さは４μｍ必要であり、このウェルな拡散により形成１
′る際にｎ＋型埋込層は３５μｍ程１【Ｖも「わき−ヒ
リ」、シたがって、エピタキシャル層の厚さは８μｍを
必要としたが、本発明によればｎ＋型埋込層の１わき七
り分」約３，５７１ｍ分だけエピタキシャル層を薄くす
ることができる。すなわち、エピタキシャル層の厚さｄ
ｋ２〜４μｍｆ４度としても十分なドレイン耐圧か得ら
れる。なおｐヂャネルＭＯ８ＦＥＴおよびｎｐｎ）ラン
ジスタにおいてはｎ＋型埋込層の［＝わき上９１は殆ん
ど問題にならない。According to the present invention described in the embodiments, at least by not having an n+ type buried layer directly under the p type well where the n channel MO8FET is located, the n+ type buried layer rises up to the epitaxial layer. Since there is no epitaxial n-type/? ! Even if the thickness d) of 2 is thinner, for example only 274 m or less, n
Since the depletion layer extends sufficiently from the PN junction between the type train layer and the p-type well toward the inside of the p-type well, n+1
There is no reduction in fHIJ drain breakdown voltage. For example, in a conventional n-channel MO8FET with a structure in which there is a buried layer under it, if you want to output a withstand voltage of 15V, the well depth needs to be 4 μm.
The thickness of the n+ type buried layer was approximately 35 μm when the n+ type buried layer was used. The epitaxial layer can be thinned by approximately 3,571 m by 1 width. That is, the thickness d of the epitaxial layer
Sufficient drain breakdown voltage can be obtained even if k2 to 4 μm f4 degrees. Note that in a p-channel MO8FET and an npn) transistor, the side 91 of the n+ type buried layer hardly poses a problem.

このように薄いエピタキシャル層な使用できる結果、拡
散や酸化によって、形成するアイソレーション部の（７
へ方向の余裕を小さくすることができる。千ノブ面１７
ｔを小さく（高集積化）できるとともニｆｋｌｌえばＳ
ｉゲート３　／ｉ　ｍ長の高速化Ｉ’３ｉ−ＣＭ　ＯＳ
　Ｉ　Ｃを実現できることになった。As a result of being able to use such a thin epitaxial layer, the isolation region (7
The margin in the direction can be reduced. Sennobu side 17
If t can be made smaller (higher integration), S
i Gate 3 /i m length acceleration I'3i-CM OS
It became possible to realize IC.

本発明は前記実施例に限定されない。例えば（図示され
ブＩい）　ｌｌｉ−ＣＭＯ８Ｉ　Ｃにおいて、バイポー
ラｎｐｎ）ランジスタ直下にのみｎ＋型埋込層な形成し
、ｎチャネルＭＯ３ＦＥＴ及びｐチャネルＭ　□Ｓ　Ｆ
　Ｅ　Ｔの下には＋１＋型埋込層を・形成しない４４’
ｌ”造をどる場合にも本発明の前記効果が得られイ）。The invention is not limited to the above embodiments. For example, in lli-CMO8IC (not shown), an n+ type buried layer is formed only directly under the bipolar npn) transistor, and n-channel MO3FET and p-channel M □S F
+1+ type buried layer is not formed under E T44'
The above-mentioned effects of the present invention can be obtained even when the structure is changed to 1".

ただこの場合、０ＭＯ８ＦＥＴのラソチアッノ゛が間層
１どなる。However, in this case, the lasso chino of the 0MO8FET becomes the interlayer 1.

本発明はＴ３ｉ　−ＣＭＯＳ　Ｉ　Ｃ及びラッチアップ
防市のためにｎ−Ｉ　型埋込層を部分的に有する６ＭＯ
３ＩＣの全てに適用できるものである。The present invention is a 6MO with partial n-I type buried layer for T3i-CMOS IC and latch-up prevention.
This is applicable to all 3 ICs.

【図面の簡単な説明】[Brief explanation of the drawing]

るＩ′５１図はｒｌｉ　−ＣＭＯＳ　Ｉ　Ｃの一例を模
式図的に示した断面図である。 第２図は本発明による１３ｉ−ＣＭＯ８ＩＣの一実施例
を示す断面図である。 第３図〜第１０図は本発明による丁１ｉ−ＣＭＯ８ＩＣ
をその製造プロセスで示す工程断面図である。 第１１図は本発明にょろ１３ｉ　−ＣＭＯＳ　Ｉ　Ｃの
他の一実施例を示す断面図である。 １　　・ｐ〜型Ｓｉ基板、２−　ｎ型Ｓｉ層、３ａ。 ３ｂ・・・０＋を埋込層、４・・−１イル−ジョン１）
型層、５・・・ｐ　　−５ウエル、６・・ｎ１型ソース
・ドレイン、７・・・ナイトライド膜、８・フィールド
酸化膜、９・・・ｎ＋型コレクタ、１０・・・ｐ型ベー
ス、１１・・・ゲート自安化月シ＼、１２・・・ポリＳ
ｉゲート、１３・・・ｐ″°型ノース・ドレイン、１４
．１５・・・マスク、１６・・・ｐ＋型７−ス・ドレイ
ン、１７・・・ｎ＋型エミッタ、１８−　Ｐ　Ｓ　Ｇｄ
ｌ’！、１９　・Ａ、−（３電（敵。 第　　７　　図 第　　９　　図 第１０図Figure I'51 is a sectional view schematically showing an example of rli-CMOS IC. FIG. 2 is a sectional view showing an embodiment of a 13i-CMO8 IC according to the present invention. FIG. 3 to FIG. 10 show the D1i-CMO8IC according to the present invention.
FIG. 3 is a process sectional view showing the manufacturing process. FIG. 11 is a sectional view showing another embodiment of the Nyoro 13i-CMOS IC of the present invention. 1. P-type Si substrate, 2- N-type Si layer, 3a. 3b...0+ is embedded layer, 4...-1 illusion 1)
type layer, 5... p-5 well, 6... n1 type source/drain, 7... nitride film, 8... field oxide film, 9... n+ type collector, 10... p type base , 11...Gate Jianka Tsukishi\, 12...PolyS
i-gate, 13...p''° type north drain, 14
．． 15...Mask, 16...p+ type 7-s drain, 17...n+ type emitter, 18-P S Gd
l'! , 19 ・A, - (3 electricity (enemy. Figure 7 Figure 9 Figure 10

Claims (1)

【特許請求の範囲】[Claims] ■　第１導電匹ν半導体基板の一主面上に第２導電型半
り！フ１体層を有し、第１導電型基板と第２導電型層と
の間に部分的に第２導電型高濃度埋込層が設けられ、第
２導電型十２！゛２体層の一部に第１導電型ウエル領１
成が形成され、このウェル領域表面とウェルの形成され
ない半導体層の一部の表面にチャネル力電型の異なるＭ
ＯＳＦＥＴが相補的に設けられるどどもにウェルの形成
されない半導体１ｖうの他の−↑１］（にバイポーラト
ランジスタが設けられた半樽体隼債回Ｉｌ！、）装置に
おいて、−ヒ記第２導電型高４′（度埋込層は少なくと
も第１導電型ウエル領域直下には形成されていないこと
を特徴どする半ＮＪ体集積回ｉｉ：５１’、　ｉ］′□
′Ｊ′。■ The first conductive type ν The second conductive type is placed on one main surface of the semiconductor substrate! A second conductivity type high-concentration buried layer is partially provided between the first conductivity type substrate and the second conductivity type layer, and the second conductivity type 12!゛First conductivity type well region 1 in a part of the two-body layer
M is formed on the surface of this well region and on the surface of a part of the semiconductor layer where no well is formed, and has a different channel power type.
In a device in which OSFETs are provided complementary to each other and no well is formed in the semiconductor 1v other than the other -↑1] (a half-barrel body in which a bipolar transistor is provided!), Conductivity type height 4' (half NJ integrated circuit ii: 51', i]'□ characterized in that the buried layer is not formed directly under the first conductivity type well region)
'J'.
JP18901582A 1982-10-29 1982-10-29 Semiconductor integrated circuit device Pending JPS5979564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18901582A JPS5979564A (en) 1982-10-29 1982-10-29 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18901582A JPS5979564A (en) 1982-10-29 1982-10-29 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5979564A true JPS5979564A (en) 1984-05-08

Family

ID=16233869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18901582A Pending JPS5979564A (en) 1982-10-29 1982-10-29 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5979564A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255049A (en) * 1985-05-02 1986-11-12 テキサス　インスツルメンツ　インコ−ポレイテツド Integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61255049A (en) * 1985-05-02 1986-11-12 テキサス　インスツルメンツ　インコ−ポレイテツド Integrated circuit

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