JPS61228543A - Data processing system - Google Patents

Abstract

PURPOSE:To detect a trouble in a buffer memory by adding a circuit which detects the discordance between a diagnosis mode where the Hit signal is suppressed and the read data to fetch simultaneously both a main memory and the buffer memory and comparing the read data given from both memories with each other. CONSTITUTION:A buffer memory 300 stores a partial copy of an instruction or data on a main memory 200 of a data processing system. An access is given to the memory 200 or 300 in response to a program instruction. Then a processor 100 processes a program. The read request and the memory address given from the processor 100 to the memory 200 are sent to both memories 200 and 300 through an address bus 101. Then a comparator 402 compares the memory signals read out of both memories with each other in response to said read request and address. The result of this comparison is delivered as fault diagnosis result of the memory 300. Then the discordance is detected between a diagnosis mode where the Hit signal is suppressed and the read data. Thus a trouble in the memory 300 is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing system having a failure diagnosis function for a buffer storage device.

[Background of the invention]

The buffer storage device is faster than the main storage device, but is composed of small-capacity storage elements, which can reduce the access time of the storage device isometrically, and also shortens the access time of the large-capacity main storage device. A slow and inexpensive memory element can be used, and the cost/performance ratio can be improved. For this reason, it is used in many electronic computers and has recently become an essential component. In order to guarantee normal operation of such a buffer storage device, the problem is how to perform failure detection.

Regarding testing methods for LSI built-in memory, there is a method for static memory in JP-A No. 58-205992, and a method for testing RAM in JP-A-58-205992.
-205993, each of which has a dedicated testing circuit.

However, in such a buffer storage device, the operation of the address association section and data storage section depends on the address and data set during execution, and a dedicated circuit is required to diagnose whether or not the operation is being executed correctly. The problem was that it was complicated.

Furthermore, as the degree of integration of LSIs has improved in recent years, it is also conceivable to realize a microprocessor in which an associative memory is built into the same LSI as a buffer storage device. The associative memory consists of a tag section and a data section, and is a memory that can read data or instructions corresponding to a matching tag by searching the tag section. However, since access to the associative memory is closed only within the LSI chip, diagnosis is difficult, and in order to check the associative memory individually, a diagnostic circuit is required, making it complicated.

Furthermore, in order to diagnose a failure of a buffer storage device using the conventional technology, the data processing device is forced to temporarily suspend normal program execution. However, from a practical standpoint, it is desirable to be able to perform this fault diagnosis during one normal program execution.

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned problems.
It is an object of the present invention to provide a data processing device for a buffer storage device that can perform failure diagnosis of the buffer storage device with a simple circuit.

Still another object of the present invention is to provide a data processing system capable of diagnosing a failure of a buffer storage device while executing a normal program.

[Summary of the invention]

Therefore, when diagnosing a failure in a buffer storage device, a failure in the buffer storage is detected by fetching the main storage and the buffer storage at the same time and comparing the data read from each.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a microprocessor system according to the present invention, where 100 is a microprocessor and 200 is a microprocessor system.
300 is a main memory, 300 is a buffer storage, 301 is an address association section, 303 is a data storage section, 305 is a multiplexer, 401 is an H1L signal suppression circuit, and 402 is a data comparator. Note that 500 is a test control circuit. Setting of fault diagnosis mode by operator or other methods.

This is a circuit that can be reset.

This circuit 500 is preferably provided on an LSI having a microprocessor 100 and a buffer memory 300;
It may be provided outside the LSI. When the processing device 100 accesses a storage device and fetches an instruction or data, it outputs the address to the address bus 101 and a read instruction signal 105. The buffer storage device 300 receives this address 101, and the address association unit 301 determines whether a copy of the main memory corresponding to this address 101 exists in the buffer storage device. If it exists, the Hit signal 302 is asserted and the data storage unit 30
Data 304 is output from 3.

When the test mode signal 400 is not set, the ON output of the inverter 405 causes the AND gate 4
01 is on, the Hit signal 302 is given to the multiplexer 305, and the multiplexer 305 outputs the Hit signal.
Controlled by signal 302, data 304 is transferred to data bus 1.
02 and sends the hit signal to the transfer end report (AC
K) is transferred to the processing device 100 via the 4ft 107, and a transfer completion report 107 is output. Further, since the ON output of the AND gate 401 is given to the AND gate 311 via the inverter 310, the read instruction signal 10
5 is never applied to line 320 and main memory 300 is not accessed. Also, if it does not exist, Hi
The t signal 302 is negated.

A main memory read instruction signal 320 is output from the AND gate 311. The main memory device 200 outputs the corresponding data to the read data bus 201 and at the same time outputs a transfer completion report signal 203. The multiplexer 305 outputs the data 201 read from the external main memory bag [20o] to the data bus 102, and transfers the ACK signal 203 to the processing bag gtoo via the line 107.

Furthermore, data 201 and address 101 read from main memory 200 are written to data storage section 303 and address association section 301, respectively. At this time, the output 302 of the address association unit 301 remains O, so
An AND gate 408 which inputs the inverted output of this output 302 by the inverter 409 and the read instruction signal 105 is turned on and used as a write signal.

Next, the operation during writing will be explained. Processing device 100
According to the write instruction 106 from the buffer storage device 300
operates the address association unit to determine whether data at the corresponding address exists, and if so, updates the contents of the data storage unit 303. If it does not exist, writing of day and evening is not performed. Of course, it is also possible to modify it by writing. On the other hand, the write instruction 106 is passed directly to the main memory device 200, and a write operation is immediately performed. When the write operation ends normally, the main storage device 200 outputs a memory completion report (No. 5 203), and in response, the buffer storage device 300 outputs a transfer completion report signal 107.
Output.

Next, the operation of the buffer storage device 300 in the failure diagnosis mode will be described. The control signal 400 is a signal for specifying the operation mode from the test control circuit 500, and by asserting this signal, the failure diagnosis mode is set. When the microprocessor 100 executes a program and sends an address 101 and a read request 105 to perform a memory fetch, the address association unit 301 operates in response to the read request 105, and the address of the data requested by the microprocessor 100 is If it exists in the address associative unit 301, the address associative unit 301 asserts a Hit signal 302.

However, the HjL signal 302 is suppressed by the AND circuit 401 due to the inverted signal of the asserted control signal 400. The negative output of the AND gate 401 is the inverter 310
is input to the AND gate 311, and the read request 3
20 is sent to the main storage device 200 and instructs the main storage device 200 to perform a fetch operation. multiplexer 305
is applied from main memory device 200 to data bus 201 and line 203 in response to the negated output of AND gate 401. Read data and read completion signal (AC
K) on data bus 102 and line 107, respectively, for transfer to microprocessor 100. Microprocessor 100 receives data on data bus 102 and executes secondary instructions in response to the ACK signal on line 107.

On the other hand, the buffer storage device 200 reads data corresponding to the input address 101 from the data storage section 303, and the comparator 402 compares the data 201 read from the main storage device 200 and the data 303 read from the data storage section 303.
When the address association is Hit in the failure diagnosis mode as described above, if there is a mismatch, the signal 403 is asserted and reported to the external test control circuit 500.

The test control circuit outputs a discrepancy detection signal 4 in the diagnostic mode.
When 03 is asserted, a 9 interrupt request 501 is output to the processing device 100. Therefore, in the failure diagnosis mode, the buffer storage device 300 can be diagnosed for failure while operating the microprocessor 100, and the processing device 100 can receive the result as an interrupt request while executing the program.

On the other hand, as a result of the address search, the microprocessor 100
If the address of the requested data does not exist in the address association section, H is sent as in the normal operation mode.
Since it signal 302 is not asserted, gate 311
, 310 outputs a main memory read instruction 320 to read the contents of the main memory. At this time, the output 304 from the data storage unit 303 is undefined, and the output of the comparator 402 is also undefined, but the AND gate 404
When 02 is negated, the mismatch detection signal 403 is not output.

In addition, a write instruction 106 is issued from the microprocessor 100.
When is issued, even in the failure diagnosis mode, as in the normal operation mode, if the corresponding address exists as a result of searching the address association section 301, the corresponding data in the data storage section 303 is updated. do. Therefore, as long as the data storage unit 303 is operating normally, the internal data should always match the data in the main storage device 200.

Note that in this embodiment, the means for fetching to the main memory regardless of the presence or absence of desired data in the buffer memory is realized by a circuit that negates an assert signal. There are ways to achieve this, such as by adding this function to the circuit that controls it.

〔Effect of the invention〕

As explained above, according to the present invention, by simply adding a diagnostic mode for suppressing a hit signal and a circuit for detecting mismatch between read data, buffer storage devices and associative memories, which were conventionally difficult to diagnose, can be operated in a diagnostic mode. This has the advantage that diagnosis can be easily made by running the program.

Furthermore, when the internal state of the LSI cannot be easily diagnosed, such as with a microprocessor that has a built-in buffer memory on the same LSI, the diagnostic method of the present invention can be applied to diagnose the LSI by running a program in the 1-diagnosis mode. You can perform a self-test.

Furthermore, it is also possible to perform diagnosis during normal operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic computer system using a buffer storage device equipped with a test diagnosis circuit according to the present invention. 100... Processing device, 200... Main storage device. 300...Buffer storage device, 301...Address association unit. 302...Data storage unit, 302...Hit signal. 305...Multiplexer, 400...Diagnostic mode control signal, 401...Hi signal suppression circuit, 402...
...Data comparator, 403...Failure detection output signal.

Claims (1)

[Claims] 1. A main memory device, a buffer memory device for storing a copy of instructions or data on the main memory device, and a buffer memory device for storing a copy of instructions or data on the main memory device; means for sending a read request and a memory address for the main memory output from the processor to both the main memory and the buffer memory to a processor that responds to access and execute a program instruction; A fault diagnosis that compares storage signals read from each of the main storage device and the buffer storage device in response to the read request and the memory address, and outputs the comparison result as a fault diagnosis result of the buffer storage device. A data processing system having means. 2. The failure diagnosis means outputs the failure diagnosis result in response to a hit signal indicating that a storage signal corresponding to the read address is currently stored in the buffer storage device. Data processing system. 3. Item 1, wherein the sending means has means for sending a write request to the main storage device, a memory address, and data to be written, which are output from the processing device, to both the main storage device and the buffer storage device. data processing system. 4. The sending means sends the read request to both the main storage device and the buffer storage device when the signal specifying the failure diagnosis mode is given, and when the signal specifying the failure diagnosis mode is not given. , first sends the read request to the buffer storage device, and if a signal corresponding to the memory address is read to the buffer storage device, sends the read signal to the processing device, and if not read, sends the read request to the processing device. further sends the read request to the main storage device, sends the signal read from the main storage device to the processing device, and
2. The data processing system according to claim 1, wherein the data processing system stores data in the buffer storage device. 5. The sending means includes first means for first sending the read request and the memory address to the buffer storage device, and whether a failure diagnosis mode signal and a storage signal for the memory address are stored in the buffer storage device. When a hit signal indicating whether the hit signal is input or not is input and the failure diagnosis mode signal is given, the read request is transferred to the main storage device regardless of whether the hit signal is given, and the hit signal is When the hit signal is not given, the signal read from the main memory is stored in the buffer storage, and when the failure diagnosis mode is not given, the read request is sent to the main memory only when the hit signal is not given. 4. The data processing system of clause 4, which is means for sending data to a storage device. 6. The processing device is connected to means for generating an interrupt signal in response to the failure diagnosis result, and has means for executing an exception handling routine for dealing with a failure of the buffer storage device in response to the interrupt signal. The data processing system of Section 1.