JPS61213937A - Tracing system for information processing system - Google Patents

Abstract

PURPOSE:To eliminate the need to interrupt a program by monitoring addresses of instructions which are executed successively, and storing the operand addressed of instructions in a trace information storage area when finding that the instructions are in a trace area. CONSTITUTION:A specifying means 78 specifies a trace gathering range by a trace head address register 7 and a trace end address register 8. A trace area detecting means 9' detects whether the address of a program counter 5 which is executed currently is within the trace range and a control means 10' stores the address of an operand in an instruction register 3 in the trace information storage area 15 of the memory 2 when the executed instruction is for operand access while its address is within the trace gathering range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This is a tracing method that obtains and records addresses of operands accessed during instruction execution without interrupting instruction execution.

[Industrial application field]

The present invention relates to a tracing method for collecting trace information during program execution used for program debugging and fault diagnosis in an information processing system such as a computer system.

Recent computers are equipped with a trace function that collects trace information indicating the operation history during program execution for use as diagnostic data for program debugging and the like.

[Conventional technology]

Conventional trace information collection methods mainly collect the fetch address of executed instructions, but this alone is not sufficient information for debugging, as it is unclear whether or not the operand was actually accessed. There are many cases. For this reason, addresses of operands used during instruction execution are often collected at the same time.

FIG. 5 schematically shows a conventional tracing method for collecting traces of operand accesses. In this method, an area for collecting trace information is set in the main memory, and when this area is accessed, its address is collected. In fig.

21 is a main memory, 22 is a trace setting area 123 is a trace information storage area, 24 is an execution program in the CPU,
25.26 is the operand address.

27 represents a trace information collection program.

Operand access trace information is collected from main memory 2.
The trace setting area 22 on top of 1 is monitored.

Executed automatically when this area is accessed. For example, assume that an instruction in the execution program 24 makes an access request at operand addresses 25 and 26 shown in FIG. 2 to fetch or store an operand. In this case, since operand addresses 25 and 26 are within the trace setting area 22, they are detected when each memory access is executed and two interrupts are generated.

The trace information collection program 27 is called for this interrupt processing. Trace information collection program 2
7 stores the operand address etc. in the address register in the trace information storage area 23 and returns control to the execution program 24.

In this way, an interrupt is generated every time the inside of the trace setting area 22 is accessed, the address thereof is stored in the trace information storage area 23, and trace information is outputted by giving an instruction at a necessary time.

[Problem that the invention seeks to solve]

In the conventional technology, as shown in FIG.
When U performs an operand fetch or operand store, an interrupt is generated and trace information is collected by software.

Such interrupts adversely affect the processing power of the system. In particular, if the entire memory area is set as the trace setting area, the running of the program will be significantly delayed, so it cannot be used in an operating system unless the trace range is limited. However, when the trace range is limited, there is a drawback that the trace information becomes incomplete.

The present invention is intended to solve this drawback, and aims to make it possible to collect trace information without interrupting the execution program.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. The present invention
Basically, the specification means 78 for specifying the trace collection range
, trace start address register 7 and trace end address register 8.

means 9' for detecting whether the address of the execution instruction is within the trace range; and means 9' for detecting whether the address of the execution instruction is within the trace collection range; and a control means 10' for storing the information.

To detect the trace area, the detecting means 9' compares and detects whether the address of the program counter 5 being executed is within the trace collection range.

Further, the trace information collection control means 10' operates according to the settings of the register 6 for setting the trace collection mode.

In this way, the address of the operand (OP) of the instruction register 3 is stored in the trace information storage area 15 of the memory 2.

[Effect]

According to the configuration of the present invention, instructions are executed sequentially and in parallel according to the address of the program counter 5, and the addresses are monitored, and when it is found that the address is within the trace area, the operand address of the instruction is transferred to the trace information. Since the information can be stored in the storage area, there is no need for processing control such as calling a trace information collection program using an interrupt or the like.

〔Example〕

FIG. 2 is a configuration diagram of a system 1 according to an embodiment of the present invention.

In FIG. 2, the same reference numerals as in FIG. 1 indicate the same objects; 1 is a CPU, 2 is a main memory, 3 is an instruction register, 4 is an instruction decoder, 5 is a program counter, and 6 is a trace mode display register.

7 is a trace start address register, 8 is a trace end address register, 9 is a trace area detection circuit, 10 is a trace information collection control circuit, 11 is a trace information storage area pointer register, 12 is an arithmetic Unison I-ALU, 1
3 represents a memory address register, 14 a buffer register, and 15 an operand trace information storage area.

To collect trace information for operand access, set the operand trace collection mode (
This is executed by setting "l"). The trace information collection control circuit 10 is activated by the operand trace mode of the trace mode display register 6.

Operand access trace information is collected from main memory 2.
Store instruction (S) in the trace collection area set above
This is done by recording the operand address when the load instruction (T) or load instruction (L) is executed.

The instruction fetched into instruction register 3 is a store instruction (S
T) or load instruction (L), it is detected by the instruction decoder 4 and the trace information collection control circuit 10
will be notified.

The start address and end address of the trace collection area on the main memory are set in the trace start address register 7 and the trace end address register 8, respectively.

The trace area detection circuit 9 compares the actual execution instruction address of the program counter 5 with the start address and the final address of the register 7.8, and when it detects that the actual execution instruction is within the trace collection area, trace information collection is started. The control circuit 10 is notified.

Operand area of instruction register 3 and program counter 5. Address data such as pace registers, index registers, and pointer registers can be selectively input to the input section of the arithmetic unit 12, and execution addresses such as instruction fetch addresses and operand addresses can be input to address operations as needed. is generated,
It is output from the arithmetic unit 12 to the memory address register 3.

When the trace information collection control circuit 10 detects the operand access timing of a store instruction (ST) or load instruction (L) in the trace collection area, it copies the operand address of the memory address register 3 to another control register, and After the access is completed, the operand address is stored at the address indicated by trace information storage area pointer register 1.

The value of the trace information storage area pointer register is:

It is counted up by 1 each time it is used as an address, and is counted up by 1 each time it is used as an address.
5 sequential storage positions.

In this way, the operand trace information storage area 15
The trace information on operand accesses collected is read out via the buffer register 14 and output to a printer or display in accordance with instructions, as in the past.

FIG. 3 shows an example of the control operation of the embodiment system shown in FIG.

In the illustrated example, addresses a10000'' and “100FF” of the main memory 2 are set as the start and end addresses of the trace collection area,
Store instruction (ST) and load instruction (L) among these.

When ST RO/H (100) ST R1/H (104) ST R2/H (102) is executed, each operand address "1"
00'', ``104'', and ``102'' are collected in the operand trace information storage area 15 and output as a link.

FIG. 4 shows an example of control operation according to another embodiment of the present invention.

The difference between FIG. 4 and FIG. 3 is that in the case of FIG. 4, a zone trace function is added that collects the instruction execution address history without interrupting instruction execution, and it works in conjunction with the operand access trace function. This is what they were made to do.

In FIG. 4, the trace mode display register 6.

The operating status of the system can be changed to the above zone trace mode (“1”).
”) and operand access trace mode (P1”)
) is set. Further, values specifying a common trace range are set in the trace start address register 7 and the trace end address register 8.

A zone trace information storage area 16 is provided on the main memory 2 in addition to the operand trace information storage area 15 for operand access, and the trace information storage area pointer register 11 is used to point to these two trace information storage areas. Switched to and shared.

A buffer register 17 is also provided to take out trace information from the zone trace information storage area I6.

Before starting the operation, first of all.

(2) Initialize the trace information storage area pointer register 11 so that address information is stored from the beginning of both trace information storage areas 15 and 16.

(2) Set the start address of the trace range in the trace start address register 7 and the end address of the trace range in the trace end address register 8.

■ Set the trace mode display register 6 so that the system operates in both zone trace and operand access trace modes.

With the above operations, when an instruction in the specified trace range is executed, the instruction execution address and operand access address are continuously updated to the zone trace information storage area 16 and the operand trace information storage area 16, respectively, without interrupting instruction execution. The contents of the trace information storage area pointer register 11 are stored in the area 15 as an address (the base address is specified separately).

Note that when the trace information storage area is exceeded, the data is stored again from the beginning.

In addition, secondary measures are taken when collecting operand addresses so that the contents of the zone trace information storage area correspond to the contents of the operand trace information storage area. That is, when an instruction that does not perform operand access, such as an inter-register transfer instruction or a jump instruction, is executed, invalid data display is set in the operand trace information storage area 15, and when an instruction that performs operand access is executed.

Set valid data display. These are indicated by flags 15a in FIG.

Next, the one-car trace information is displayed as follows.

■ Set the address of the trace information storage area to be read in the trace information storage area pointer register 11.

(2) The instruction execution address in the trace information is read into the buffer register 17, and the operand access address is read into the buffer register 14.

Read the contents of the two-car trace information storage area by repeating the above procedure ①. Note that if invalid data is displayed in the read operand access address, the read value is not output, and only when valid data is displayed, the operand access address is added to the simultaneously read instruction execution address and displayed.

In this embodiment, since the instruction execution address and operand access address are displayed in correspondence, it is possible to easily check the program that accessed specific data.
This is particularly effective in diagnosing data corruption.

Note that although the present invention can be implemented as a complete hardware configuration using logic circuits, it can also be implemented using firmware based on a microprogram.

〔Effect of the invention〕

According to the present invention, the history of operand addresses accessed by instruction execution can be collected at high speed without interrupting instruction execution by a single interrupt, even in an operating system.

This trace information has the advantage of being able to investigate program buffers and the like.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, and Figure 2 is a block diagram of the principle of the present invention.
FIG. 3 is an explanatory diagram of a control operation example of the embodiment system shown in FIG. 1; FIG. FIG. 4 is an explanatory diagram of an example of control operation of another embodiment system, and FIG. 5 is an explanatory diagram of a conventional tracing method. 1 is the CPU, 2 is the main memory, and 3 is the instruction register. 5 is a program counter, 6 is a trace mode display register, and 7 is a trace start address register. Reference numeral 8 represents a trace final address register, 9 represents a tray large area detection circuit, 10 represents a trace information collection control circuit, 11 represents a trace information storage area pointer register, and 15 represents an operand trace information storage area.

Claims (1)

[Claims] In a computer system having a trace function, a specification means (78) for specifying a trace collection range on main memory.
a detection means (9') for detecting whether the address of the execution instruction is within the trace collection range; and when it is detected that the address of the execution instruction is within the trace collection range;
If the execution instruction performs operand access, its address is stored in the trace information storage area (1
5) A tracing method for an information processing system, characterized in that the tracing method comprises a control means (10') for storing operand accesses as trace information without interrupting execution instructions.