JPS6122814B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to an information processing device including an operator console and an interface control circuit.

In order to interact with the system manually, a general information processing device inputs a supply signal that is generated in response to command information and consists of a mode instruction signal and an input data signal, so a keyboard device and a central processing unit for the supply signal are input/output. It includes an operator console consisting of a control device and a display device that displays response signals from the main memory device, and has the following functions.

A system initialization function that initializes all devices in the system (central processing unit, input/output control unit, main memory, system interface control circuit).

A function to set the device number and channel number of the input/output control unit on the keyboard, specify the central processing unit number, and load the initial program.

A function to set system configuration control information to the central processing unit, input/output control unit, and main storage device, or to display it on the operator console.

External interrupt function to central processing unit.

Central processing unit, input/output control unit failure status,
Function to display status information such as program monitoring.

In order to realize the above functions, the supply signal is transferred in a timely manner to a response fulfillment device such as a central processing unit and an input/output control unit, and a main storage device, and a response signal is returned.

There is also a main memory access control circuit for controlling reading and writing of general main memory from the central processing unit and the input/output control unit.

In order to achieve the functions described above, conventional information processing devices transmit supply signals consisting of mode instruction signals and input data signals generated in response to command information between a central processing unit, an input/output control device, and a main storage device. An operation console that outputs the response signal to a separately provided system interface line and displays the response signal, and a console that receives the supply signal through the system interface line, processes the input data signal using the mode instruction signal, and generates the response signal. A response fulfillment device that sends data back to the operation console via a system interface line, and a memory interface line that is included as a circuit in the response fulfillment device or is independent as a device and is connected from the response fulfillment device to the main storage device. It also included a main memory access control circuit that controlled reading and writing of the main memory.

This configuration has the disadvantage that the number of system interface lines connected from the operator console to each device and the number of driver and receiver circuits associated with the lines are large, which increases the cost of the device.

An object of the present invention is to provide an information processing device in which the amount of hardware is reduced by reducing the number of system interface wires and the driver and receiver circuits attached thereto.

The information processing device of the present invention outputs a supply signal consisting of a mode instruction signal and an input data signal generated in response to command information to only one set of system interface lines, and displays a response signal supplied from the line. and the supply signal transmitted between the response execution determination circuit that outputs the activation signal to the activation signal line selected in response to the mode instruction signal and the operation console via the system interface line. a system interface control device including a main memory access control circuit for controlling transmission and reception of response signals and control for reading and writing of the main memory; and when receiving the activation signal via the activation signal line, the main storage access control circuit; and receives the supply signal via a memory interface line provided between the main memory access control circuit and the main memory access control circuit in order to transfer information to and from the main memory, and receives the supply signal according to the mode instruction signal. and a response implementation device that processes an input data signal, generates the response signal, and returns the response signal via the memory interface line.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention.

Reference numeral 1 denotes an operation console, which includes a keyboard device for interacting with the system, and a display device for displaying response signals for configuration control and the like.

The system interface control device 2 includes a central processing unit 3, an input/output control device 4, and a main storage device 5 including a system interface line b, a system interface line c, a memory system interface line d,
The operator console 1 has an interface via a system interface line a, and collectively controls the system configuration and the interface between the main memory access devices.

FIG. 2 is a block diagram showing the system interface control device shown in FIG. 1.

The system interface line a in FIG. 1 is connected to system interface lines 106 and 107 in this figure.
The system interface line b is divided into a signal line 100 and a memory interface line 102, the system interface line c is divided into a signal line 101 and a memory interface line 103, and the memory interface line d is equivalent to 104.

The operation code reception register 8 receives an operation instruction signal, which is a coded supply signal, from the operator console 1 via the system interface line 106.
The output 8' of the operation code reception register 8 is input to one input of the two-input selection circuit 13.

A signal from the maintenance diagnosis control device 15 is input to the other input of the two-input selection circuit 13. The output of the two-input selection circuit 13 is addressed to the decoder 6.

The decoder 6 is a decoder that discriminates between the central processing unit 3 and the input/output control unit 4, which are response devices to the operator console 1, according to the operation instruction signal from the operator console 1, and its output is input to the output holding register 7. .

The outputs of the output holding registers 7 are connected to the signal line 1, respectively.
An index request is made to the firmware of the central processing unit 3 and input/output control unit 4 via 00 and 101.

The main memory access control circuit 12 controls read/write requests from the central processing unit 3 and the input/output control unit 4 to the main memory. Memory interface lines, which are interface lines between the main memory device access control circuit 12, the central processing unit 3, the input/output control device 4, and the main memory device 5, are 102 and 1, respectively.
03,104.

A response code sending register 9 sends a response code signal to the console 1, and returns the response code to the console 1 via the system interface line 107.

Reference numeral 10 is a system status display register that displays system status such as failure status of each device.

Reference numeral 11 is a mode display register for displaying modes such as multiprocessing mode.

The main memory access control circuit 12 includes firmware of the central processing unit 3 and input/output control unit 4, an operation code reception register 8 in the system interface control unit 2, a response code transmission register 9,
Controls read or write operations of system status display register 10 and mode control register 11. Reading and writing operations to the operation code reception register 8, response code transmission register 9, system status display register 10, and mode control register 11 are performed by the memory interface line 102 to the main memory.
103 and is controlled as an additional function for read/write requests to the main memory. Operation code reception register 8, response code transmission register 9,
To read the system status display register 10 and mode control register 11, the output of the 4-input selection circuit 14 that selects the 4 outputs of the register is connected to the signal line 10.
8 to the central processing unit 3 or input/output control unit 4 under the control of the main memory access control circuit 12.
This is done by transferring the information to Writing to the operation code reception register 8, response code transmission register 9, system status display register 10, and mode control register 11 is performed via the signal line 109 under the control of the main memory access control circuit 12, and the write data is sent to the four registers. This is done by writing to any one of 8, 9, 10, and 11.

Next, the operation will be explained with reference to the time chart shown in FIG. 3 from the operation instruction from the operation console 1 to the time when a response is returned.

When the operation instruction signal 106' from the operation console 1 or the system interface control signal 2 is sent to the system interface control signal 2 via the system interface line a at timing t1, the operation code reception register of the system interface control device 2 is sent from the system interface line 106. 8, and the operation code 8' is held. The operation instruction signal 106' encodes various functions such as an initial program load function, an external interrupt function, settings for configuration control information of each device, a display function, and a function to display status information of each device, and is a mode instruction signal. input data signal.

At timing t2, the two-input selection circuit outputs the access signal 13' to the decoder 6, and the decoder 6 is accessed. The decoder 6 receives the mode instruction signal from the operation code receiving register 8, analyzes the signal, determines the device that will respond to the operator console 1, and outputs the signal to the output holding register 7.

At timing t3, the output of the output holding register 7 is transferred to the signal line 10 according to the analysis result of the decoder 6.
0 and 101, respectively, to the firmware of the central processing unit 3 or the input/output control unit 4. In this example, a case will be explained in which an indexing request is issued to the central processing unit 3, but when an indexing request is issued to the input/output control unit 4, the same procedure is followed. Since the index reception of the firmware of the central processing unit 3 is performed when the command of the central processing unit is completed, it is awaited until the end of the command.

When the index is accepted at timing tm, the central processing unit outputs an index request acceptance signal 200.
The main memory access control circuit 12 is operated via the memory interface line 102, and the 4-input selection circuit 1
4 and signal line 108 to read out the operation code 8'. The firmware of the central processing unit determines the mode instruction signal, determines the operation content, and shifts to a cycle of creating a code at timing t(m+1). After creating the response code, the main memory access control circuit 12 is operated via the memory interface line 102, and a request to write the response code to the response code sending register 9 is sent out via the signal line 109 at timing tn. timing t(n
+1), a response code 107' is returned to the console 1 via the system interface line 107.

The first effect of this embodiment is that by encoding supply signals and response signals, the number of system interface lines between the operator console and the system control device and the number of associated driver and receiver circuits can be reduced. This is something that can be reduced.

The second advantage of this embodiment is that by changing the firmware information of the central processing unit and input/output control unit, it is possible to easily add or change functions to the operator console.

A third advantage of this embodiment is that by configuring the decoder with a rewritable memory, it is possible to easily add or change functions to the operator console.

The information processing device of the present invention integrates the system interface control circuit and the main memory access control circuit as a device instead of equipping each part with the system interface control circuit and the main memory access control circuit, and connects the device and the console with a set of interface wires. By configuring so that the main memory read/write line can generally be used for communication with the response execution device, there is an effect that the number of interface lines and associated driver and receiver circuits can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram including an embodiment of the present invention;
FIG. 2 is a block diagram showing the system interface control device shown in FIG. 1, and FIG. 3 is a time chart illustrating the operation of the embodiment shown in FIGS. 1 and 2. DESCRIPTION OF SYMBOLS 1... Operation console, 2... System interface control device, 3... Central processing unit, 4... Input/output control device, 5... Main storage device, 6... Decoder, 7
...Output holding register, 8...Operation code reception register, 9...Response code transmission register, 10...
...System status display register, 11...Mode display register, 12...Main storage access control circuit, 13...2 input selection circuit, 14...4 input selection circuit, 15...Maintenance diagnosis control device, 100,1
01, 108, 109...Signal line, d, 102,
103, 104...Memory interface line, 1
05...Diagnostic control signal line, a, b, c, 106,
107...System interface line, t...1
Machine cycle, 106'...operation instruction signal, t
1, t2, t3, t4, tm+t(m+1), t
(m+2), tn, t(n+1)...timing,
8'...Operation code, 13'...Access signal, 1
00'... Index request signal to central processing unit, 1
07'...Response code, 200...Identification request acceptance signal, 300...Response code creation signal.

Claims (1)

[Claims] 1. A console that outputs a supply signal consisting of a mode instruction signal and an input data signal generated in response to command information to only one set of system interface lines and displays a response signal supplied from the line, and the mode instruction signal. a response execution determination circuit that outputs a startup signal to a startup signal line selected in accordance with the system interface line, and control of exchange of the supply signal and the response signal between the operation console and the system interface line; A system interface control device including a main memory access control circuit that performs read/write control of the main memory, and the main memory access control circuit and the main memory when the activation signal is received via the activation signal line. receives the supply signal via a memory interface line provided between the main memory access control circuit and the main memory access control circuit in order to transfer information to and from the main memory access control circuit, and processes the input data signal according to the mode instruction signal. and a response fulfillment device that generates the response signal and sends it back via the memory interface line.