JPH05134971A - Computer device - Google Patents

Abstract

PURPOSE:To perform transfer between main memory and a resist and an arithmetic operation between the resists by a CPU even while a DMA controller performs DMA transfer. CONSTITUTION:When the DMA transfer is performed, the CPU 2 delivers a transfer address to the DMA controller 8 via a shared bus 1 first. The transfer address designates the address of buffer memory 5, not that of the main memory 4. Thence, the DMA controller 8, etc., is started up by delivering a series of commands from the CPU 2 to the DMA controller 8, and switching so as to connect a DMA pass selector 7 to a memory pass selector 6 is performed. The DMA controller 8 transfers received data as increasing or decreasing the number of transfer addresses. The memory pass selector 6 decodes part of received transfer addresses, and write is performed by automatically selecting the buffer memory 5.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a computer device.

[0002]

2. Description of the Related Art Conventionally, in a system in which a CPU (central processing unit), a DMA (direct memory access) device, a memory and the like are connected by a bus, a bus master (a device capable of controlling the bus.
The U and DMA devices correspond to this), and the bus arbiter receives the request and arbitrates the bus access for processing. For example, in a system that includes an Ethernet (Ethernet) controller and a SCSI controller, these controllers are connected to a shared bus via a DMA controller. Data transfer with the Ethernet and SCSI controllers is performed as follows.

First, the CPU sends a series of commands and transfer addresses to the DMA controller to activate it.
The DMA controller sends a bus request signal to the bus arbiter, acquires the bus, and then transfers data between the Ethernet or SCSI controller and the memory. This method allows the CPU to continue processing while these controllers are transferring data.
As described above, according to the conventional technique, the CPU can continue the processing while the Ethernet controller or the SCSI controller is accessing the memory. However, this processing is performed by register-register transfer, operation on the accumulator, and the like.
The processing is limited to the processing inside the PU, and the processing requiring memory access is made to wait until the DMA transfer is completed.

[0004]

[Object] The present invention has been made in view of the above-mentioned circumstances, and makes it possible to access any data other than the data being operated in the DMA transfer while the DMA transfer is being performed, thereby improving reliability and expandability. It is made for the purpose of providing a computer device having a high memory system.

[0005]

In order to achieve the above object, the present invention provides (1)
Shared bus, CPU connected to the shared bus, and I / O
In a computer device including a device, a DMA device, and a memory, a buffer memory for the DMA transfer data, a memory path selector that determines a path for memory access from the shared bus, and the DMA to or from the DMA And a DMA path selector that determines the data of the above, and enables parallel operation with the CPU by performing the DMA transfer not to the main memory but to the buffer memory. Divided into blocks, enabling parallel operation for access to the buffer memory, and (3) above (2)
In the above, in each of the memory blocks, a selector is provided to simplify the memory path selector and provide expandability. Hereinafter, description will be given based on examples of the present invention.

FIG. 1 is a block diagram for explaining an embodiment of a computer device according to the present invention. In the figure, 1 is a shared bus, 2 is a CPU (central processing unit), and 3 is an I / O (input / output). (Device), 4 is a main memory, 5 is a buffer memory, 6 is a memory bus selector, 7 is a DMA (direct memory access) bus selector, and 8 is a DMA controller.

The memory selector 6 is a shared bus 1 or D.
This circuit receives an access address and access data from the MA bus selector 7, decodes a part of the access address to select either the main memory 4 or the buffer memory 5, and supplies the remaining addresses and data. The DMA bus selector 7 is a CPU
2 from the shared bus 1 to access D
This is a circuit that functions as a switch for changing the access address and access data flow path used by the DMA controller 8 at the time of MA transfer to make either the shared bus 1 or the memory bus selector 6. In addition, DM
A (direct memory access) is a function in which an external device directly accesses a memory without going through a microprocessor (MPU).

First, claim 1 will be described. In the initial state, the DMA path selector 7 is connected to the shared bus 1. First, the case of sending data from the DMA to the memory will be described. When performing DMA transfer, first
U2 passes the transfer address to the DMA controller 8 via the shared bus 1. At this time, the transfer address is not the main memory 4 but the buffer memory 5 address.
Next, a series of commands are passed from the CPU 2 to the DMA controller 8 and the DMA controller 8 and the Ethere
The t controller or the SCSI controller is activated, and the DMA path selector 7 is switched to be connected to the memory path selector 6. DMA controller 8 is Etherne
t Transfer the data received from the controller or SCSI controller while increasing or decreasing the transfer address. The memory path selector 6 decodes a part of the received transfer address, whereby the buffer memory 5 is automatically selected and writing is performed.

When data is transferred from the memory to the DMA controller side, the system allocates addresses so that the buffer memory 5 has a buffer for storing the transfer data in advance. After that, the DMA controller 8 is activated in the same manner as described above to transfer data.
Send to Ethernet controller or SCSI controller. In either case, while DMA transfer is being performed,
Since the shared bus 1 is free, the CPU 2 has the main memory 4
Alternatively, other I / O devices can be freely accessed without waiting time.

FIG. 2 is a diagram showing another embodiment (claim 2) of the computer apparatus according to the present invention, in which 5a to 5n are shown.
Is a buffer memory, and other parts having the same functions as those in FIG. 1 are denoted by the same reference numerals. According to the embodiment of FIG.
There is an advantage that the CPU 2 can access other devices while performing the DMA transfer. However, with this method, for example, the data transferred by DMA is transferred to the CPU.
2 while it is reading the DMA transfer data
While writing to the buffer memory 5, the next DMA transfer cannot be performed. Conversely, during DMA transfer, the CPU
Neither can the buffer 2 access the buffer 5 to read the data by the previous DMA transfer or write the data for the next DMA transfer to the buffer memory 5. Therefore, the buffer memory 5 is divided into a plurality of blocks, and the buffer memory block 5a for performing DMA transfer.
If 5n is a block different from the block used in the previous DMA transfer, the above-mentioned parallel operation becomes possible. In this case, the memory path selector 6 can be regarded as a two-circuit, multi-contact switch that decodes an input address, selects one of a plurality of memory blocks, and switches the bus.

FIG. 3 is a diagram showing the memory path selector in FIG. 2, in which 11a to 11c are buffer memory blocks and 12a and 12b are decoders. According to the embodiment shown in FIG. 2, the CPU and the DMA can operate in parallel except when the same buffer block is simultaneously accessed, and the processing can be performed at high speed. However, as described above, since the memory path selector has to simultaneously switch the buses that are a set of a plurality of signal lines, the circuit is complicated and is likely to cause a malfunction. Moreover, the circuit must be changed so that the buffer memory block can be accessed. Therefore, the system configuration cannot be changed flexibly. Therefore, the memory path selector is changed as shown in FIG. Selector 1 for each memory block
3a to 13c decode a part of the input address to determine whether the block is being accessed, and output the address, data and enable signals to the memory. An arbiter is provided in the selector to prevent access to the other while one is accessing.

[0012]

As is apparent from the above description, the present invention has the following effects. (1) According to claim 1, the DMA controller is DM
While the A transfer is being performed, the CPU can perform the transfer between the main memory and the registers, the operation between the registers, etc., and the processing speed becomes high. (2) According to claim 2, the DMA controller is DM
Even during the A transfer, the CPU can access the buffer memory if it is not in the same buffer memory block, so that higher speed processing is possible. (3) According to the third aspect, it is possible to construct a highly reliable system with few malfunctions by simplifying the circuit of the memory path selector. Further, since the buffer memory can be easily added, a flexible system with high expandability can be constructed.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a computer device according to the present invention.

FIG. 2 is a configuration diagram for explaining another embodiment of the computer device according to the present invention.

FIG. 3 is a diagram showing a memory path selector in FIG.

FIG. 4 is a diagram showing another memory path selector.

[Explanation of symbols]

1 ... Shared bus, 2 ... CPU (central processing unit), 3 ... I /
O (input / output device), 4 ... Main memory, 5 ... Buffer memory, 6 ... Memory bus selector, 7 ... DMA (Direct Memory Access) bus selector, 8 ... DMA controller.

Claims (3)

[Claims] 1. A shared bus and a C connected to the shared bus
In a computer device including a PU, an I / O device, a DMA device, and a memory, a buffer memory for the DMA transfer data, a memory path selector that determines a path for memory access from the shared bus, A computer device having a DMA path selector for determining data from or to the DMA and enabling parallel operation with a CPU by performing DMA transfer not to a main memory but to a buffer memory. .. 2. The computer apparatus according to claim 1, wherein the buffer memory is divided into a plurality of blocks, and parallel operations can be performed even when accessing the buffer memory. 3. The computer apparatus according to claim 2, wherein a memory path selector is simplified and provided with expandability by providing a selector in each of the memory blocks.