JPS61225871A - Manufacture of semiconductor memory device - Google Patents
Manufacture of semiconductor memory deviceInfo
- Publication number
- JPS61225871A JPS61225871A JP6692685A JP6692685A JPS61225871A JP S61225871 A JPS61225871 A JP S61225871A JP 6692685 A JP6692685 A JP 6692685A JP 6692685 A JP6692685 A JP 6692685A JP S61225871 A JPS61225871 A JP S61225871A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon film
- silicon nitride
- polysilicon
- accumulated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims description 10
- 239000007800 oxidant agent Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 43
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000004678 hydrides Chemical class 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はＥＰＲＯＭ （紫外線消去型ＦＲＯＭ ）とし
て適する半導体記憶装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor memory device suitable as an EPROM (ultraviolet erasable FROM).
一般に、ＥＰＲＯＭセルのフローティングｆ−）とコン
トロールゲート間の眉間絶縁は、７０−ティングゲート
となるポリシリコン膜の表面領域を酸化し、ポリシリコ
ン酸化膜を形成することによシなされている。ところで
近時、ＥＰＲＯＭデバイスの大容量化と共に高速書き込
みが要求されるため、ＥＰＲＯＭセルの７０−ティング
ゲートとコントロールゲート間の眉間絶縁膜としてのポ
リシリコン酸化膜の薄膜が必須である。しかしながら３
００Ｘ以下の膜厚では、ポリシリコン酸化膜の耐圧がピ
ンホール等が原因で劣化し、フローティングゲートにお
けるデータ保持が難しくなるものである。In general, glabellar insulation between the floating f-) and control gate of an EPROM cell is achieved by oxidizing the surface region of a polysilicon film that will become a 70-ring gate to form a polysilicon oxide film. Nowadays, as the capacity of EPROM devices increases and high-speed writing is required, a thin polysilicon oxide film is essential as an insulating film between the glabella between the 70-ring gate and the control gate of the EPROM cell. However, 3
If the film thickness is less than 00X, the withstand voltage of the polysilicon oxide film deteriorates due to pinholes and the like, making it difficult to retain data in the floating gate.
本発明は上記実情に鑑みてなされたもので、信頼性の高
い層間絶縁膜が形成できる半導体記憶装置（特にＥＰＲ
ＯＭセル）の製造方法を提供しようとするものである。The present invention has been made in view of the above-mentioned circumstances, and is a semiconductor memory device (particularly an EPR
This paper aims to provide a manufacturing method for OM cells.
本発明は、第１のポリシリコン膜（フローティングゲー
ト）上に、例えばＬＰＣＶＤ （Ｌｏｗ Ｐｒｅｓｓｕ
ｒｅＣｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉ
ｏｎ ）法によりシリコン窒化膜を堆積し、酸素雰囲気
中で熱処理を行なうことにより、上記シリコン窒化膜を
すべて酸化性物質に変換することＫよってなされる。In the present invention, for example, LPCVD (Low Pressure
reChemical Vapor Deposit
On), a silicon nitride film is deposited by the method, and the silicon nitride film is completely converted into an oxidizing substance by performing heat treatment in an oxygen atmosphere.
上記ＬＰＣＶＤ法によるシリコン窒化膜は、３００Ｘ以
下の薄膜領域でも耐圧が良好である。しかしながらシリ
コン窒化膜は、電子に対するバリヤハイドが酸化膜に比
べて低やため、ＥＰＲＯＭセルに適用する場合には、酸
素雰囲気中で熱処理を行ない、上記シリコン窒化膜を酸
化性物質に変換する必要がある。この方法により、良好
な耐圧、電子に対する充分なバリヤハイド、更にトラッ
プ密度が問題とならない大容量ＥＰＲＯＭデバイスに適
した層間絶縁膜が可能となる。The silicon nitride film produced by the LPCVD method has good breakdown voltage even in the thin film region of 300X or less. However, silicon nitride film has a lower barrier hydride for electrons than oxide film, so when it is applied to EPROM cells, it is necessary to perform heat treatment in an oxygen atmosphere to convert the silicon nitride film into an oxidizing substance. . This method makes it possible to create an interlayer insulating film that has good breakdown voltage, sufficient barrier hydride for electrons, and is suitable for large-capacity EPROM devices in which trap density is not a problem.
以下本発明の一実施例を、第１図に示す製造工程断面図
に従がって説明する。まず第１図（、）の如く１０〜２
０Ω傭のＰ型シリコン基板１上に２００ Ｘのｙ−ト酸
化膜２を形成し、厚さ０．４μｍの７０−テインググー
トとなる第１のプリシリコン膜３を堆積し、これにｐａ
ｃｔ３を拡散源としてＰをドープする。続いてＬＰＣＶ
Ｄ法にょシ厚さ１８０Ｘのシリコン窒化膜４を堆積する
。次に第１図（ｂ）に示す如＜、９５０℃にてウェット
酸素雰囲気中で熱処理を行なうことにより、窒化膜４を
すべて酸化性物質５に変換する。この結果、等制約に厚
さ３００Ｘの酸化膜が形成されたことになる。その後、
厚さ０．４μｍのコントロールゲートとなる第２のプリ
シリコン膜６を堆積し、同様の方法によ、６ｐをドーグ
する。次に第１図（、）の如く、第２のポリシリコン膜
６上に部分的にレジスト膜７を設け、ＲＩＥ（Ｒｅａａ
ｔｌｖｅ ＩｏｎＥｔｃｈｉｎｇ ）法により第２のポ
リシリコン膜６、酸化性物質５、第１のポリシリコン膜
３、ゲート酸化膜２を順次エツチング除去する。次に第
１図（ｄ）に示す如くレジスト膜７を除去した後、Ａ８
を５０ ｋ＊Ｖにて５ Ｘ １０１５備−２イオン注入
する。An embodiment of the present invention will be described below with reference to the manufacturing process cross-sectional diagrams shown in FIG. First, as shown in Figure 1 (,), 10-2
A 200X Y-type oxide film 2 is formed on a 0Ω P-type silicon substrate 1, and a first pre-silicon film 3 having a thickness of 0.4 μm and a 70-TEG is deposited.
P is doped using ct3 as a diffusion source. Then LPCV
A silicon nitride film 4 having a thickness of 180× is deposited using method D. Next, as shown in FIG. 1(b), all of the nitride film 4 is converted into an oxidizing substance 5 by performing heat treatment at 950° C. in a wet oxygen atmosphere. As a result, an oxide film with a thickness of 300× was formed under equal constraints. after that,
A second pre-silicon film 6 having a thickness of 0.4 μm and serving as a control gate is deposited, and 6p is doped using the same method. Next, as shown in FIG. 1(,), a resist film 7 is partially provided on the second polysilicon film 6, and RIE
The second polysilicon film 6, the oxidizing substance 5, the first polysilicon film 3, and the gate oxide film 2 are sequentially etched and removed using a tlve ion etching method. Next, as shown in FIG. 1(d), after removing the resist film 7,
5×1015-2 ions are implanted at 50 k*V.
続いて酸素雰囲気中にて９５０’Ｃで２０分間熱処理を
行なうことにより、露出しているシリコン基板、ポリシ
リコン表面領域に酸化膜８を形成する。これと同時に１
型ソース、ドレイン領域９．１０が形成される。次に第
１図（、）に示す如く、厚さ０．５μｍのＣＶＤ酸化膜
１１を堆積し、ＲＩＥ法によシコンタクト孔を設け、厚
さ１μｍのＡｔ−８ｔ膜を堆積し、パターニングしてソ
ース、ドレイン電極１２．１３を設けて、本発明による
ＥＰＲＯＭセルが得られるものである。Subsequently, heat treatment is performed at 950'C for 20 minutes in an oxygen atmosphere to form an oxide film 8 on the exposed silicon substrate and polysilicon surface areas. At the same time 1
Type source and drain regions 9.10 are formed. Next, as shown in FIG. 1(,), a CVD oxide film 11 with a thickness of 0.5 μm is deposited, contact holes are formed by RIE method, and an At-8T film with a thickness of 1 μm is deposited and patterned. By providing source and drain electrodes 12 and 13, an EPROM cell according to the present invention is obtained.
上記のものにあっては、フローティングゲートとなるポ
リシリコン膜３上に、ＬＰＣＶＤ法にょシ窒化膜４を堆
積し、これを酸化にょシ酸化性物質５に変換することで
、３００１以下の薄膜領域においても良好な耐圧、信頼
性の高いフローティングゲートとコントロールゲート間
の層間絶縁が可能となるものである。In the above case, a nitride film 4 is deposited by LPCVD on a polysilicon film 3 that will become a floating gate, and this is converted into an oxidizing substance 5 to form a thin film region of 3001 or less. This also enables interlayer insulation between the floating gate and the control gate with good breakdown voltage and high reliability.
フローティングゲートとなる第１のポリシリコン膜上に
酸化によＦ） ｐｏｌｙ酸化膜を形成し、窒化膜を堆積
し、この窒化膜を酸化性物質に変換しても本発明がなさ
れる。The present invention can also be achieved by forming a F) poly oxide film by oxidation on the first polysilicon film that will become the floating gate, depositing a nitride film, and converting this nitride film into an oxidizing substance.
以上説明した如く本発明によれば、信頼性の高い第１．
第２の／ リシリコン膜間の層間絶縁膜が得られるもの
である。As explained above, according to the present invention, the highly reliable first.
An interlayer insulating film between the second silicon film and the silicon film is obtained.
第１図（ＩＬ）ないしくｅ）は本発明の一実施例の工程
説明図である。
１・・・Ｐ型−７，ＩＪコン基板、２・・・ゲート酸化
膜、３・・・第１のプリシリコン膜（フローティングゲ
ート）、４・・・窒化膜、５・・・酸化性物質、６・・
・第２ Ｆ） 、ｆ？ ＩＪシリコン膜（コントロール
ｆ−））、２・・・レジスト膜、８・・・酸化膜、９・
・・Ｎ＋型ソース領域、１０・・・Ｎ＋型ドレイン領域
。
第１
（ａ）
（Ｃ）FIG. 1 (IL) to e) are process explanatory diagrams of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type-7, IJ converter substrate, 2... Gate oxide film, 3... First pre-silicon film (floating gate), 4... Nitride film, 5... Oxidizing substance , 6...
・Second F), f? IJ silicon film (control f-)), 2... resist film, 8... oxide film, 9...
...N+ type source region, 10...N+ type drain region. 1st (a) (C)
Claims (2)
のポリシリコン膜を設ける工程と、前記第１のポリシリ
コン膜上にシリコン窒化膜を設ける工程と、前記シリコ
ン窒化膜を酸素雰囲気中にて熱処理を行なうことによっ
て少くとも前記シリコン窒化膜を酸化性物質に変換する
工程と、前記酸化性物質上に第２のポリシリコン膜を設
ける工程と、前記第２のポリシリコン膜、酸化性物質、
第１のポリシリコン膜、ゲート絶縁膜を部分的にエッチ
ング除去する工程と、第２導電型を与える不純物を前記
基板中にドーピングする工程とを具備したことを特徴と
する半導体記憶装置の製造方法。(1) A gate insulating film on a semiconductor substrate of a first conductivity type, a first
a step of providing a polysilicon film on the first polysilicon film, a step of providing a silicon nitride film on the first polysilicon film, and a heat treatment of the silicon nitride film in an oxygen atmosphere to make at least the silicon nitride film oxidizable. a step of converting into a substance, a step of providing a second polysilicon film on the oxidizing substance, the second polysilicon film, the oxidizing substance,
A method for manufacturing a semiconductor memory device, comprising the steps of partially etching away a first polysilicon film and a gate insulating film, and doping an impurity imparting a second conductivity type into the substrate. .
ト、第２のポリシリコン膜をコントロールゲートとする
ことを特徴とする特許請求の範囲第１項に記載の半導体
記憶装置の製造方法。(2) The method of manufacturing a semiconductor memory device according to claim 1, wherein the first polysilicon film is used as a floating gate, and the second polysilicon film is used as a control gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6692685A JPS61225871A (en) | 1985-03-30 | 1985-03-30 | Manufacture of semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6692685A JPS61225871A (en) | 1985-03-30 | 1985-03-30 | Manufacture of semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61225871A true JPS61225871A (en) | 1986-10-07 |
| JPH0116024B2 JPH0116024B2 (en) | 1989-03-22 |
Family
ID=13330072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6692685A Granted JPS61225871A (en) | 1985-03-30 | 1985-03-30 | Manufacture of semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61225871A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453634A (en) * | 1987-12-21 | 1995-09-26 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor device |
-
1985
- 1985-03-30 JP JP6692685A patent/JPS61225871A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453634A (en) * | 1987-12-21 | 1995-09-26 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0116024B2 (en) | 1989-03-22 |
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