JPS61220048A - System for processing trouble of channel - Google Patents

Abstract

PURPOSE:To minimize the number of troubled channels to be restored and to shorten the restoration processing time by informing the positions of the troubled channels simultaneously when seriously troubled plural channels are reported. CONSTITUTION:A trouble position display latch 17 detects and latches the error of each register in a channel processor CHP 3, and displays the position of trouble. It is discriminated by a separate part 8 and a common part 9, and its information is made collectable by a service processor SVP 6. When the trouble is detected by the separate part 8 or the common part 9, the 1st trouble processing part 15 processes a trouble processing request capable of pinpointing a channel CH with only the CH as a trouble, and reports it as a slight CH trouble to a CPU 2. When plural CHs develop troubles, it is processed as a CH damage expressing a serious trouble state by asking the 2nd trouble processing part 16, and is reported to the CPU 2. Simultaneously trouble information is read out of the latch 17 and the position of the troubled CH is reported to the CPU 2.

Description

Detailed Description of the Invention [Summary] In a channel processor that commonly controls a plurality of channels, appropriate fault processing and reporting to the CPU are performed corresponding to fault states in each of the common part 1 and the individual parts. To minimize the range of failure recovery processing by notifying the CPU of the failure channel number in the case of severe failures that occur simultaneously.

[Industrial application field]

The present invention relates to a computer system.

In particular, it relates to a channel fault handling method in a channel processor.

[Conventional technology]

FIG. 2 shows the configuration of a general computer system having nine channel processors to which the present invention is directed. In the figure, 1 represents a main storage unit MSU, 2 a central processing unit CPU, 3 a channel processor CHP, 4 a channel CH, and 5 an input/output device 110.6 a service processor SvP.

The channel processor CHP sequentially controls a plurality of channels CH, and controls the input/output device I10 and the main storage device MSU.
Perform input/output data transfer between

The channel processor CHP includes an individual unit that individually and cyclically controls each channel CH, and a common unit that sequentially processes processing requests generated in each channel CH, and manages respective failures. When a failure occurs, a report is made to the operating system (O8) of the central processing unit CPU, and detailed information about the failure is collected by the service processor SVP.

FIG. 3 shows a channel CH control mechanism in the channel processor CHP. In the figure, 7 indicates a stack memory in which control information for each of the 16 channels CHO to CHF is stored, 8 indicates an individual section, and 9 indicates a common section.

In the individual section 8, the channel CHO is stored from the stack memory 7.
From CHl, CH2,..., CHF, CHO, CHI
, CH2, . . . control information is read out and updated cyclically. At this time, if processing is required by the common unit 9, a processing request is issued to the common unit 9.

At this time, if the common unit 9 is processing a processing request for another channel, it issues the processing request again in the first cycle. When a request is accepted, the common unit 9 reads out the control information of the channel, processes it, and updates it.

By the way, during the above operation, there was a hardware failure.

For example, if a register parity error occurs.

This is indicated by the Channel Control Check CCC (Cha
This is reported to the OS as a control check).

For example, if the common unit 9 is composed of a microprocessor and a 2-bit error is detected in its control memory, this is reported to the O8 as channel damage, indicating that it is impossible to continue processing.

Additionally, if another failure occurs during the processing of these failure reports, the O8 is notified as a channel damage, and the OS performs the failure recovery process, which is a common method. .

In addition, if a failure occurs to the extent that normal operation can continue while a certain channel is operating, only that channel will undergo a channel control check (CCC), and other channels will continue normal operation without being affected. It is also common to do so.

[Problem that the invention seeks to solve]

In a channel processor, if a failure occurs in the same channel or another channel while a failure is being processed for a certain channel, 2 In a system that reports a severe failure to the CPU, the operating system of the CPU that receives the report performs recovery processing. However, in the past, many methods were used to examine all channels within a channel processor, identify a channel that has become inoperable, and reinitialize it.

In this case, the operating system has to examine all channels, which is wasteful.

There was a problem in that the recovery process took a long time.

[Means for solving problems]

As described above, when reporting a severe failure when multiple channel failures occur simultaneously, the present invention can reduce the number of channels targeted for failure recovery processing by simultaneously notifying the location of the failed channel. This is intended to reduce one recovery processing time to the necessary minimum.

FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, 92 is the central processing unit CPU, 3 is the channel processor CHP, 4 is the channel CH, and 5 is the input/output device I.
10.6 is a service processor SP, 8 is an individual part, 9
15 is a common part, 15 is a first fault processing section, 16 is a second fault processing section, and 17 is a set of fault position display latches.

The fault position indicator latch 17 is connected to the channel processor CHP.
This is a means for primarily displaying the cause of failure, such as the error detection latch (EDL) of each register in the
Alternatively, it may be identified by the common part 9 and its information may be directly collected by the service processor SVP.

When a failure is detected in the individual unit 8 or the common unit 9, the first failure processing unit 15 receives a failure processing request from the individual unit 8 or a failure processing request from the common unit 9, if the channel can be identified.

Only the corresponding channel is treated as a failure, and the channel failure is reported to the CPU.

In addition, if faults of the same type or different types repeatedly occur in the same channel or other channels during fault processing of one channel, a request is made to the second fault processing unit 16 to handle it as channel damage indicating a severe fault state. and report to the CPU (or other higher-level device). At this time, the location of each channel where the failure has occurred is also notified at the same time.

Channel damage reporting is done by Service Processor SvP
It is also held in In response, the service processor SP directly reads the fault location display latch 17 and makes it available for fault analysis as detailed fault information.

Note that if no other failure occurs during the failure processing of one channel, the processes of other channels that are normally being executed at that time are allowed to continue as they are.

[Effect]

According to the present invention, the first failure processing unit responds to the presence or absence of a failure for each channel, and reports the failure of a single channel as a minor channel failure.

However, if other channel failures occur at the same time during the reporting process of one channel failure, the second failure processing unit will report the failure as a double failure, but at that time, the locations of those failed channels will also be reported. C who received the report will be notified.
The operating system of the PU can immediately designate a faulty channel and perform recovery processing, thereby eliminating unnecessary processing.

〔Example〕

FIG. 5 shows the configuration of a system according to an embodiment of the present invention, and FIG. 6 shows its processing flow.

In FIG. 5, 1 is a main storage unit MSU, 2 is a central processing unit CPU, 3 is a channel processor CHP, 4 is a channel CH, 5 is an input/output device 110, 6 is a service processor SVP, 8 is an individual unit, and 9 is a Common part, 11 is operating system O3, 12 is error detection launch EDL
, 15 is a first fault processing unit, 16 is a second fault processing unit, 18
19 is a first fault processing request flag, and 19 is a second fault processing request flag.

20 represents an execution launch, and 21 represents a channel position notification circuit.

A large number of error detection latches EDL in the channel processor CHP are controlled by related individual sections 8 and common sections 9, and when a failure occurrence state is displayed, it is recognized by the corresponding individual section 8 or common section 9. Each of these EDLs is also configured as each stage of a shift register, and the contents can be scanned out according to instructions from the service processor SvP.

Each individual unit 8 has a 1-bit first fault handling request flag 18, and sets the flag on when the subordinate EDL recognizes the occurrence of a fault. This flag is
For example, it can be included as part of the control information for each channel of the stack memory shown in FIG.

Regarding a failure occurring in the common unit 9, if the corresponding channel CH can be identified, the corresponding first failure processing request flag 18 is set on.

However, if the channel cannot be identified or if normal operation cannot be guaranteed overall, the second failure processing request flag 19 is set to ON as a 9 severe failure. In addition,
In this case, it is also possible to set on the first failure handling request flags corresponding to the individual units of all channels operating at that time.

The execution latch 20 is set on while the first failure processing unit 15 is executing failure processing.

The channel location notification circuit 21 is a circuit that generates location information for identifying the number of each faulty channel when reporting channel damage when a plurality of channel faults occur simultaneously.

The channel damage (CD) report by the second failure processing unit can be done with one bit per channel processor CHP. However, several more bits are required to notify the channel number in code. However, in this embodiment, by associating the timing of generating a channel damage (CD) reporting bit with the channel position, it is possible to eliminate the need for adding a special bit for channel number notification.

For example, if there are 16 channels from CHO to CHF, 16 timing positions or time slots consisting of To to TIS are determined as shown in FIG. , that is, it is sufficient to send out the CD bit.

The illustrated example is a case where CH2 and CH5 are faulty channels.

Note that the time slots To to TIS can be synchronized with the time slots of the individual unit 8 that cyclically accesses the stack memory 7 described in FIG.

FIG. 8 shows the configuration of one embodiment of a channel position notification circuit using a multiplexer.

In the figure, 7 is a stack memory and 8 is an individual section.

Reference numeral 9 represents a common section, 16 a second failure processing section, 22 a 16-manpower multiplexer, 23 a failure channel position signal, 24 a 4-bit time slot signal, and 25 a CD signal containing channel position information.

When the second failure processing unit 16 is notified of a severe channel failure state due to the occurrence of multiple channel failures from the first failure processing unit, the second failure processing unit 16 turns on the failure channel position signal 23 of the corresponding channel.

The multiplexer 22 functions to sequentially select 16 faulty channel position signal inputs using a 4-bit time slot signal 24 and convert parallel data on the input side to serial data. In this way, it is possible to send a CD signal including any number of faulty channel locations as information to the CPU.

On the CPU side, the time slot position where the pulse exists is detected from the received CD signal, and the channel number is recognized from this.

Note that the channel position notification circuit shown in FIG. 8 is just one example, and a similar function can be easily achieved by using a shift register, a counter, or comparing channel numbers with a comparator. It is configurable. Furthermore, in the case of a severe failure in which the channel cannot be specified, CD signals may be output at all time slot positions.

Next, referring to the processing flow in FIG.
5 and the functions of the second failure processing unit 16 will be explained.

■ The first fault processing unit 15 sets the first fault processing request flag 1.
8 is checked, and if it is on, execute the process (■), and if it is off, execute the process (■).

(2) If the first fault processing request flag is on, whether or not the execution latch 20 is set on.

That is, it is checked whether or not the first failure process is currently being executed, and if it is on, execute (2), and if it is off, execute (2).

■ Since the execution latch 20 is off, set it on. Next, execute ■.

■ Executes the first failure process, registers the requested channel in the table as a failure channel, and registers the status register 10.
The channel control check (CCC) is set to , and is reported to the CPU's operating system O8. Next, execute ■.

■Reset the execution latch 20 to OFF.

■ If the first failure processing request flag is off in ■.

Check the second failure processing request flag 19. If it is on, execute ■, and if it is off, return to ■.

■ If the execution latch is on in ■, that is, another failure occurs in the same channel or another channel while handling the failure of the previous failed channel, and if the second failure handling request flag is on in ■, i.e. If a fault that occurs in a common part cannot identify the channel being executed or if normal operation cannot be guaranteed thereafter, it is treated as a 9 severe fault, and the channel damage (CD) is recorded in the status register 10.
and reports to CPU O8. Note that in the case of channel damage caused by multiple channel failures, the channel location is also notified.

When the operating system O8 receives a channel control check (CCC) or channel damage (CD) report from the channel processor CHP, it examines the channel status and takes appropriate actions such as initializing the channel and reloading the control memory. Execute recovery processing.

Channel damage (CD) is also reported to the service processor SVP at the same time as to the CPU. In response, the service processor SvP
Each error detection latch EDL of the channel processor CHP is read by scanning out independently of the reporting process to the CPU.

Collected as detailed information for failure analysis, and after processing is completed,
Reset the error detection latch EDL.

In particular, when receiving a channel damage (CD) report when channel failures occur simultaneously, the operating system O3 executes initialization processing only for the channel positions notified at the same time.

In the channel processor CHP, channel damage (C
D) is recorded in the table as a failed channel, and responds to an I10 instruction from the CPU with a condition code indicating that it is not operable. If the initialization is completed normally, the record on the table is changed to online.

In the above explanation, the case where there is only one channel processor CHP has been explained as an example, but as shown in FIG. It goes without saying that the present invention is similarly applicable.

〔Effect of the invention〕

According to the present invention, in the case of a severe failure in which a channel can be identified in the channel processor, the channel position, that is, the channel number, is notified to the CPU or other higher-level device at the same time as the channel failure report, thereby speeding up recovery processing. I can do it.

It is possible to improve the processing efficiency of the system.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, and FIG. 2 is a configuration diagram of a general computer system to which the present invention is applied. FIG. 3 is an explanatory diagram of the control mechanism of the channel processor. FIG. 4 is an explanatory diagram of the channel failure detection mechanism of the conventional system, FIG. 5 is a configuration diagram of the embodiment system of the present invention, FIG. 6 is a processing flow diagram of the embodiment system of FIG. 5, and FIG. 7 is the channel failure detection mechanism of the conventional system. A damage (CD) signal timing diagram, FIG. 8 is a block diagram of an embodiment of a channel position notification circuit, and FIG. 9 is a block diagram of a multichannel processor. In FIG. 1, 2 is a central processing unit CP0.3 is a channel processor CHP, and 4 is a channel CH. 6 is a service processor SVP, 8 is an individual section, 9 is a common section, 15 is a first fault processing section, 16 is a second fault processing section, 1
7 indicates a set of fault location indicating latches, CCC indicates channel control check, and CD indicates channel damage.

Claims (1)

[Claims] An individual unit that individually and cyclically controls a plurality of channels;
It has a common part that sequentially processes processing requests generated from each channel, and faults that occur in the individual parts and the common part are reported to the CPU as channel faults.The channel processor processes the faults that occur in the individual parts. In addition to reporting the problem as a minor channel failure, if the channel that is operating in the common part can be identified, the failure occurring in the common part is treated in the same way as a failure occurring in the individual part, and the failure is treated as a minor channel failure. and a second fault processing means that reports a fault occurring in the common part as a severe channel fault when the channel operating in the common part cannot be identified. While the fault handling means detects a fault in one channel and reports a minor channel fault,
If a similar or different type of failure occurs in the same channel or other channels, the second failure processing means reports a severe failure, and at the same time notifies the location of the failed channel. failure handling method for the channel.