JPH07306811A - Memory fault diagnosing method - Google Patents

Abstract

PURPOSE:To provide an effective fault diagnosing function of a memory fault which is low in reproduction frequency by effectively utilizing the surplus processing ability of a controlled device. CONSTITUTION:The microprocessor of the controlled device 101 reads the contents of a 1st-class specified area of a memory device out in order and takes a 1st-class fault diagnosis wherein an error detecting means detects an error; if the error detecting means detects the error in the 1st-class fault diagnosis, a 2nd-class fault diagnosis for detecting an error repeatedly is taken for a 2nd-class area which is an area including the address where the error is detected and narrower than the 1st-kind fault specified area of the memory device. When a control signal is received from a host processor during the 1st-kind fault diagnosis or 2nd-class fault diagnosis, the fault diagnosis is discontinued.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention enables a free time of a sub-processor (hereinafter referred to as a μ-processor) mounted on a controlled device controlled by a host processor and operable under the control of the host processor. The present invention relates to a method for efficiently performing failure diagnosis of a large capacity memory by utilizing the method.

[0002]

2. Description of the Related Art It has become common for a controlled device that operates based on a control order from a processing device to incorporate a μ processor, reflecting recent advanced component technologies such as LSI technology. It was This type of controlled device receives a control order or an emergency interrupt signal from the host processor,
In many cases, it is required to perform the processing associated therewith at an extremely high speed, and in the conventional system, until the next control order arrives after the processing of the control order from the upper processing unit is completed, In spite of its high processing capacity, it was performing a process of waiting for the arrival of the next control order by continuing wasteful idling or waiting for the interrupt related to the next control order. In the system adopting such a method, the lower the frequency of control order reception, the lower the usage rate of the μ processor, and the processing capacity of the μ processor is not effectively used.

On the other hand, there has been a problem that the scale of the memory required by the μ-processor increases with the increase of the functions shared by the controlled devices, and the time required for the failure diagnosis of the memory increases. In particular, with the recent widespread use of large-scale integrated circuit technology, a complicated failure form in which a failure rarely becomes apparent as the memory address is accessed many times has increased. Such a complicated failure mode has been one of the factors that further lengthen the failure diagnosis time.

The problems of the prior art will be described below with reference to the drawings. FIG. 1 is a conceptual diagram of a general system including a host processor and a plurality of controlled devices that operate under the control of the host processor, and is used in many computer control systems including an exchange. In FIG. 1, reference numeral 100 is a host processor, 101-n is an nth controlled device controlled by the host processor 100, which can operate under the control of the host processor. A signal path 102 for transmitting a control signal and its response signal is provided between 100 and 101. 101 receives the control signal from 100 via signal path 102, performs necessary processing, and returns the result to 100 again via signal path 102.

FIG. 2 is a diagram for explaining a general functional block configuration example of the controlled device 101. In FIG. 2, 100, 101, and 102 are the same as the abbreviations shown in FIG. First, the connection configuration of the functional blocks in FIG. 2 will be described.

In FIG. 2, 200 is a controlled device 101.
The control signal from 100 reaches the controlled device 101 via the signal path 102. The signal receiving circuit 20 is provided inside the controlled device 101.
4 receives the signal and notifies 200 by an interrupt or a bus message. Reference numerals 201, 202, and 203 denote a RAM (random access memory; main memory), a ROM (read only memory), and an HD (file memory; hard disk) connected to the μ processor 200. Reference numeral 205 denotes a device to be controlled which is finally controlled based on the processes 200 to 203.

Next, the outline of the operation will be described with reference to FIG. The upper processing device 100 performs necessary processing based on the control of the stored program, and based on the result, selects one of the plurality of controlled devices 101 under its control and sends the necessary control order. . Controlled device 101
Then, the signal receiving circuit 204 accepts this, and notifies it by interrupting the built-in μ processor 200 or by periodical reading. The μ processor 200 interprets this and executes the necessary processing related to the received signal to the control target device 205 at high speed. When the μ processor 200 finishes processing all of these processes, the previous process that was interrupted is executed from the interrupt point.

The configuration of the system and the outline of the processing are as described above, but in order to improve the performance of the entire system, the function to be controlled by the controlled device 101 has been increasing in recent years.
Along with this, the memory function (20
1,202,203) capacity also tends to increase dramatically. One of the functions that the controlled device has taken charge of
One of them is a failure diagnosis function of the controlled device, which is generally called self-diagnosis or autonomous diagnosis.

In the previous system in which the LSI technology has not advanced so much, the failure diagnosis of the lower controlled device is executed in the idle time of the upper processing device (100) or the level of low priority for cost reduction. However, since it can be applied at a level where the μ processor cost can be ignored, the effect of the circuit level of the lower controlled device affects the application program of the upper processing device, In order to solve problems such as that the load on the device can no longer be ignored and that the failure diagnosis time is lengthened due to the complexity of failure modes and the low priority of diagnosis processing, Controllers are often adopting a self-diagnosis method of diagnosing their own circuit failure. However, despite the adoption of such a method, the memory capacity continues to increase beyond the effect of such measures, and as a result, it is difficult to shorten the diagnosis time by the self-diagnosis method. It was

On the other hand, as the function allocation ratio on the controlled device side increases, the performance required of the μ processor also increases,
Once the control order is accepted, the processing based on this control order is executed at extremely high speed. However, as the frequency with which one processing device accesses a plurality of controlled devices increases, it cannot be said that the frequency of control order reception in the controlled devices is necessarily high, and as a result the control order waiting time ratio also increases. There was also a problem that the μ processor could not always be used effectively.

FIG. 3 is a diagram for explaining the conventional method in more detail. In the memory device, it is important to detect an error in the stored data even when the storage device is in operation. For this reason, error detection codes have been widely used in the past. One of the simplest error detection codes is a vertical parity code, and a code capable of error correction as well as error detection is a vertical and horizontal error detection code or an ECC code. Since these failure detection methods and correction methods are widely known and are not necessary for explaining the constituent conditions of the present invention, the description thereof will be omitted here.

In a system such as an exchange that requires continuous and stable operation, measures such as duplication of important devices such as memory devices are taken, and an abnormality is detected in such devices. Then, while continuing the communication switching service, the service is switched to the standby system, the service is started in the new system, and then the diagnosis of the switched failure device is performed.

In the failure diagnosis performed at such a time, the failure detection is performed on the failure diagnosis area of the memory device after the apparatus to be diagnosed is set to the initial state so that the diagnosis result does not change each time the failure diagnosis is performed. In general, a suitable pattern is written, the written data is read again, and the correct data (write data) is compared.
Hereinafter, such a failure diagnosis method will be described in detail with reference to the drawings.

In FIG. 3, reference numeral 201 denotes a memory device, which externally receives write data and address information required for memory access from the data bus 301 and the address bus 302, and the memory device 201 stores the data in the memory element 307 based on this information. When accessed and read, read data can be output to the answer bus 303.

The memory device 201 includes a memory address register 304 for storing memory address information, a data write register 305, a data read register 306,
It includes a memory element 307 and the like. μ processor 200
Includes a memory data bus 301 and a memory address bus 3
When the memory is accessed using 02, circuits (308-1, 308-2) for generating parity information are provided in order to check whether or not the data can be correctly received on the memory side, and the memory device side receiving the data has the circuit. , A first-type parity check circuit (309-) for detecting an error in the data.
1, 309-2) are provided. Further, in order to detect an error when reading the memory data with parity information, the μ-processor side answer bus is provided with a type II parity check circuit (310).

In the memory device in operation, 308-1, 3
An inspection is performed every time writing or reading is performed by using an error checking code generating circuit such as 08-2, 309-1, 309-2 or the like, and its checking circuit. When an error is detected here, the entire controlled device 101 is disconnected from the system, and the failure diagnosis of the memory device disconnected from the system is performed. In this case, the failure diagnosis target memory 201 is initialized, and all specified data (for example, data of all 0s) is completely written according to a predetermined procedure (generally, sequentially updating addresses from the lowest address of the memory address). After writing to the address, this is read out, compared with the correct value and inspected, and then the above-described processing is repeated by writing the inverted data of the previous data (for example, all 1's data).

FIG. 4 shows an outline flow of an example of a conventional test execution procedure. By carrying out such a test, a 1-bit stack failure of the memory (a failure that becomes 0 or 1 fixedly when the memory bit is read) can be reliably detected.

However, as a general tendency, it is not always 1
A memory failure cannot always be detected by reading once.
In many cases, there are occasions when a failure occurs at the time of reading, and even if the data at the relevant address is read and a test is performed at such times, it is not always necessary to confirm an error (error in memory data) with one read. I can't. Such a failure is called a temporary failure (intermittent failure) and has been one of the factors that make the system unstable.

Further, when a large number of controlled devices whose memory scale exceeds 100,000 bytes are handled, the fault diagnosis data is written once to all the addresses, then this is read and collated with the correct answer data. Therefore, a long time of several minutes to several tens of minutes is required, and further, when the proportion of temporary failures increases, it is necessary to repeatedly perform failure diagnosis, and therefore the required time becomes longer. .

[0020]

SUMMARY OF THE INVENTION An object of the present invention is to effectively utilize the surplus processing capacity of a controlled device to efficiently diagnose a large-capacity memory failure and to prevent a memory failure with a low frequency of reproduction. On the other hand, it is to provide an effective failure diagnosis function.

[0021]

According to the present invention, in order to achieve the above object, the μ processor of the controlled device sequentially reads the contents of the type 1 designated area of the memory device and detects the error by the error detecting means. When the type 1 failure diagnosis is performed and the error detecting means detects an error in the type 1 failure diagnosis, the area includes the address where the error is detected and is narrower than the type 1 designated area of the memory device. Second
The second type failure diagnosis for repeatedly detecting an error is performed on the seed area.

Further, according to the present invention, when the control signal from the host processor is received during the execution of the type 1 failure diagnosis or the type 2 failure diagnosis, the type 1 failure diagnosis or the type 2 failure diagnosis is performed.
Interrupt the seed failure diagnosis.

[0023]

With the recent improvement in the performance of the μ processor, the control order from the host processor is sent at a sufficiently long time interval as compared with the performance of the μ processor mounted on the controlled device which is apparently controlled by it. Will come. Even in an example of a large-scale system such as an exchange, there are not a few devices that are used for processing related to a control order only about half of the available time of the controlled device. However, once the control order is accepted, it is necessary to process it at high speed and send back its response in a short time, so the performance requirement for the μ processor is not weakened. Until now, attempts have been widely made to effectively utilize this idle time to reduce the load on the processing device. A first feature of the present invention is that the surplus capacity of the μ processor mounted on the controlled device is applied to the failure diagnosis of the controlled device memory.

On the other hand, along with the increase in the function allocation to the controlled device, the scale of the memory mounted on the controlled device has increased. The failure mode of such a large-scale memory is complicated,
In many cases, it cannot be detected by writing or reading once. In the failure diagnosis of such a large scale memory, the diagnosis time becomes long. The second feature of the present invention is that the fault diagnosis is divided into two layers in order to solve such a problem. That is, in a normal operating state, for a failure diagnosis target memory that may have a low frequency of failure reproduction,
The error detection of the memory data is intermittently performed by utilizing the idle time of the μ processor mounted in the controlled device, and once the failure is detected in the failure diagnosis of this hierarchy, the failure occurrence address or the failure occurrence address is set. It is characterized in that the failure diagnosis is repeatedly executed in a concentrated manner only in the area of the memory that includes it.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Recently, not only memory has been often equipped with an error automatic correction mechanism as well as an error detection mechanism, but such a mechanism itself is provided inside a memory device (memory peripheral circuit). Many methods have been adopted. As such a mechanism, an ECC system, a horizontal / vertical parity system, or the like is often used. When storing memory data, extra information for error detection / correction of the data is stored in addition to the data to be stored. It is common in that when the data in the area is read, the extra data is used to perform error detection or correction. Since the present invention does not depend on what kind of error detection method or correction method is adopted, the method of performing error detection using the simplest parity code is taken as an example in the description of the embodiment.

The points necessary for explaining the embodiment in detail will be described in more detail by taking FIG. 3 as an example. In FIG. 3, reference numeral 201 denotes a memory device, which externally receives write data and address information required for memory access from the data bus 301 and the address bus 302,
01 accesses the memory element 307 based on this information, and at the time of reading, the read data is transferred to the answer bus 303.
Can be output to. The memory device 201 includes a memory address register 30 for storing memory address information.
4, a data write register 305, a data read register 306, an error check circuit that can check whether or not an error has occurred in the data at the time of reading the memory, and can generate check data necessary for the check at the time of writing. include.

The memory element 307 is provided with an address for each unit called a word, and the address register 30
When the address information m is stored in 4, the content of the address m is read out to the read register 306.

The contents of the address m are composed of a storage target data part sent from the data bus and an error detection code (parity code) capable of detecting an error in the contents of the data part. . At the time of reading this data, the parity check circuit 309 can check the error of the data based on the error detection code. This error checking method is performed so that the number of 0s or 1s of the memory bit to be inspected is 1 evenly or oddly.
Since it is a method of adding bits and is widely used, detailed description thereof will be omitted in the present embodiment.

Since the memory device has such a configuration, when a 1-bit failure occurs in the memory, an error can be detected as an abnormality of the parity code by simply reading the memory data.

However, as a general tendency, it is not always 1
A memory failure cannot always be detected by reading once.
In many cases, a failure sometimes occurs at the time of reading, and even if the data of the address is read and a test is performed at such a time, it is not possible to confirm the abnormality (error of memory data). Such a failure is called a temporary failure (intermittent failure) and makes the system unstable.

The first type failure diagnosis is characterized in that the entire area of the memory device having a large capacity or a large area (first type designated area) therein is sequentially read out to perform error detection. In the second type failure diagnosis, when the memory device is incorporated in the online system,
First to minimize the impact on the host processor
Execute with a lower priority for species failure diagnosis. As a result, the type 1 failure diagnosis will be executed when the load of the μ processor is light, and by repeating this operation many times, the deteriorated bits of the memory device will eventually have a temporary or fixed parity. It can be detected as an error.

However, since the error can be detected only by reading, the fault diagnosis for one round of the designated whole area of the large capacity memory is relatively short in parallel with the online processing based on the instruction order from the host processor. It can be done in time. Further, when the memory device is not incorporated in the online system, even if the same processing as that in the case where the memory device is incorporated in the online system is performed, there is no order from the higher-order processing device. The failure detection rate for diagnosis will effectively increase.

Second operation performed in association with the first type failure diagnosis result
Species failure diagnosis is a feature of the present invention. That is, in the first type failure diagnosis, when an error is detected, additional information (error data etc.) including the address in which the error has occurred is collected, and the failure is intensively detected in a narrow area including this error occurrence address. Is performed (type 2 failure diagnosis).

The number of times of failure diagnosis per bit of the memory is from several minutes to several tens of minutes in the first type failure diagnosis, but in the second type failure diagnosis, the frequency is several thousand to several million times. Can be increased. By performing high-frequency failure diagnosis in a narrow area where an error has been detected, it becomes possible to efficiently manifest a rarely detected failure.

The above operation in the embodiment will be described in more detail with reference to the flowchart of FIG. In this flowchart, i is the number of failures detected in the type 1 failure diagnosis. In this embodiment, when the type 1 failure diagnosis is started, i is initialized and 0 is written. After that, when a failure is detected in the type 1 failure diagnosis, the value of i is incremented by 1 each time, and the number of failures detected in the type 1 failure diagnosis is stored.

On the other hand, the type 2 failure diagnosis is performed corresponding to the failure detected in the type 1 failure diagnosis, and the type 2 failure diagnosis is 1
The value of i is decremented by 1 each time a case is completed, and when the value of i becomes 0, the type 2 failure diagnosis is not executed only during that period.

In FIG. 5, when the first type failure diagnosis is first activated, the value of i is also written to 0, and the first type failure diagnosis mode is set which is repeatedly executed at the lowest priority. In the failure diagnosis in this mode, information on the execution range of the diagnosis such as the diagnosis start address and the end address is required, and this information is designated before the execution of the diagnosis. First
At the start of the seed failure diagnosis, data is read from the diagnosis start address and the data is checked.Therefore, in this flowchart, it is judged whether this address is within the diagnosis target range or out of the range before reading. If it is outside, it is decided to execute the diagnosis again from the first diagnosis start address.

If the address is within the diagnostic range,
The error control information (parity ECC code or the like is well known) added to the read data is inspected to check the normality of the data. Since this inspection is repeatedly performed by updating the address every time one word is executed, if no error occurs in the data, this type 1 failure diagnosis will be repeated indefinitely.

When a failure is detected in this type 1 failure diagnosis, relevant data including the address in which an error is detected (for example, error data pattern, correct answer value, etc.) is collected, and this information is saved. , I are incremented by one.

There are many possible triggers for the type 2 failure diagnosis, but in the immediate activation trigger mode, the trigger is activated each time one failure is detected. On the other hand, in the regular activation trigger mode, the regular activation is activated every time a certain period of time elapses (for example, once a day). This determination is the activation mode determination in the flowchart.

When the type 2 failure diagnosis is started, the failure-related data stored at the time of the type 1 failure diagnosis is retrieved one by one, and a very narrow range (1 to 10) including the failure occurrence address is fetched.
A sufficient number of times (for example, 100 to 100 words)
1,000,000 times).

In the first type failure diagnosis, since the diagnosis target is wide,
It is not uncommon that the number of failure diagnoses per memory element is only once / 15 minutes. A failure such as a temporary failure may occur only once for 100 to 10,000 accesses, and in a memory having a memory error automatic correction function, error data is automatically corrected. It is often extremely difficult to reproduce the failure only by this diagnosis.

However, since this diagnosis is repeatedly executed infinitely many times with a low priority level,
When a certain amount of time has passed, a failure is detected with a certain probability. On the other hand, in the second type diagnosis, since the diagnosis is performed with a sufficiently large number of repetitions for a location where a failure has occurred once, the failure reproduction probability can be dramatically increased. Become.

Here, the determined type 2 failure diagnosis is carried out, the result is notified to the upper software, and such a test is repeated for the next failure location.
When the type 2 failure diagnosis is completed for one failure, the value of i is decremented by 1 each time, and these processes are repeatedly executed until the value of i becomes 0.

As described above, the type 2 failure diagnosis is
When an error is detected in the type 1 failure diagnosis, it may be activated each time, but it may be activated periodically. The reason is that in any of the above activation triggers, in the process of the type 2 failure diagnosis, it is checked whether or not an error has been detected in the type 1 failure diagnosis. This is because the type 2 failure diagnosis is performed sequentially focusing on the location. Further, the second type designation area may be one word (or byte) or plural words (or bytes) including the address.

Further, the type 1 failure diagnosis may be carried out in a time-division manner during the idle time while performing online processing under the control of the host processor, or may be disconnected from the system and carried out in an offline state. .

In the first type failure diagnosis, the occurrence of a temporary failure is inspected for a long period of time, and a simple error detection method such as a parity code is used to inspect the location where an error is detected even once. Since the failure reproduction probability is high for the type 2 failure diagnosis, it is conceivable to use a stricter error checking method (a method using reading after writing inverted data together).

Further, in the embodiment, the description has been limited to the main memory (RAM), but if the type of memory device is ROM,
The target is not limited, even if it is a file memory device such as a hard disk device or a magneto-optical disk device.

[0049]

When the present invention is applied, the following effects can be obtained due to the features described above. The μ processor in the controlled device, which has not been effectively used in the past, can contribute to the preventive maintenance that effectively functions for the memory failure diagnosis as the free time increases. If a fault with low reproducibility occurs even once, when viewed from the relevant address, the diagnosis can be performed at an access frequency that exceeds several thousand or tens of thousands times the frequency of the fault diagnosis (first type fault diagnosis) performed in the first layer. It can be repeated and the failure can be easily revealed. Further, since the failure diagnosis is automatically performed during the free time of the μ processor, the waiting time for the failure diagnosis is apparently eliminated.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a general system including a host processor and a plurality of controlled devices that operate under the control of the host processor.

FIG. 2 is a general functional block configuration diagram of a controlled device.

FIG. 3 is a detailed functional block diagram of a controlled device for explaining the conventional system in more detail.

FIG. 4 is a schematic flowchart of a conventional test execution procedure.

FIG. 5 is a schematic flowchart showing an embodiment of the present invention.

[Explanation of symbols]

 100 host processor 101 controlled device 102 signal path 200 μ processor 201 RAM 202 ROM 203 hard disk 204 signal transmission / reception circuit 205 controlled device 301 data bus 302 address bus 303 answer bus 304 memory address register 305 write register 306 read register 307 memory element 308 Parity addition circuit 309 First type parity check circuit 310 Second type parity check circuit

Claims (2)

[Claims] 1. A high-order processing device, a sub-processor (hereinafter referred to as a μ processor) operable under the control of the high-order processing device, a memory device connected to the μ processor, and reading the contents of the memory device. In the method of diagnosing a memory failure in a system including an error detecting unit for checking the data error by means of the above, the μ processor sequentially reads the contents of the first type designated area of the memory device and detects the error by the error detecting unit. If the first type failure diagnosis is performed and the error detecting means detects an error in the first type failure diagnosis,
A memory failure characterized by repeatedly performing a second type failure diagnosis for repeatedly detecting an error in a second type area which is an area including an address where an error is detected and is narrower than a first type designated area of the memory device. Diagnostic method. 2. The first type failure diagnosis or the second type failure diagnosis is interrupted when a control signal from the host processor is received during execution of the first type failure diagnosis or the second type failure diagnosis. The memory failure diagnosis method according to claim 1.