JPS61219154A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to accurately monitor the internal wiring condition of the title semiconductor device by a method wherein a groove part is provided on the circumference of a semiconductor chip when a semiconductor element is formed on the semiconductor chip, and a measuring pad is provided at both ends of the wiring which crosses the groove part. CONSTITUTION:An oxide film 2 is formed on the surface of a semiconductor layer 1. At this time, a patterning is performed on a nitride film mask in such a manner that an almost rectangular-shaped groove part 3 is formed on the surface of said oxide film 2. A wiring 4 to be used for checking is provided in such a manner that it crosses said groove part 3, and a measuring pad 5 is provided at both ends of the wiring 4. The stepping generated on the practical element located in the internal part is reproduced on the check pattern, and the check pattern is provided on the circumference of the semiconductor chip. Accordingly, the disconnection in stepped part of the wiring of the internal practical element can be checked by inspecting the presence or not of the disconnection in the stepped part of the wiring in the check pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of monitoring the manufacturing status of wiring.

(Prior Art) In recent years, there has been a trend toward higher speed, higher density, and higher integration of L8I, and various process improvements have been made to achieve this. The local oxidation method (hereinafter referred to as LOCO8 method) is also widely used in LSI manufacturing as one of the methods.

(Problems to be Solved by the Invention) However, the LOCO8 method has a major problem in that it produces a large oxide layer step on the wafer surface, causing a break in the wiring that crosses this step. In addition, differences in level may occur due to 8i, lower layer wiring, etc., which may cause disconnection of the level. In the past, various efforts have been made to eliminate this problem in manufacturing and pattern design, but monitoring the storage conditions due to this step during the LSI manufacturing process is important for manufacturing good LSIs. That's true. Currently, in order to investigate this, the appearance of the entire area of the wasasa chip is checked using a microscope, but this method requires a large amount of man-hours.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device provided with a peripheral check pattern suitable for accurately monitoring the internal wiring state of a chip with less man-hours.

(Means for Solving the Problems) A semiconductor device of the present invention has a step difference that is equivalent to a step difference caused by a semiconductor layer, an oxide film, a Tl wiring, etc. when forming a semiconductor element on a semiconductor chip, and is approximately rectangular. The device includes a peripheral check pattern including at least one groove provided around the semiconductor chip, a wiring that crosses the groove, and measurement pads provided at both ends of the wiring.

(Example) Next, examples of the present invention will be described.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention.

In FIGS. 2(a) and 2(b), 1 is a semiconductor substrate or a semiconductor layer such as an epitaxial layer formed on a semiconductor substrate. An oxide film and a nitride film are provided on the surface of this semiconductor layer 1, and selectively removed by photolithography.
An oxide film 2 is formed using the LocO8 method of oxidizing using the remaining nitride film as a mask. At this time, the nitride film mask is patterned to form a substantially rectangular groove 3 on the surface.

A check wiring 4 is provided so as to cross this groove 3, and measurement pads 5 are provided at both ends thereof.

The measurement pad 5 may have a thickness of approximately 50 μm. In addition, the wiring 4 has a length of several tens to several hundred μm and a width a of several μm to several tens of μm.
About m is fine. The width of the groove portion 3 may be approximately the same as the collector width of the transistor, and is generally several μm to several tens of μm.

The above check pattern reproduces the level difference that occurs in internal practical elements, and is provided around the semiconductor chip. Therefore, it is possible to check whether there is a break in the wiring in this check pattern or not in the wiring in the internal practical element. This check is performed by directly viewing the wiring 4 with a microscope or by setting a probe on the measurement pad 5 and applying a current. Therefore, it is possible to check the internal wiring state with much fewer man-hours than the man-hours required to check the external fitting of the entire chip using a microscope.

(Effects of the Invention) As described above, according to the present invention, a semiconductor device can be obtained in which the internal wiring state of a semiconductor chip can be accurately monitored with a small number of man-hours.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan view and a sectional view of an embodiment of the present invention. 1... Semiconductor layer, 2... Oxide film, 3...
...Groove, 4...Wiring, 5...
Measuring pad.

Claims (1)

[Claims] When forming a semiconductor element on a semiconductor chip, a semiconductor layer,
At least one substantially rectangular groove having a step difference caused by an oxide film, lower layer wiring, etc. is provided around the semiconductor chip, a wiring is provided that crosses the groove, and measurement is performed at both ends of the wiring. A semiconductor device comprising a peripheral check pattern provided with pads.