JPS61216479A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive the formation of an accurate active region and the improve ment in the integration of a semiconductor by forming grooves by etching source and drain regions of an MIS transistor on a semiconductor substrate to form the source and drain regions of the transistor. CONSTITUTION:A gate insulating film 3 and a gate electrode layer made of polycrystalline silicon or high melting point metal material are laminated on a P-type silicon substrate 1, an interlayer insulating film 11 is further grown thereon, a gate electrode 2 is patterned, and grooves are formed by etching source and drain regions 6, 7. Then, a crystalline insulating film 12 for example, of barium fluoride is epitaxially grown on the inner surfaces of the regions 6, 7, and the bottoms of the source and drain regions, and the upper end of the wall are etched by anisotropic etching method. Then, silicon is selectively epitaxially grown on BaF2, P or As is simultaneously doped to obtain a semiconductor layer 13.

Description

[Detailed Description of the Invention] [Summary] Sources and drains of MIS transistors are usually formed by ion implantation and then heat treatment, but it is difficult to form shallow diffusion regions required for highly integrated transistors.
Therefore, the problem was solved by growing doped silicon on the insulating film, that is, the barium fluoride buried layer.

[Industrial application field]

The present invention relates to a method for forming source and drain regions of MIS transistors that require high integration and high speed.

In MIS transistors that require high integration and high speed, it is desired to shorten the channel between the source and drain and to form shallow diffusion layers for the source and drain.

Normally, the diffusion layer is formed by performing high-temperature annealing treatment after ion implantation, but this makes it difficult to accurately control the profile of the diffusion region. There is a need for a highly accurate method for forming shallow active regions.

[Conventional technology]

A conventional method for manufacturing an MIS transistor will be explained with reference to the drawings.

Although many methods are used to form this type of transistor, a process using a polycrystalline silicon layer as a gate electrode with a relatively high degree of integration will be described.

Figures 2 (al to d) are cross-sectional views of transistor parts in the order of steps.To simplify the explanation, steps for forming channel stops, field oxide films, etc. that separate elements not directly related to the present invention are shown. I have omitted it.

FIG. 2(a) shows a state in which a gate electrode 2 made of polycrystalline silicon is formed in the element formation region. In the drawings, 1 indicates a p-type silicon substrate, 3 a gate oxide film, and 4 a field oxide film.

In Fig. 2, the gate electrode is masked with a resist film 5.
A state in which ions are implanted into the source and drain regions 6.7 is shown.

After removing the resist, ions are implanted into the n-region 8 for connecting the source and drain regions and the channel region, and then heat treatment is performed at approximately 1000°C for more than 10 minutes to activate the diffusion region. Finish forming. This is shown in FIG. 2(C).

Next, a 5ift or PSG film 9 is applied to the entire surface using the CVD method.
grow. Furthermore, a state in which a contact hole 10 is formed is shown in FIG. 2(d).

The subsequent formation of wiring layers will be omitted.

[Problem that the invention seeks to solve]

The conventional method described above requires high-temperature annealing after ion implantation, and the profile of the active layer region changes greatly depending on the conditions of this step.

This greatly affects transistor characteristics such as threshold voltage and conductance.

Formation of active regions with higher precision is becoming an increasingly important issue as the degree of integration of semiconductors increases.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a structure and manufacturing method of a semiconductor device in which a shallow diffusion region is formed.

That is, when forming the source and drain regions of the MIS transistor, trenches are formed in the semiconductor substrate by etching the regions. -The problem is solved by a manufacturing method and structure that consists of the steps of selectively epitaxially growing a crystalline insulating film in the liquid groove, and then selectively epitaxially growing a semiconductor doped with impurities on top of it. It will be done.

[Effect]

The impurity regions for the source and drain are formed on a crystalline insulator such as barium fluoride, separated from the silicon substrate, and are completely unaffected by subsequent processes such as heat treatment.

Therefore, the region and amount of impurities to be introduced can be controlled to desired values in separate processes.

〔Example〕

A first embodiment of the manufacturing method according to the present invention will be described in detail in the order of steps with reference to the drawings.

In FIG. 1(a), a gate insulating film (Si(h film) 3, polycrystalline silicon, 1/2) is laminated with a gate electrode layer made of a high melting point metal material on a p-type silicon substrate 1, and A glabellar insulating film 11 is grown on this, a gate electrode 2 is patterned, and grooves are formed in the source and drain regions 6.7 by etching.

Next, a crystalline insulating film 12, in this example barium fluoride (BaFz), is epitaxially grown on the inner surface of the region 6.7. BaF is a crystalline transparent insulator with a melting point of 1280°C.BaF is heated in a vacuum to near its melting point and epitaxially grown on a substrate heated to about 800°C. . This is shown in Figure 1.

Next, the bottoms of the source and drain regions and the tops of the walls are etched using an anisotropic etching (RIE) method. This is shown in Figure 1 (C1).

Next, silicon is selectively epitaxially grown on BaFz. At this time, P or As is doped at the same time. By controlling the doping amount, a semiconductor layer 13 made of silicon having an arbitrary impurity concentration can be obtained. This is shown in FIG. 1(d).

Furthermore, an insulating film (Sing), 14, is formed on the entire surface by CVD method.
When grown, the result shown in FIG. 1(e) is obtained.

A contact hole for an electrode is opened in the insulating film, and a wiring layer 15 is formed.
By forming this, the transistor shown in FIG. 1(f) is completed.

〔Effect of the invention〕

As explained above, by applying the structure and manufacturing method of the present invention, MISFE which requires a high degree of integration can be manufactured.
This contributes to improving the quality of T and manufacturing yield.

[Brief explanation of drawings]

FIG. 1 is a step-by-step cross-sectional view showing a method for manufacturing and using a MIS FET according to the present invention, and FIG. 2 is a step-by-step cross-sectional view showing a conventional method for manufacturing a MIS FET. In the drawings, 1 is a p-type silicon substrate, 2 is a gate electrode, 3 is a gate insulating film (SiO□ film), 4 is a field oxide film, 5 is a resist film, 6 is a source region, -7 is a drain region, and 8 is a drain region. n- region, 9 is a PSG film or SiO film, 10 is a contact hole, 11.14 is an insulating film (SiO! film), 12 is a crystalline insulating film (BaFz), 13 is a semiconductor ( doped silicon layer), 15 is a wiring layer, and 15 is a wiring layer. Misfire Q+=tr? lJ3 Mis FET ＾＠j
lT3f-e,i,7'Lth*tfrIi7M11
II' $11r! I.J.

Claims (2)

[Claims] (1) A semiconductor device characterized in that at least one of a source region (6) and a drain region (7) of a MIS transistor is embedded in a substrate in the order of an insulating film (12) and a conductor (13). (2) When forming the source region (6) and drain region (7) of the MIS transistor, grooves (6) are etched into the semiconductor substrate (1).
), (7), and selectively epitaxially growing an insulating film (12) in the groove, and selectively epitaxially growing a semiconductor (13) doped with impurities on the insulating film. A method for manufacturing a semiconductor device, comprising: