JPS61214527A - Low resistance n- type semiconductor thin film and manufacture thereof - Google Patents

Low resistance n- type semiconductor thin film and manufacture thereof

Info

Publication number
JPS61214527A
JPS61214527A JP60056660A JP5666085A JPS61214527A JP S61214527 A JPS61214527 A JP S61214527A JP 60056660 A JP60056660 A JP 60056660A JP 5666085 A JP5666085 A JP 5666085A JP S61214527 A JPS61214527 A JP S61214527A
Authority
JP
Japan
Prior art keywords
thin film
type semiconductor
zinc
single crystal
dialkyl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60056660A
Other languages
Japanese (ja)
Other versions
JPH0697651B2 (en
Inventor
Naoyuki Ito
直行 伊藤
Takashi Shimobayashi
隆 下林
Teruyuki Mizumoto
照之 水本
Norihisa Okamoto
岡本 則久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP5666085A priority Critical patent/JPH0697651B2/en
Publication of JPS61214527A publication Critical patent/JPS61214527A/en
Publication of JPH0697651B2 publication Critical patent/JPH0697651B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02557Sulfides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02576N-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To improve the reproducibility and the mass-productivity by a method wherein, when an N<-> type semiconductor layer to be an active layer or a closed layer of light emitting diode, laser diode etc. is formed, III group elements as donor impurity are contained in single crystal zinc sulfide thin film. CONSTITUTION:When an N<-> type semiconductor thin film is grown on a substrate made of GaAs, GaP and Si etc., the substrate is heated in a heating furnace fed with carrier gas containing material gas to be epitaxially grown. At this time, as for donor impurity, either one of Al, Ga, In or mixture of these elements is contained in single crystal zinc sulfide; or as for zinc source, dialkyl zinc and dialkyl sulfur or an additive produced from equimole mixture of dialkyl selenium are used; and as for sulfur source, hydrogen sulfide is used. Through these procedures, the dependability upon growing temperature may be made excellent enabling to emit dark blue light at room temperature when excited.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は発光ダイオード(LED)l レーザーダイオ
ード(KID)の活性層や閉じ込め層に用いられる低抵
抗ZnS単結晶薄膜及びその製造法に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a low resistance ZnS single crystal thin film used for the active layer or confinement layer of a light emitting diode (LED) or laser diode (KID), and a method for manufacturing the same.

〈発明の概要〉 本発明はLICD、LDの活性層や閉じ込め層に用いら
れる低抵抗n−型半導体薄膜において、硫化亜鉛単結晶
薄膜の中にドナー不純物としてl族元素を含むことを特
徴とし、硫化亜鉛を用いた発光デバイスの作製を可能と
するものである。
<Summary of the Invention> The present invention is characterized in that a low resistance n-type semiconductor thin film used for the active layer and confinement layer of LICD and LD includes a group I element as a donor impurity in a zinc sulfide single crystal thin film. This makes it possible to create light-emitting devices using zinc sulfide.

さらにその製造法において亜鉛ソースとしてジアルキル
亜鉛とジアルキル硫黄又はジアルキルセレンの等モル混
合によって得られる付加体を用い、硫黄ソースとして硫
化水素を用いるM、OCV D法により硫化亜鉛薄膜&
″!Imを影膚すスジ−■怖テ素の有機金属化合物を同
時供給することによシ、ドナー不純物の制御を行ないつ
つ、低抵抗n−型ZnS単結晶薄膜が製造できる様にし
たものである。
Furthermore, in the manufacturing method, a zinc sulfide thin film &
By simultaneously supplying an organometallic compound of a feared element, a low-resistance n-type ZnS single crystal thin film can be produced while controlling donor impurities. It is.

〈従来の技術〉 直接遷移型のワイド・ギャップ化合物半導体である硫化
亜鉛(ZrLS)は、室温において約λ6eVのバンド
ギャップを有し、短波長発光素子材料として注目されて
いる。これまで、種々の結晶成長法によシ高品位のZn
S単結晶薄膜の製造が試みられているが、今だデバイス
作製の可能なレベルの単結晶薄膜は得られていない◇こ
れは、構成元素であるZn、9ともに蒸気圧が高いため
、結晶成長過程において格子欠陥を内包しやすいことに
よる。格子欠陥を抑制するためKは、成長温度を低下す
ること75に1つの方法であるとされ、近年、低温にお
けるZnSの結晶成長が可能な、有機金j11気相熱分
解法(MOO’VD法)、分子線エピタキシー法(MI
E法)などが注目されている。
<Prior Art> Zinc sulfide (ZrLS), which is a direct transition type wide-gap compound semiconductor, has a band gap of about λ6 eV at room temperature, and is attracting attention as a material for short wavelength light emitting devices. Until now, high-grade Zn has been produced using various crystal growth methods.
Attempts have been made to produce a S single crystal thin film, but a single crystal thin film that can be used for device fabrication has not yet been obtained ◇ This is because the constituent elements Zn and 9 both have high vapor pressures, making crystal growth difficult. This is because lattice defects are easily included in the process. In order to suppress lattice defects, K is said to be one method to lower the growth temperature75, and in recent years, the organic gold j11 vapor phase pyrolysis method (MOO'VD method), which allows crystal growth of ZnS at low temperatures, has been developed. ), molecular beam epitaxy (MI
E method) etc. are attracting attention.

MOOVD法、MBIC法は、液相エピタキシャル成長
や、気相化学成長法(OVD法)に比べて低い温度での
結晶成長が可能で、しかも結晶成長過程が熱力学的平衡
状態から大きくずれた状態(非平衡状1m1)で進行す
るため、格子欠陥の発生や不純物の取り込み等が抑制す
ることが可能である。
MOOVD and MBIC methods allow crystal growth at lower temperatures than liquid phase epitaxial growth and chemical vapor deposition (OVD) methods, and they also allow crystal growth to occur in conditions where the crystal growth process deviates significantly from the thermodynamic equilibrium state ( Since the process proceeds in a non-equilibrium state (1 m1), it is possible to suppress the generation of lattice defects and the incorporation of impurities.

MOOVD法やMBE法によシ良質の単結晶薄膜が報告
されている。(Hえば :Tapanese J、Appl、Phys、、 2
2(19B3) ll583J、 0rys+ta工G
rowth、jj−(1981) 423 参照)Z 
n S f:Xr M DやLDに応用するためには、
導伝型や抵抗率を不純物のドーピングにより制御する必
要がある。前述の様に格子欠陥が内包されやすいZnB
では導伝型の制御や薄膜の低抵抗化が極めて難しく、特
にP−型ZnBの作製は、MOaVD法、MBK法を用
いても今だに得られる目途すらたっていない。
High quality single crystal thin films have been reported by MOOVD and MBE methods. (For example: Tapanese J, Appl, Phys, 2
2 (19B3) ll583J, 0rys+ta engineering G
rowth, jj- (1981) 423) Z
nS f:Xr MD In order to apply to LD and LD,
It is necessary to control the conductivity type and resistivity by doping with impurities. As mentioned above, ZnB easily contains lattice defects.
It is extremely difficult to control the conductivity type and reduce the resistance of the thin film, and in particular, there is no prospect of producing P-type ZnB even by using the MOaVD method or the MBK method.

Zn19はnatiマeにはn−型であるため、n−型
のZnS単結晶薄膜は比較的作製が容易であると考えら
れ幾つかの実験例が報告されている。以下に概略を述べ
る。
Since Zn19 is n-type in nature, it is thought that it is relatively easy to produce an n-type ZnS single crystal thin film, and several experimental examples have been reported. An outline is given below.

1、ジlfk亜鉛(DMZ )と硫化水素(H,8)を
用いた減圧MOOVD法により、Q&Aa上に成長させ
たZnSは、不純物の添加を行なわないアンドープの状
態で、しかもas−growの状態で低抵抗率を示した
。例えば成長温度300℃では比抵抗ρ中1Ωs1であ
った。
1. ZnS grown on Q&Aa by the low-pressure MOOVD method using dilfk zinc (DMZ) and hydrogen sulfide (H, 8) is in an undoped state without the addition of impurities, and in an as-grow state. showed low resistivity. For example, at a growth temperature of 300° C., the specific resistance ρ was 1Ωs1.

(第45回応用物理学会学術講演会 1984年秋季大会講演予稿集12a−3−5630ペ
ージ) 2211LSをソースとするMBE法罠よりGaAs上
に成長させたZnSはアンドープ、 am−gro■の
状態で、ρ+to畠Ω・1を呈した。ρが最小となる成
長温度は240c付近であった。
(45th Japan Society of Applied Physics Academic Conference 1984 Autumn Conference Proceedings 12a-3-5630) ZnS grown on GaAs by the MBE trap using 2211LS as a source is in an undoped, am-gro state. , ρ+toHatakeΩ・1. The growth temperature at which ρ was minimized was around 240°C.

(、T、 0rystal Growth it ((
1984)125. )IDMZとH,Sを用いた減圧
MOOVD法によりGaP上1cZユSを成長させる際
n−型ドーパントとしてトリエチルアルミニウム(TI
CAI)を導入し、A1を添加したZnS抗も変化して
おり、400℃において最小値を呈した。しかし400
℃においてすらρ中104Ω・1と大きく、デバイスに
応用できるレベルではなかった。
(, T, 0rystal Growth it ((
1984) 125. ) Triethylaluminum (TI
The ZnS resistance introduced with CAI) and added with A1 also changed, and exhibited a minimum value at 400°C. But 400
Even at ℃, the value of ρ was as large as 104Ω·1, which was not at a level that could be applied to devices.

(Hxtended ab*traats or th
e xsthOonferanae on 5olid
 St&te D・マ1assan4 Materia
ls、  Tokyo、 1983. pp、 349
−352)〈発明が解決しようとする問題点及び目的〉
ZnSは室温においてバンドギャップλ6sVを有する
ため、高品位のZnSは高抵抗を呈するはずである。従
って従来技術1.2に示したアンドープの低抵抗ZnS
は、結晶品位が低いために低抵抗になっていると考えら
れる。すなわち内包されている格子欠陥あるいは、成長
過程で、取り込まれる不純物が自由電子のソースになっ
ている可能性が強い。従って、比抵抗の再現性に乏しい
ことや、比抵抗を意図的に変化させることができないた
めに、デバイス作製への応用は難しい。
(Hxtended ab*traats or th
e xsthOonferanae on 5olid
St&te D・Maassan4 Materia
ls, Tokyo, 1983. pp, 349
-352) <Problem and purpose to be solved by the invention>
Since ZnS has a bandgap of λ6sV at room temperature, high-grade ZnS should exhibit high resistance. Therefore, the undoped low resistance ZnS shown in Prior Art 1.2
It is thought that the resistance is low due to the low crystal quality. In other words, there is a strong possibility that the included lattice defects or the impurities taken in during the growth process are sources of free electrons. Therefore, it is difficult to apply to device fabrication because the reproducibility of the resistivity is poor and the resistivity cannot be changed intentionally.

比抵抗を意図的に変化させる目的で、不純物のドーピン
グを行なりたのが、従来技術3であるが、得られたZn
Sはρ:104Ω・備と高抵抗のため、デバイスには応
用できていない。
In prior art 3, impurity doping was performed for the purpose of intentionally changing the resistivity, but the resulting Zn
S has a high resistance of ρ: 104Ω, so it cannot be applied to devices.

本発明の目的とするところは、これまでに実現されてい
ない不純物元素のドーピングにより技術的に制御された
低抵抗ZnS単結晶薄膜の作成にある。
An object of the present invention is to create a ZnS single crystal thin film with a low resistance technically controlled by doping with an impurity element, which has not been achieved so far.

〈問題点を解決するための手段〉 本発明においては、硫化亜鉛単結晶薄膜中にドナー不純
物としてl族元素を含むことを特徴とする。さらにその
製造法においては、亜鉛ソースとしてジアルキル亜鉛と
ジアルキル硫黄又はジアルキルセレンの等モル混合によ
って得られる付加体を用い、硫黄ソースとして硫化水素
を用いるM00VD法によりZnS単結晶薄膜を形成す
る際、l族元素の有機金属化合物を同時供給することに
より、低抵抗n−型ZrxF3単結晶薄膜の製造するこ
とを特徴とする。ここでいう付加体とは、ジアルキル亜
鉛とジアルキル硫黄(ジアルキルセレン)を等モル混合
した際酸−塩基及芯によりて得られる配位化合物のみな
らず、等モル混合を行なうた混合物をも含む。さらに該
混合物において、一部が配位化合物を形成し他がジアル
キル亜鉛とジアルキル硫黄(ジアルキルセレン)に解離
した状態で3つの化学種が共存している場合も含む。
<Means for Solving the Problems> The present invention is characterized in that a zinc sulfide single crystal thin film contains a group I element as a donor impurity. Furthermore, in the manufacturing method, when a ZnS single crystal thin film is formed by the M00VD method using an adduct obtained by equimolar mixing of dialkyl zinc and dialkyl sulfur or dialkyl selenium as a zinc source and using hydrogen sulfide as a sulfur source, l The method is characterized in that a low resistance n-type ZrxF3 single crystal thin film is produced by simultaneously supplying an organometallic compound of group elements. The adduct here includes not only a coordination compound obtained by acid-base and core when dialkyl zinc and dialkyl sulfur (dialkyl selenium) are mixed in equimolar amounts, but also a mixture obtained by equimolar mixing. Furthermore, in the mixture, the case where three chemical species coexist is also included, with some forming a coordination compound and the others dissociating into dialkylzinc and dialkylsulfur (dialkylselenium).

第1図は本発明において低抵抗n−型ZnS単結晶薄膜
を作製する際に用いるMOOVD装置の概略図である。
FIG. 1 is a schematic diagram of a MOOVD apparatus used in producing a low resistance n-type ZnS single crystal thin film in the present invention.

石英ガラス製の横型反応管■の内部にはSi。Si is inside the horizontal reaction tube made of quartz glass.

コーティングを施したグラフフィト製サセプター■が置
かれ、さらKその上には基板■が置かれている。反応炉
の側面から高周波加熱炉、赤外線炉。
A coated graphite susceptor (■) is placed, and a substrate (■) is placed on top of it. High frequency heating furnace, infrared furnace from the side of the reactor.

または抵抗加熱炉■などKより基板加熱を行なう。Alternatively, heat the substrate using a resistance heating furnace (2) or the like.

基板温度はグラファイト製サセプター■の中に埋め込ん
だ熱電対■によシモ二ターする。反応管は排気系■及び
廃ガス処理系■とパルプ■、■を介して接続されている
。Znソースであるジアルキル亜鉛とジアルキル硫黄又
はジアルキルセレンとの等モル混合によって得られる付
加体はバブラー■に封入されている。またl族元素のソ
ースとなる有機金属化合物2例えばトリエチルアルミニ
ウム(TEAL)、)リメテルガリウム(TMGa)。
The substrate temperature is monitored by a thermocouple embedded in a graphite susceptor. The reaction tube is connected to the exhaust system (2) and the waste gas treatment system (2) via the pulps (2) and (2). An adduct obtained by equimolar mixing of dialkylzinc, which is a Zn source, and dialkyl sulfur or dialkylselenium is enclosed in a bubbler (2). Also, an organometallic compound 2 that serves as a source of group I elements, such as triethylaluminum (TEAL), )rimethergallium (TMGa).

トリエチルインジウム(TIc工n)などはバブラー■
に封入されている。
Bubbler such as triethyl indium (TIc-n)
is enclosed in.

キャリアーガス及び硫化水素はそれぞれボンベ0゜■に
充填されている。純化装置@によりて精製されたキャリ
アーガス及び硫化水素はそれぞれマスフローコントロー
ラ@によシ流量制御される。バブラー[相]、■に封入
された付加体及び鳳族有機金属化合物は恒温槽[相]に
よシそれぞれ所定の温度に維持されている。
The carrier gas and hydrogen sulfide are each filled in a cylinder at 0°■. The carrier gas and hydrogen sulfide purified by the purifier are each controlled in flow rate by a mass flow controller. The adduct and the Otori group organometallic compound encapsulated in the bubbler [phase] and (2) are each maintained at a predetermined temperature by a constant temperature bath [phase].

このバブラーの中に適当量のキャリアーガスを導入、バ
ブリングを行なうことにより、所望の量の付加体及びl
族有機金属化合物が気化し供給される。バブラー[相]
、■及びボンベ0より供給された付加体2層族有機金属
化合物、硫化水素はそれぞれキャリアーガスによりて希
釈され合流した後、三方パルプ0を経て反応管■へ導入
される。三方パルプ■は原料ガスの反応管のへの導入及
び廃ガス処理系■への廃棄の切り換えを行なう。第1図
にはm型反広炉を承1−た九濤刑d広栢を外層イも基本
的構成は同じである。但し基板の回転機構を設けること
により、得られる膜の均一性を確保する必要がある。
By introducing an appropriate amount of carrier gas into this bubbler and performing bubbling, a desired amount of adduct and liter can be obtained.
Group organometallic compound is vaporized and supplied. bubbler [phase]
, (2) and the adduct two-layer group organometallic compound and hydrogen sulfide supplied from the cylinder 0 are each diluted with a carrier gas and combined, and then introduced into the reaction tube (2) through the three-way pulp 0. The three-way pulp (2) switches the introduction of the raw material gas into the reaction tube and the disposal to the waste gas treatment system (2). Figure 1 shows that the basic structure of the outer layer is the same as that of the M-type anti-broad furnace. However, it is necessary to ensure the uniformity of the obtained film by providing a rotation mechanism for the substrate.

以下l族元素を含む低抵抗n−型ZnS単結晶薄膜の具
体的な作製プロセスをa明する。
A specific manufacturing process for a low resistance n-type ZnS single crystal thin film containing group I elements will be explained below.

(100)面、(1oo)面から(lzo)面の方向に
5°あるいは2@のずれを有する面においてスライスし
、鏡面研磨したヒ化ガリウム(Q&A!I)1リン化ガ
リウム(GaP)及びシリコン(Sl)をトリクロルエ
チレン、アセトン、メタノールによる超音波洗浄を施し
た後にエツチングをする。
Gallium arsenide (Q&A!I), gallium monophosphide (GaP), which is sliced in a plane with a deviation of 5° or 2@ from the (100) plane, (1oo) plane to the (lzo) plane, and polished to a mirror finish. Silicon (Sl) is etched after being subjected to ultrasonic cleaning using trichloroethylene, acetone, and methanol.

エツチング条件は、以下の通りである。The etching conditions are as follows.

GaAa基板 H,So、 :H,O,:H,Q==3
: 1 : 1c体積比)室温で2w1n GaP基板 HOl:HNO,==31(体積比)室温
で30 aaaS1基板  HF:H,0==1:1(
体積比)  室温で 2 !11in純水を用いてエツ
チングを停止し、純水、メタノールにて洗浄した後、ダ
イフロン中に保存した。
GaAa substrate H, So, :H, O, :H, Q==3
: 1 : 1c volume ratio) 2w1n GaP substrate at room temperature HOl:HNO,==31 (volume ratio) 30 aaaS1 substrate HF:H,0==1:1(
Volume ratio) 2 at room temperature! Etching was stopped using 11 inches of pure water, washed with pure water and methanol, and then stored in a Daiflon.

基板は反応管へのセットを行なう直前にグイフロンより
取り出し、乾燥窒素ブローによりダイフロンを乾燥除夫
する。基ゼセットの後反応炉内を1 ” Torr程度
まで真空す1きし、系内に残留するガスを除く。キャリ
アーガスを導入して系内を常圧に戻した後1〜21 /
 win程度のキャリアーガスを流しつつ昇温を開始す
る。加熱には赤外線加熱炉を用いた。キャリアーガスと
しては、純度99、9999%のHeまたは純化装置を
通過させたR2を用いた。基板温度が所定温度に到達し
、安定した後、原料ガスの供給を開始し、低抵抗2nS
膜の成長を行とり。但し81基板の場合には、水素気流
中900℃、10分間程度の熱処理による基板表面の清
浄化を行なう必要がある。用いた付加体は純度99.9
999%のジメチル亜鉛とジエチル硫黄を等モル混合し
て得られる付加体である。この付加体は3o′cにおい
て2801111Hg程度の蒸気圧を有する。寵族元素
を含む有機金属化合物としてトリエチルアルミニウム(
rx*1)を用いた。
Immediately before setting the substrate in the reaction tube, the substrate is taken out from the Guyflon, and the Daiflon is dried and removed by dry nitrogen blowing. After setting the base, vacuum the inside of the reactor to about 1" Torr to remove residual gas in the system. After introducing carrier gas and returning the inside of the system to normal pressure,
Start heating up while flowing a carrier gas of about 100 mL. An infrared heating furnace was used for heating. As the carrier gas, He with a purity of 99.9999% or R2 passed through a purification device was used. After the substrate temperature reaches the predetermined temperature and becomes stable, the supply of raw material gas is started and the low resistance is 2nS.
Conduct membrane growth. However, in the case of an 81 substrate, it is necessary to clean the substrate surface by heat treatment at 900° C. for about 10 minutes in a hydrogen stream. The purity of the adduct used was 99.9.
It is an adduct obtained by mixing equimolar amounts of 999% dimethylzinc and diethyl sulfur. This adduct has a vapor pressure of about 2801111 Hg at 3 o'c. Triethylaluminum (
rx*1) was used.

成長条件は下記の通りである。The growth conditions are as follows.

、基板温度350″c、rl料導入口から基板までの距
離 20cm、  付加体バブリング量 −15℃にお
いて 30 r+l/min、  T E A 1バブ
リング量−10℃において 20 ml/win、  
Heで希釈した2%のH,3の供給量 200 ml/
win 、  キャリアーガスを含む全ガス流量 4.
5 l/mtn 、成長時間 90 win 所定の時間成長を行なった後、原料の供給をスト、グし
、冷却する。冷却中はHe又はR1を1〜21 / m
in流しておく。基板表面の熱エッチを防ぐためにHe
希釈2%のH,Sを50〜60 m4/+1n程度流し
ながら冷却してもよい。基板が室温にもど9たら反応炉
内を排気し、系内に残留する硫化水素を除去する。系内
金大気圧に戻した後に基板をとシ出す。この時に得られ
たZn5jAl膜の厚さは、約1μmであり、成長速度
は約0.7μm/hrであった。
, substrate temperature 350''c, distance from RL material inlet to substrate 20cm, adduct bubbling amount at -15°C 30 r+l/min, TEA 1 bubbling amount at -10°C 20 ml/win,
Supply amount of 2% H,3 diluted with He 200 ml/
win, total gas flow rate including carrier gas 4.
5 l/mtn, growth time 90 win After performing growth for a predetermined time, the supply of raw materials is stopped and cooled. During cooling, He or R1 is 1-21/m
Let it flow in. He was used to prevent thermal etching of the substrate surface.
Cooling may be performed while flowing diluted 2% H, S at about 50 to 60 m4/+1n. When the substrate returns to room temperature, the reactor is evacuated to remove hydrogen sulfide remaining in the system. After returning the system to atmospheric pressure, remove the substrate. The thickness of the Zn5jAl film obtained at this time was about 1 μm, and the growth rate was about 0.7 μm/hr.

以上のプロセスによシ作製したZn8:Al単結晶薄膜
は室温において比抵抗は約0.1〜Zo。
The Zn8:Al single crystal thin film produced by the above process has a specific resistance of about 0.1 to Zo at room temperature.

Q傭程度の値を再現性よく示した。成長温度を300℃
から400℃の間で変化させた時、比抵抗は330〜3
70℃付近で極小値を呈した。比抵抗の成長温度依存性
も再現性は良好であった。
It showed values on the order of Q with good reproducibility. Growth temperature 300℃
When the temperature was varied between
The minimum value was observed at around 70°C. The growth temperature dependence of resistivity also had good reproducibility.

成長温度350℃において、Tl!iAlの一10℃に
おけるバブリング量を変化させた時、15mJ/win
から25 m l / winの範囲ではバブリング量
の増加に伴ない、比抵抗の減少が観測されたが、15m
 l / winより少ない場合あるいは25 m l
 / minより多い場合には比抵抗の急激な増加がお
こった。
At a growth temperature of 350°C, Tl! When changing the bubbling amount of iAl at 10℃, 15mJ/win
A decrease in resistivity was observed as the amount of bubbling increased in the range from 15 m to 25 ml/win, but
If less than l/win or 25 ml
/min, a rapid increase in resistivity occurred.

得られた低抵抗ZnS膜をHe −Odレーザー(発振
波長32 s OA’)で励起した時に室温において強
い青色発光(発光波長460〜470・fl)を示した
When the obtained low-resistance ZnS film was excited with a He-Od laser (oscillation wavelength 32 s OA'), it exhibited strong blue light emission (emission wavelength 460-470·fl) at room temperature.

低抵抗Zn3膜の室温におけるフォトルミネッセンスス
ペクトルの1例を第2図に示す。
An example of the photoluminescence spectrum of a low resistance Zn3 film at room temperature is shown in FIG.

キセノンランプを用いて、励起波長を250  mから
40Qsniで変化させても、460〜470鱈付近の
発光以外は観測されなかった。以上の事実は本発明で作
製されるZnSjAm薄が極めて高品位であることを示
している。
Even when the excitation wavelength was changed from 250 m to 40 Qsni using a xenon lamp, no emission other than light emission around 460 to 470 m was observed. The above facts indicate that the ZnSjAm thin film produced by the present invention is of extremely high quality.

TmA 1G道入1.8L/−1〒虚写六!今zn S
II t[〒は少なくとも比抵抗10’Ω・1以上の高
抵抗を示し、470x付近の7オトルミネツセンスも観
測されなかった。比抵抗の減少及び7オトルミネツ七ン
スがA1のドーピングに由来していることがわかる。
TmA 1G Doinyu 1.8L/-1〒Kousa Roku! Now zn S
II t[〒 showed a high resistivity of at least 10'Ω·1 or more, and no 7 otoluminescence near 470x was observed. It can be seen that the decrease in resistivity and the 7 ounces are due to the doping of A1.

上記の説明では付加体としてジメチル亜鉛とジエチル硫
黄の等モル混合によシ得られるものくついて述べたが、
この他、ジメチル亜鉛とジメチル硫黄(20℃における
蒸気圧約120m)Ig)。
In the above explanation, we have described some adducts that can be obtained by equimolar mixing of dimethylzinc and diethyl sulfur.
In addition, dimethylzinc and dimethylsulfur (vapor pressure at 20°C: about 120mIg).

ジエチル亜鉛とジメチル硫黄(30’Cにおける蒸気圧
約88龍Hg)及びジエチル亜鉛とジエチル硫黄(20
℃における蒸気圧約151111Hg)などの組み合せ
による付加体も、ジアルキル亜鉛とジアルキル硫黄の等
モル混合によって得られ、ジメチル亜鉛とジエチル硫黄
の付加体と同様にして使用でき、本発明の範ちゅうに入
るものである。また成長温度400℃以下では、はとん
ど分解しない、ジメチルセレン、ジエチルセレンと、ジ
メチル亜鉛、ジエチル亜鉛の組み合せによって得られる
4種類の付加体も、アルキルセレンの付加体と同じく使
用が可能であシ、本発明に含まれるものでおる。
Diethyl zinc and dimethyl sulfur (vapor pressure approximately 88 Hg at 30'C) and diethyl zinc and diethyl sulfur (vapor pressure approximately 88 Hg at 30'C)
Combination adducts, such as those obtained by equimolar mixing of dialkyl zinc and dialkyl sulfur (with a vapor pressure of about 151,111 Hg at °C), can also be used in the same manner as the adducts of dimethylzinc and diethyl sulfur, and are within the scope of the present invention. It is. In addition, four types of adducts obtained by combining dimethylselenium, diethylselenium, dimethylzinc, and diethylzinc, which do not decompose at growth temperatures of 400°C or lower, can also be used in the same way as alkylselenium adducts. However, it is included in the present invention.

以上の説明から容易に類推できる如く、znSへのA1
の添加と同様にして、Ga、Inの添加も、対応する有
機金属化合物、例えばトリエチルガリウム(沸点=14
3℃)、トリエチルインジウム(沸点=184℃)を用
いることにより可能である。バブリング温度における蒸
気圧とバブリングガスの流量から計算される供給量がト
リエチルアルミニウムのそれと等しいとき、得られたZ
nS:Ga、ZnS:工nは、ZnS:Alと同様な電
気的特性を示した。本発明により、ドーピングにより制
御された低抵抗ZnS単結晶薄膜の製造が付加体をZn
ソースとするMOOVD法により可能となった。
As can be easily inferred from the above explanation, A1 to znS
Similarly to the addition of Ga, In, the corresponding organometallic compound, such as triethylgallium (boiling point = 14
3°C) and triethyl indium (boiling point = 184°C). When the supply amount calculated from the vapor pressure at the bubbling temperature and the bubbling gas flow rate is equal to that of triethylaluminum, the obtained Z
nS:Ga, ZnS:N exhibited electrical characteristics similar to ZnS:Al. According to the present invention, the production of low-resistivity ZnS single crystal thin films controlled by doping is possible by adding Zn
This was made possible by the MOOVD method used as a source.

以下、本発明で製造された低抵抗ZnSのデバイス応用
例として、青色発光素子の作製について述べる。
The production of a blue light emitting element will be described below as an example of device application of the low resistance ZnS produced according to the present invention.

1、(Zoo)面でスライスしたn−型GaAa基板上
に、上述のMOOVDプロセスに従りてA1ドープの低
抵抗Zn8層を約3/Jl成長させる。。
1. On an n-type GaAa substrate sliced along the (Zoo) plane, an A1-doped low-resistance Zn8 layer is grown to a thickness of about 3/Jl according to the MOOVD process described above. .

2 基板裏面にA u−G o (G o = 12 
vrt−%)を約200 OA’程度蒸着後、不活性雰
囲気中350℃において5〜10 minの熱処理を施
して、GaAs基板へのオーム性接触を形成する。
2 A u-G o (G o = 12
vrt-%) to about 200 OA', heat treatment is performed at 350° C. for 5 to 10 minutes in an inert atmosphere to form an ohmic contact to the GaAs substrate.

λ スパッタにより約100 OA’のSin、をZn
S上に積層する。
λ Sputtering approximately 100 OA' of Sin and Zn
Stack it on S.

4、S10.上に厚さ300〜500A!程度のAu半
透明電極を積層する。
4, S10. Thickness 300-500A on top! Au translucent electrodes of about 100 mL are laminated.

以上の様にして作製されたM工S構造を有する素子の表
面Au電極と、Q&A11基板に設は九オーム性接触の
間に順方向のバイアス電圧を印加すると、1〜2v付近
から発光が観測された。発光スペクトルは室温において
460〜4701111付近にピークを有し、発光強度
は素子を流れる電流に比例して増大した。量子効率は約
10−1であった。
When a forward bias voltage is applied between the surface Au electrode of the device having the M/S structure fabricated as described above and the 9 ohm contact provided on the Q&A11 substrate, light emission is observed from around 1 to 2 V. It was done. The emission spectrum had a peak around 460 to 4701111 at room temperature, and the emission intensity increased in proportion to the current flowing through the device. The quantum efficiency was approximately 10-1.

本発明により形成されたZn8:Alを発光層とするM
工8型素子において青色発光が確認されたことによシ、
本発明によって製造される低抵抗znSがデバイス作製
にかなう品位であることが実証された。
M having a light emitting layer of Zn8:Al formed according to the present invention
Due to the confirmation of blue light emission in the 8-type device,
It was demonstrated that the low resistance znS manufactured by the present invention has a quality suitable for device fabrication.

本発明に基づく低抵抗n−型半導体薄膜は、上記MIS
型青色発光素子に限らず、p−型Zn8との積層による
ホモ接合素子をはじめとして、他の化合物半導体との間
に形成されるペテロ接合を利用したLED、LDなどへ
も適当することは容易である。
The low resistance n-type semiconductor thin film based on the present invention can be applied to the above-mentioned MIS.
It is easy to apply not only to type blue light emitting devices, but also to homojunction devices formed by stacking with p-type Zn8, as well as LEDs, LDs, etc. that utilize petrojunctions formed between other compound semiconductors. It is.

〈発明の効果〉 以上述べた様に、本発明によれば、亜鉛ソースとしてジ
アルキル亜鉛とジアルキル硫黄又はジアルキルセレンの
等モル混合によって得られる付加体を用い硫黄ソースと
してH,Sを用いるMOOVD法によJZnS単結晶薄
膜を形成する際、l族元素の有機金属化合物を同時供給
することにより、デバイスへの応用が可能な低抵抗n−
型ZnS単結晶薄膜の作製が実現した。しかもドナー不
純物の制御を行ないつつ該薄膜を製造することが可能と
なった。再現性、量産性に優れたMOOVD法を用いた
本発明が、表示用として極めて重要な主として青色領域
のLED、LD用の活性層、とじ込め層の製造に寄与す
るところは非常に大きいと確信する。
<Effects of the Invention> As described above, according to the present invention, an adduct obtained by equimolar mixing of dialkyl zinc and dialkyl sulfur or dialkyl selenium is used as a zinc source and H and S are used as sulfur sources in the MOOVD method. When forming a JZnS single crystal thin film, by simultaneously supplying an organometallic compound of group I elements, a low resistance n-
The fabrication of a type ZnS single crystal thin film was realized. Furthermore, it has become possible to manufacture the thin film while controlling donor impurities. We are confident that the present invention, which uses the MOOVD method with excellent reproducibility and mass production, will greatly contribute to the production of active layers and containment layers for LEDs and LDs, which are mainly in the blue region, which are extremely important for display purposes. do.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明において用いるM00VD装置の概略図 1 石英ガラス製反応管  2  SiOコーティング
を施したグラファイト製サセプター3 基板  4 高
周波加熱炉又は赤外線炉又は抵抗加熱炉  5 熱電対
  6 排気系7 廃ガス処理系  8.9 パルプ 10  付加体の入ったバブラー  11璽族元素の有
機金属化合物の入ったバブラー  12  キャリアー
ガスの入りたボンベ  13  硫化水素の入ったボン
ベ  14  ガス純化装置  15  マスフロコン
トローラ  16  ffl温槽17  三方パルプ 
 18  パルプ 第2図は本発明により製造された低抵抗ZnS:A1の
7オトルミネッセンススペクトル第1図 双+い− 第2図
FIG. 1 is a schematic diagram of the M00VD apparatus used in the present invention 1 Reaction tube made of quartz glass 2 Susceptor made of graphite coated with SiO 3 Substrate 4 High frequency heating furnace, infrared furnace, or resistance heating furnace 5 Thermocouple 6 Exhaust system 7 Waste gas Processing system 8.9 Pulp 10 Bubbler containing adduct 11 Bubbler containing organometallic compound of group element 12 Cylinder containing carrier gas 13 Cylinder containing hydrogen sulfide 14 Gas purification device 15 Mass flow controller 16 FFL temperature Tank 17 Three-way pulp
18 Pulp Figure 2 shows the 7 otoluminescence spectrum of low-resistivity ZnS:A1 produced according to the present invention.

Claims (4)

【特許請求の範囲】[Claims] (1)硫化亜鉛単結晶薄膜の中に、ドナー不純物として
III族元素を含むことを特徴とした低抵抗n−型半導体
薄膜。
(1) As a donor impurity in zinc sulfide single crystal thin film
A low resistance n-type semiconductor thin film characterized by containing a group III element.
(2)特許請求の範囲第1項において、ドナー不純物と
して含まれるIII族元素が、Al、Ga、Inのいずれ
かひとつ又はそれ以上であることを特徴とした低抵抗n
−型半導体薄膜。
(2) In claim 1, a low resistance n characterized in that the Group III element contained as a donor impurity is one or more of Al, Ga, and In.
- type semiconductor thin film.
(3)亜鉛ソースとしてジアルキル亜鉛とジアルキル硫
黄又はジアルキルセレンの等モル混合によって得られる
付加体を用い、硫黄ソースとして硫化水素を用いる有機
金属気相熱分解法(MOCVD法)により硫化亜鉛薄膜
を形成する際、III族元素の有機金属化合物を同時供給
することを特徴とした低抵抗n−型半導体薄膜の製造法
(3) Forming a zinc sulfide thin film by metal organic vapor phase pyrolysis (MOCVD) using hydrogen sulfide as the sulfur source and using an adduct obtained by equimolar mixture of dialkylzinc and dialkylsulfur or dialkylselenium as the zinc source. A method for producing a low-resistance n-type semiconductor thin film, which comprises simultaneously supplying an organometallic compound of a group III element.
(4)特許請求の範囲第3項において、硫化亜鉛薄膜を
形成する際に同時供給する有機金属化合物がAl、Ga
、Inの有機金属化合物のいずれかひとつ又はそれ以上
であることを特徴とした低抵抗n−型半導体薄膜の製造
法。
(4) In claim 3, the organometallic compound simultaneously supplied when forming the zinc sulfide thin film is Al, Ga, etc.
A method for producing a low-resistance n-type semiconductor thin film, characterized in that it is made of one or more of organometallic compounds of , In.
JP5666085A 1985-03-20 1985-03-20 Method for producing low resistance n-type zinc sulfide thin film Expired - Lifetime JPH0697651B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5666085A JPH0697651B2 (en) 1985-03-20 1985-03-20 Method for producing low resistance n-type zinc sulfide thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5666085A JPH0697651B2 (en) 1985-03-20 1985-03-20 Method for producing low resistance n-type zinc sulfide thin film

Publications (2)

Publication Number Publication Date
JPS61214527A true JPS61214527A (en) 1986-09-24
JPH0697651B2 JPH0697651B2 (en) 1994-11-30

Family

ID=13033542

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH0697651B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6393189A (en) * 1986-10-08 1988-04-23 Seiko Epson Corp Semiconductor light-emitting device and manufacture thereof
WO2003095700A1 (en) * 2002-05-10 2003-11-20 Umk Technologies Co., Ltd. Method for high purity purification of high functional material and method for deposition of high functional material by mass separation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6393189A (en) * 1986-10-08 1988-04-23 Seiko Epson Corp Semiconductor light-emitting device and manufacture thereof
WO2003095700A1 (en) * 2002-05-10 2003-11-20 Umk Technologies Co., Ltd. Method for high purity purification of high functional material and method for deposition of high functional material by mass separation method

Also Published As

Publication number Publication date
JPH0697651B2 (en) 1994-11-30

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