JPS6121012B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly accurate and stable digital phase shifter.

A conventional phase shifter uses, for example, a tapped delay line as shown in FIG.

That is, a signal supplied from input terminal 1 is supplied to terminator 3 via delay line 2,
The delayed signal from the tap 4 was output to the output terminal 5, but it had the disadvantage that it was difficult to set the tap position with high accuracy and stability.

This invention was made in view of these points, and by making it possible to set the phase digitally, the setting accuracy is high, and the amount of phase shift does not change due to temperature etc. It is a highly accurate and stable digital system. It provides a phase shifter.

An embodiment of the invention shown in FIG. 2 will be described below. In the figure, 10 is an input terminal, 11 is a first frequency converter, which is composed of a circuit including a phase-locked loop, and multiplies the frequency of the input signal by (n/n-1) (n is an integer, the same applies hereinafter). While converting, the phase is also controlled to be constant in phase synchronization,
12 is a first counter that counts down the input signal to 1/n, and 13 is a second counter that has a function of counting down the input signal to 1/n and a preset that is prepared in advance by an external control signal. Information (n-p) (p is an integer, n-p>
14 is a phase setting for setting preset information to be loaded into the second counter, and 15 is a second frequency converter for phase synchronization. 16 is an output terminal that converts the frequency of the second counter output signal (n-1/n×n) times the frequency (n-1/n×n) and is controlled to be constant in synchronization with the phase of the second counter output signal, which is configured by a circuit including a loop. It is.

Next, the operation will be explained. The signal applied to the input terminal 11 (frequency f=n-1/nfo, phase θ=0) is converted by (n/n-1) times (f= fo, θ=0) is applied to the first counter 12 and the second counter 13.
Here, the second counter 13 has a phase setter 14.
Since the information preset in the first counter 12 is connected and operated so as to be loaded by the output of the first counter 12, the operating states of the first counter 12 and the second counter 13 have the relationship shown in FIG. becomes.

That is, as shown in FIG. 3A, the first counter 12 changes its contents to (000...
), the count is incremented to (111...), and the next input signal of (111...) causes the count to go up to (000...).
), and one output signal is generated as shown in FIG. 3B.

The second counter 13, like the first counter 12, counts up its contents from (000...) to (111...) depending on the input signal, but the output of the first counter 12 Signal (Figure 2B)
As a result, the contents of the phase setter 14 (indicated by (n-p) in FIG. 3C) are loaded into the second counter 13.
The contents of the counter 13 are set to the same contents as the phase setter 14, and the set value is used as a starting point and is subsequently counted up based on the input signal.

If the setting content of the phase setter 14 is (n-p), the second counter 13 will output one output when it counts p after this setting content is loaded, so the second counter 12 will output one output. The output timing is a position delayed by (2π×p/n) radians from the timing when the first counter 12 outputs the output.

That is, when the output of the second counter 13 is compared with the output of the first counter 12, the signals have the same frequency but a phase shift of (2π×p/n) radians.

This signal is converted to (n×
When converting the frequency by a factor of n-1/n), a signal with a frequency f of f=n/n-1fo and a phase θ of {θ=2π p/n)} in radians is obtained at the output terminal 16. Become.

That is, it is possible to obtain a signal having the same frequency as the signal at the input terminal 10, but having a phase shifted by 2π (p/n) radians.

Here, since the phase shift amount (2πp/n) rad is determined by the setting value of the phase setter 14, the phase shift amount can be digitally set finely. (For example, if the first and second counters are constituted by 10-bit counters, n=1024, which can be set in steps of 2π/1024 radians) and also does not fluctuate with respect to temperature changes. In other words, a highly accurate and highly stable phase shifter can be obtained.

Above, the frequency conversion ratio of the first frequency converter 11 was explained as (n/n-1), but this can be changed to (n/n+
1), (n/n±m or n±m/n (m: integer). In this case, the frequency conversion ratio of the second frequency converter is n(n/n+1, n(n±m /n=(n+m).

As described above, the present invention provides a first frequency conversion amount for frequency converting an input signal to a frequency (n/n±m) or n±m/n) times the input frequency in phase synchronization, and this frequency converter. a first counter that counts an output signal of the first counter; a second counter that is controlled by the first counter and is loaded with a preset value and uses the input signal as a counter; A second frequency converter converts the frequency in phase synchronization with the same frequency as the signal, and the output of the second frequency converter has the same frequency as the input signal but a phase shift corresponding to the preset value. Since the digital phase shift signal is obtained, it is possible to perform highly accurate and highly stable digital phase shifting.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional phase shifter, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing the relationship between the operation timings of each part. 11: first frequency converter, 12: first counter, 13: second counter, 14: phase setting value, 15: second frequency converter.

Claims (1)

[Claims] 1. The input signal is n/n±m times its frequency or n±m/
a first frequency converter that converts the frequency in phase synchronization with a frequency multiplied by n (m, n is an integer); a first counter that counts down the signal from the first frequency converter to 1/n; a second counter controlled by the output signal of the first counter to load a preset digital setting value and count down the signal from the first frequency converter to 1/n; and the output signal of the second counter. a second frequency converter that frequency-converts this signal to the same frequency as the input signal in phase synchronization with the input signal.